authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-11-10 16:38:23+01:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2025-11-10 16:38:23+01:00
logd182c7e3bc20b8f90bc43ed615a3faa43287a3e4
treee66978f11f5650000f49c4604a68c05d3c22110b
parent966809862fb0dee03fbb79eb6b907bb801a5176b
parentf34b5ce28844cdf3ec66c1f6b9feb3bcdae6434c
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #25886 from alexrp/kvx

beginnings of KVX target support (via CBE)

16 files changed, 776 insertions(+), 7 deletions(-)

lib/compiler/aro/aro/target.zig+4-1
......@@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
477477 .ve,
478478 .bpfel,
479479 .bpfeb,
480 .kvx,
480481 .s390x,
481482 => return null,
482483
......@@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
551552 .nvptx64,
552553 .wasm64,
553554 .spirv64,
555 .kvx,
554556 .loongarch64,
555557 .mips64,
556558 .mips64el,
......@@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
636638 .wasm32 => "wasm32",
637639 .wasm64 => "wasm64",
638640 .ve => "ve",
639 // Note: propeller1, kalimba and or1k are not supported in LLVM; this is the Zig arch name
641 // Note: propeller1, kalimba, kvx, and or1k are not supported in LLVM; this is the Zig arch name
640642 .kalimba => "kalimba",
643 .kvx => "kvx",
641644 .propeller => "propeller",
642645 .or1k => "or1k",
643646 };
lib/std/Target.zig+33-2
......@@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig");
710710pub const hexagon = @import("Target/hexagon.zig");
711711pub const hppa = @import("Target/generic.zig");
712712pub const kalimba = @import("Target/generic.zig");
713pub const kvx = @import("Target/kvx.zig");
713714pub const lanai = @import("Target/lanai.zig");
714715pub const loongarch = @import("Target/loongarch.zig");
715716pub const m68k = @import("Target/m68k.zig");
......@@ -1035,7 +1036,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
10351036 .aarch64, .aarch64_be => .AARCH64,
10361037 .alpha => .ALPHA,
10371038 .amdgcn => .AMDGPU,
1038 .arc, .arceb => .ARC_COMPACT,
1039 .arc, .arceb => .ARC_COMPACT2,
10391040 .arm, .armeb, .thumb, .thumbeb => .ARM,
10401041 .avr => .AVR,
10411042 .bpfeb, .bpfel => .BPF,
......@@ -1043,6 +1044,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
10431044 .hexagon => .QDSP6,
10441045 .hppa, .hppa64 => .PARISC,
10451046 .kalimba => .CSR_KALIMBA,
1047 .kvx => .KVX,
10461048 .lanai => .LANAI,
10471049 .loongarch32, .loongarch64 => .LOONGARCH,
10481050 .m68k => .@"68K",
......@@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
11051107 .hppa,
11061108 .hppa64,
11071109 .kalimba,
1110 .kvx,
11081111 .lanai,
11091112 .m68k,
11101113 .microblaze,
......@@ -1310,6 +1313,7 @@ pub const Cpu = struct {
13101313 hppa,
13111314 hppa64,
13121315 kalimba,
1316 kvx,
13131317 lanai,
13141318 loongarch32,
13151319 loongarch64,
......@@ -1385,6 +1389,7 @@ pub const Cpu = struct {
13851389 hexagon,
13861390 hppa,
13871391 kalimba,
1392 kvx,
13881393 lanai,
13891394 loongarch,
13901395 m68k,
......@@ -1420,6 +1425,7 @@ pub const Cpu = struct {
14201425 .hexagon => .hexagon,
14211426 .hppa, .hppa64 => .hppa,
14221427 .kalimba => .kalimba,
1428 .kvx => .kvx,
14231429 .lanai => .lanai,
14241430 .loongarch32, .loongarch64 => .loongarch,
14251431 .m68k => .m68k,
......@@ -1623,6 +1629,7 @@ pub const Cpu = struct {
16231629 .csky,
16241630 .hexagon,
16251631 .kalimba,
1632 .kvx,
16261633 .loongarch32,
16271634 .loongarch64,
16281635 .microblazeel,
......@@ -1847,6 +1854,10 @@ pub const Cpu = struct {
18471854 .hppa64_elf,
18481855 => &.{.hppa64},
18491856
1857 .kvx_lp64,
1858 .kvx_ilp32,
1859 => &.{.kvx},
1860
18501861 .lanai_sysv,
18511862 => &.{.lanai},
18521863
......@@ -1936,6 +1947,7 @@ pub const Cpu = struct {
19361947 return switch (arch) {
19371948 .amdgcn => &amdgcn.cpu.gfx600,
19381949 .avr => &avr.cpu.avr1,
1950 .kvx => &kvx.cpu.coolidge_v1,
19391951 .loongarch32 => &loongarch.cpu.generic_la32,
19401952 .loongarch64 => &loongarch.cpu.generic_la64,
19411953 .mips, .mipsel => &mips.cpu.mips32,
......@@ -1987,6 +1999,7 @@ pub const Cpu = struct {
19871999 .bpfel, .bpfeb => &bpf.cpu.v3,
19882000 .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
19892001 .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
2002 .kvx => &kvx.cpu.coolidge_v2,
19902003 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
19912004 .loongarch64 => &loongarch.cpu.la64v1_0,
19922005 .m68k => &m68k.cpu.M68000,
......@@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct {
24402453 .aarch64,
24412454 .aarch64_be,
24422455 .hexagon,
2456 .kvx,
24432457 .m68k,
24442458 .microblaze,
24452459 .microblazeel,
......@@ -2666,16 +2680,20 @@ pub const DynamicLinker = struct {
26662680 },
26672681
26682682 .netbsd => switch (cpu.arch) {
2683 .alpha,
26692684 .arm,
26702685 .armeb,
26712686 .aarch64,
26722687 .aarch64_be,
2688 .hppa,
26732689 .m68k,
26742690 .mips,
26752691 .mipsel,
26762692 .mips64,
26772693 .mips64el,
26782694 .powerpc,
2695 .sh,
2696 .sheb,
26792697 .sparc,
26802698 .sparc64,
26812699 .x86,
......@@ -2685,13 +2703,17 @@ pub const DynamicLinker = struct {
26852703 },
26862704
26872705 .openbsd => switch (cpu.arch) {
2706 .alpha,
26882707 .arm,
26892708 .aarch64,
2709 .hppa,
26902710 .mips64,
26912711 .mips64el,
26922712 .powerpc,
26932713 .powerpc64,
26942714 .riscv64,
2715 .sh,
2716 .sheb,
26952717 .sparc64,
26962718 .x86,
26972719 .x86_64,
......@@ -2817,6 +2839,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
28172839 .bpfeb,
28182840 .bpfel,
28192841 .hppa64,
2842 .kvx,
28202843 .loongarch64,
28212844 .mips64,
28222845 .mips64el,
......@@ -2870,6 +2893,7 @@ pub fn stackAlignment(target: *const Target) u16 {
28702893 .ve,
28712894 .wasm32,
28722895 .wasm64,
2896 .x86_64,
28732897 => return 16,
28742898 // Some of the following prongs should really be testing the ABI, but our current `Abi` enum
28752899 // can't handle that level of nuance yet.
......@@ -2882,7 +2906,7 @@ pub fn stackAlignment(target: *const Target) u16 {
28822906 .riscv64be,
28832907 => if (!target.cpu.has(.riscv, .e)) return 16,
28842908 .x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16,
2885 .x86_64 => return 16,
2909 .kvx => return 32,
28862910 else => {},
28872911 }
28882912
......@@ -3375,6 +3399,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
33753399 .aarch64_be,
33763400 .alpha,
33773401 .hppa64,
3402 .kvx,
33783403 .loongarch32,
33793404 .loongarch64,
33803405 .mips64,
......@@ -3482,6 +3507,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
34823507 .aarch64_be,
34833508 .alpha,
34843509 .hppa64,
3510 .kvx,
34853511 .loongarch32,
34863512 .loongarch64,
34873513 .mips64,
......@@ -3557,6 +3583,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
35573583 .bpfel,
35583584 .bpfeb,
35593585 .hppa64,
3586 .kvx,
35603587 .loongarch64,
35613588 .mips64,
35623589 .mips64el,
......@@ -3626,6 +3653,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
36263653 .hppa => .{ .hppa_elf = .{} },
36273654 .hppa64 => .{ .hppa64_elf = .{} },
36283655 .kalimba => null,
3656 .kvx => switch (target.abi) {
3657 .ilp32 => .{ .kvx_ilp32 = .{} },
3658 else => .{ .kvx_lp64 = .{} },
3659 },
36293660 .lanai => .{ .lanai_sysv = .{} },
36303661 .loongarch64 => .{ .loongarch64_lp64 = .{} },
36313662 .loongarch32 => .{ .loongarch32_ilp32 = .{} },
lib/std/Target/kvx.zig created+64
......@@ -0,0 +1,64 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 v3_1,
9 v3_2,
10 v4_1,
11};
12
13pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
14pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
15pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
16pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
17
18pub const all_features = blk: {
19 const len = @typeInfo(Feature).@"enum".fields.len;
20 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
21 var result: [len]CpuFeature = undefined;
22 result[@intFromEnum(Feature.v3_1)] = .{
23 .llvm_name = null,
24 .description = "Enable ISA v3.1",
25 .dependencies = featureSet(&[_]Feature{}),
26 };
27 result[@intFromEnum(Feature.v3_2)] = .{
28 .llvm_name = null,
29 .description = "Enable ISA v3.2",
30 .dependencies = featureSet(&[_]Feature{
31 .v3_1,
32 }),
33 };
34 result[@intFromEnum(Feature.v4_1)] = .{
35 .llvm_name = null,
36 .description = "Enable ISA v4.1",
37 .dependencies = featureSet(&[_]Feature{
38 .v3_2,
39 }),
40 };
41 const ti = @typeInfo(Feature);
42 for (&result, 0..) |*elem, i| {
43 elem.index = i;
44 elem.name = ti.@"enum".fields[i].name;
45 }
46 break :blk result;
47};
48
49pub const cpu = struct {
50 pub const coolidge_v1: CpuModel = .{
51 .name = "coolidge_v1",
52 .llvm_name = null,
53 .features = featureSet(&[_]Feature{
54 .v3_1,
55 }),
56 };
57 pub const coolidge_v2: CpuModel = .{
58 .name = "coolidge_v2",
59 .llvm_name = null,
60 .features = featureSet(&[_]Feature{
61 .v3_2,
62 }),
63 };
64};
lib/std/builtin.zig+4
......@@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) {
274274 /// The standard `hppa64` calling convention.
275275 hppa64_elf: CommonOptions,
276276
277 kvx_lp64: CommonOptions,
278 kvx_ilp32: CommonOptions,
279
277280 /// The standard `lanai` calling convention.
278281 lanai_sysv: CommonOptions,
279282
......@@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) {
959962 .csky,
960963 .hppa,
961964 .hppa64,
965 .kvx,
962966 .lanai,
963967 .loongarch32,
964968 .loongarch64,
lib/std/builtin/assembly.zig+529
......@@ -857,6 +857,535 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
857857 f14: bool = false,
858858 f15: bool = false,
859859 },
860 .kvx => packed struct {
861 /// Whether the inline assembly code may perform stores to memory
862 /// addresses other than those derived from input pointer provenance.
863 memory: bool = false,
864
865 cs: bool = false,
866
867 ra: bool = false,
868
869 ls: bool = false,
870 le: bool = false,
871 lc: bool = false,
872
873 r0: bool = false,
874 r1: bool = false,
875 r2: bool = false,
876 r3: bool = false,
877 r4: bool = false,
878 r5: bool = false,
879 r6: bool = false,
880 r7: bool = false,
881 r8: bool = false,
882 r9: bool = false,
883 r10: bool = false,
884 r11: bool = false,
885 r12: bool = false,
886 r13: bool = false,
887 r14: bool = false,
888 r15: bool = false,
889 r16: bool = false,
890 r17: bool = false,
891 r18: bool = false,
892 r19: bool = false,
893 r20: bool = false,
894 r21: bool = false,
895 r22: bool = false,
896 r23: bool = false,
897 r24: bool = false,
898 r25: bool = false,
899 r26: bool = false,
900 r27: bool = false,
901 r28: bool = false,
902 r29: bool = false,
903 r30: bool = false,
904 r31: bool = false,
905 r32: bool = false,
906 r33: bool = false,
907 r34: bool = false,
908 r35: bool = false,
909 r36: bool = false,
910 r37: bool = false,
911 r38: bool = false,
912 r39: bool = false,
913 r40: bool = false,
914 r41: bool = false,
915 r42: bool = false,
916 r43: bool = false,
917 r44: bool = false,
918 r45: bool = false,
919 r46: bool = false,
920 r47: bool = false,
921 r48: bool = false,
922 r49: bool = false,
923 r50: bool = false,
924 r51: bool = false,
925 r52: bool = false,
926 r53: bool = false,
927 r54: bool = false,
928 r55: bool = false,
929 r56: bool = false,
930 r57: bool = false,
931 r58: bool = false,
932 r59: bool = false,
933 r60: bool = false,
934 r61: bool = false,
935 r62: bool = false,
936 r63: bool = false,
937
938 a0: bool = false,
939 a1: bool = false,
940 a2: bool = false,
941 a3: bool = false,
942 a4: bool = false,
943 a5: bool = false,
944 a6: bool = false,
945 a7: bool = false,
946 a8: bool = false,
947 a9: bool = false,
948 a10: bool = false,
949 a11: bool = false,
950 a12: bool = false,
951 a13: bool = false,
952 a14: bool = false,
953 a15: bool = false,
954 a16: bool = false,
955 a17: bool = false,
956 a18: bool = false,
957 a19: bool = false,
958 a20: bool = false,
959 a21: bool = false,
960 a22: bool = false,
961 a23: bool = false,
962 a24: bool = false,
963 a25: bool = false,
964 a26: bool = false,
965 a27: bool = false,
966 a28: bool = false,
967 a29: bool = false,
968 a30: bool = false,
969 a31: bool = false,
970 a32: bool = false,
971 a33: bool = false,
972 a34: bool = false,
973 a35: bool = false,
974 a36: bool = false,
975 a37: bool = false,
976 a38: bool = false,
977 a39: bool = false,
978 a40: bool = false,
979 a41: bool = false,
980 a42: bool = false,
981 a43: bool = false,
982 a44: bool = false,
983 a45: bool = false,
984 a46: bool = false,
985 a47: bool = false,
986 a48: bool = false,
987 a49: bool = false,
988 a50: bool = false,
989 a51: bool = false,
990 a52: bool = false,
991 a53: bool = false,
992 a54: bool = false,
993 a55: bool = false,
994 a56: bool = false,
995 a57: bool = false,
996 a58: bool = false,
997 a59: bool = false,
998 a60: bool = false,
999 a61: bool = false,
1000 a62: bool = false,
1001 a63: bool = false,
1002
1003 a0_lo: bool = false,
1004 a0_hi: bool = false,
1005 a1_lo: bool = false,
1006 a1_hi: bool = false,
1007 a2_lo: bool = false,
1008 a2_hi: bool = false,
1009 a3_lo: bool = false,
1010 a3_hi: bool = false,
1011 a4_lo: bool = false,
1012 a4_hi: bool = false,
1013 a5_lo: bool = false,
1014 a5_hi: bool = false,
1015 a6_lo: bool = false,
1016 a6_hi: bool = false,
1017 a7_lo: bool = false,
1018 a7_hi: bool = false,
1019 a8_lo: bool = false,
1020 a8_hi: bool = false,
1021 a9_lo: bool = false,
1022 a9_hi: bool = false,
1023 a10_lo: bool = false,
1024 a10_hi: bool = false,
1025 a11_lo: bool = false,
1026 a11_hi: bool = false,
1027 a12_lo: bool = false,
1028 a12_hi: bool = false,
1029 a13_lo: bool = false,
1030 a13_hi: bool = false,
1031 a14_lo: bool = false,
1032 a14_hi: bool = false,
1033 a15_lo: bool = false,
1034 a15_hi: bool = false,
1035 a16_lo: bool = false,
1036 a16_hi: bool = false,
1037 a17_lo: bool = false,
1038 a17_hi: bool = false,
1039 a18_lo: bool = false,
1040 a18_hi: bool = false,
1041 a19_lo: bool = false,
1042 a19_hi: bool = false,
1043 a20_lo: bool = false,
1044 a20_hi: bool = false,
1045 a21_lo: bool = false,
1046 a21_hi: bool = false,
1047 a22_lo: bool = false,
1048 a22_hi: bool = false,
1049 a23_lo: bool = false,
1050 a23_hi: bool = false,
1051 a24_lo: bool = false,
1052 a24_hi: bool = false,
1053 a25_lo: bool = false,
1054 a25_hi: bool = false,
1055 a26_lo: bool = false,
1056 a26_hi: bool = false,
1057 a27_lo: bool = false,
1058 a27_hi: bool = false,
1059 a28_lo: bool = false,
1060 a28_hi: bool = false,
1061 a29_lo: bool = false,
1062 a29_hi: bool = false,
1063 a30_lo: bool = false,
1064 a30_hi: bool = false,
1065 a31_lo: bool = false,
1066 a31_hi: bool = false,
1067 a32_lo: bool = false,
1068 a32_hi: bool = false,
1069 a33_lo: bool = false,
1070 a33_hi: bool = false,
1071 a34_lo: bool = false,
1072 a34_hi: bool = false,
1073 a35_lo: bool = false,
1074 a35_hi: bool = false,
1075 a36_lo: bool = false,
1076 a36_hi: bool = false,
1077 a37_lo: bool = false,
1078 a37_hi: bool = false,
1079 a38_lo: bool = false,
1080 a38_hi: bool = false,
1081 a39_lo: bool = false,
1082 a39_hi: bool = false,
1083 a40_lo: bool = false,
1084 a40_hi: bool = false,
1085 a41_lo: bool = false,
1086 a41_hi: bool = false,
1087 a42_lo: bool = false,
1088 a42_hi: bool = false,
1089 a43_lo: bool = false,
1090 a43_hi: bool = false,
1091 a44_lo: bool = false,
1092 a44_hi: bool = false,
1093 a45_lo: bool = false,
1094 a45_hi: bool = false,
1095 a46_lo: bool = false,
1096 a46_hi: bool = false,
1097 a47_lo: bool = false,
1098 a47_hi: bool = false,
1099 a48_lo: bool = false,
1100 a48_hi: bool = false,
1101 a49_lo: bool = false,
1102 a49_hi: bool = false,
1103 a50_lo: bool = false,
1104 a50_hi: bool = false,
1105 a51_lo: bool = false,
1106 a51_hi: bool = false,
1107 a52_lo: bool = false,
1108 a52_hi: bool = false,
1109 a53_lo: bool = false,
1110 a53_hi: bool = false,
1111 a54_lo: bool = false,
1112 a54_hi: bool = false,
1113 a55_lo: bool = false,
1114 a55_hi: bool = false,
1115 a56_lo: bool = false,
1116 a56_hi: bool = false,
1117 a57_lo: bool = false,
1118 a57_hi: bool = false,
1119 a58_lo: bool = false,
1120 a58_hi: bool = false,
1121 a59_lo: bool = false,
1122 a59_hi: bool = false,
1123 a60_lo: bool = false,
1124 a60_hi: bool = false,
1125 a61_lo: bool = false,
1126 a61_hi: bool = false,
1127 a62_lo: bool = false,
1128 a62_hi: bool = false,
1129 a63_lo: bool = false,
1130 a63_hi: bool = false,
1131
1132 a0_x: bool = false,
1133 a0_y: bool = false,
1134 a0_z: bool = false,
1135 a0_t: bool = false,
1136 a1_x: bool = false,
1137 a1_y: bool = false,
1138 a1_z: bool = false,
1139 a1_t: bool = false,
1140 a2_x: bool = false,
1141 a2_y: bool = false,
1142 a2_z: bool = false,
1143 a2_t: bool = false,
1144 a3_x: bool = false,
1145 a3_y: bool = false,
1146 a3_z: bool = false,
1147 a3_t: bool = false,
1148 a4_x: bool = false,
1149 a4_y: bool = false,
1150 a4_z: bool = false,
1151 a4_t: bool = false,
1152 a5_x: bool = false,
1153 a5_y: bool = false,
1154 a5_z: bool = false,
1155 a5_t: bool = false,
1156 a6_x: bool = false,
1157 a6_y: bool = false,
1158 a6_z: bool = false,
1159 a6_t: bool = false,
1160 a7_x: bool = false,
1161 a7_y: bool = false,
1162 a7_z: bool = false,
1163 a7_t: bool = false,
1164 a8_x: bool = false,
1165 a8_y: bool = false,
1166 a8_z: bool = false,
1167 a8_t: bool = false,
1168 a9_x: bool = false,
1169 a9_y: bool = false,
1170 a9_z: bool = false,
1171 a9_t: bool = false,
1172 a10_x: bool = false,
1173 a10_y: bool = false,
1174 a10_z: bool = false,
1175 a10_t: bool = false,
1176 a11_x: bool = false,
1177 a11_y: bool = false,
1178 a11_z: bool = false,
1179 a11_t: bool = false,
1180 a12_x: bool = false,
1181 a12_y: bool = false,
1182 a12_z: bool = false,
1183 a12_t: bool = false,
1184 a13_x: bool = false,
1185 a13_y: bool = false,
1186 a13_z: bool = false,
1187 a13_t: bool = false,
1188 a14_x: bool = false,
1189 a14_y: bool = false,
1190 a14_z: bool = false,
1191 a14_t: bool = false,
1192 a15_x: bool = false,
1193 a15_y: bool = false,
1194 a15_z: bool = false,
1195 a15_t: bool = false,
1196 a16_x: bool = false,
1197 a16_y: bool = false,
1198 a16_z: bool = false,
1199 a16_t: bool = false,
1200 a17_x: bool = false,
1201 a17_y: bool = false,
1202 a17_z: bool = false,
1203 a17_t: bool = false,
1204 a18_x: bool = false,
1205 a18_y: bool = false,
1206 a18_z: bool = false,
1207 a18_t: bool = false,
1208 a19_x: bool = false,
1209 a19_y: bool = false,
1210 a19_z: bool = false,
1211 a19_t: bool = false,
1212 a20_x: bool = false,
1213 a20_y: bool = false,
1214 a20_z: bool = false,
1215 a20_t: bool = false,
1216 a21_x: bool = false,
1217 a21_y: bool = false,
1218 a21_z: bool = false,
1219 a21_t: bool = false,
1220 a22_x: bool = false,
1221 a22_y: bool = false,
1222 a22_z: bool = false,
1223 a22_t: bool = false,
1224 a23_x: bool = false,
1225 a23_y: bool = false,
1226 a23_z: bool = false,
1227 a23_t: bool = false,
1228 a24_x: bool = false,
1229 a24_y: bool = false,
1230 a24_z: bool = false,
1231 a24_t: bool = false,
1232 a25_x: bool = false,
1233 a25_y: bool = false,
1234 a25_z: bool = false,
1235 a25_t: bool = false,
1236 a26_x: bool = false,
1237 a26_y: bool = false,
1238 a26_z: bool = false,
1239 a26_t: bool = false,
1240 a27_x: bool = false,
1241 a27_y: bool = false,
1242 a27_z: bool = false,
1243 a27_t: bool = false,
1244 a28_x: bool = false,
1245 a28_y: bool = false,
1246 a28_z: bool = false,
1247 a28_t: bool = false,
1248 a29_x: bool = false,
1249 a29_y: bool = false,
1250 a29_z: bool = false,
1251 a29_t: bool = false,
1252 a30_x: bool = false,
1253 a30_y: bool = false,
1254 a30_z: bool = false,
1255 a30_t: bool = false,
1256 a31_x: bool = false,
1257 a31_y: bool = false,
1258 a31_z: bool = false,
1259 a31_t: bool = false,
1260 a32_x: bool = false,
1261 a32_y: bool = false,
1262 a32_z: bool = false,
1263 a32_t: bool = false,
1264 a33_x: bool = false,
1265 a33_y: bool = false,
1266 a33_z: bool = false,
1267 a33_t: bool = false,
1268 a34_x: bool = false,
1269 a34_y: bool = false,
1270 a34_z: bool = false,
1271 a34_t: bool = false,
1272 a35_x: bool = false,
1273 a35_y: bool = false,
1274 a35_z: bool = false,
1275 a35_t: bool = false,
1276 a36_x: bool = false,
1277 a36_y: bool = false,
1278 a36_z: bool = false,
1279 a36_t: bool = false,
1280 a37_x: bool = false,
1281 a37_y: bool = false,
1282 a37_z: bool = false,
1283 a37_t: bool = false,
1284 a38_x: bool = false,
1285 a38_y: bool = false,
1286 a38_z: bool = false,
1287 a38_t: bool = false,
1288 a39_x: bool = false,
1289 a39_y: bool = false,
1290 a39_z: bool = false,
1291 a39_t: bool = false,
1292 a40_x: bool = false,
1293 a40_y: bool = false,
1294 a40_z: bool = false,
1295 a40_t: bool = false,
1296 a41_x: bool = false,
1297 a41_y: bool = false,
1298 a41_z: bool = false,
1299 a41_t: bool = false,
1300 a42_x: bool = false,
1301 a42_y: bool = false,
1302 a42_z: bool = false,
1303 a42_t: bool = false,
1304 a43_x: bool = false,
1305 a43_y: bool = false,
1306 a43_z: bool = false,
1307 a43_t: bool = false,
1308 a44_x: bool = false,
1309 a44_y: bool = false,
1310 a44_z: bool = false,
1311 a44_t: bool = false,
1312 a45_x: bool = false,
1313 a45_y: bool = false,
1314 a45_z: bool = false,
1315 a45_t: bool = false,
1316 a46_x: bool = false,
1317 a46_y: bool = false,
1318 a46_z: bool = false,
1319 a46_t: bool = false,
1320 a47_x: bool = false,
1321 a47_y: bool = false,
1322 a47_z: bool = false,
1323 a47_t: bool = false,
1324 a48_x: bool = false,
1325 a48_y: bool = false,
1326 a48_z: bool = false,
1327 a48_t: bool = false,
1328 a49_x: bool = false,
1329 a49_y: bool = false,
1330 a49_z: bool = false,
1331 a49_t: bool = false,
1332 a50_x: bool = false,
1333 a50_y: bool = false,
1334 a50_z: bool = false,
1335 a50_t: bool = false,
1336 a51_x: bool = false,
1337 a51_y: bool = false,
1338 a51_z: bool = false,
1339 a51_t: bool = false,
1340 a52_x: bool = false,
1341 a52_y: bool = false,
1342 a52_z: bool = false,
1343 a52_t: bool = false,
1344 a53_x: bool = false,
1345 a53_y: bool = false,
1346 a53_z: bool = false,
1347 a53_t: bool = false,
1348 a54_x: bool = false,
1349 a54_y: bool = false,
1350 a54_z: bool = false,
1351 a54_t: bool = false,
1352 a55_x: bool = false,
1353 a55_y: bool = false,
1354 a55_z: bool = false,
1355 a55_t: bool = false,
1356 a56_x: bool = false,
1357 a56_y: bool = false,
1358 a56_z: bool = false,
1359 a56_t: bool = false,
1360 a57_x: bool = false,
1361 a57_y: bool = false,
1362 a57_z: bool = false,
1363 a57_t: bool = false,
1364 a58_x: bool = false,
1365 a58_y: bool = false,
1366 a58_z: bool = false,
1367 a58_t: bool = false,
1368 a59_x: bool = false,
1369 a59_y: bool = false,
1370 a59_z: bool = false,
1371 a59_t: bool = false,
1372 a60_x: bool = false,
1373 a60_y: bool = false,
1374 a60_z: bool = false,
1375 a60_t: bool = false,
1376 a61_x: bool = false,
1377 a61_y: bool = false,
1378 a61_z: bool = false,
1379 a61_t: bool = false,
1380 a62_x: bool = false,
1381 a62_y: bool = false,
1382 a62_z: bool = false,
1383 a62_t: bool = false,
1384 a63_x: bool = false,
1385 a63_y: bool = false,
1386 a63_z: bool = false,
1387 a63_t: bool = false,
1388 },
8601389 .lanai => packed struct {
8611390 /// Whether the inline assembly code may perform stores to memory
8621391 /// addresses other than those derived from input pointer provenance.
lib/std/debug/Dwarf.zig+3
......@@ -1434,6 +1434,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
14341434 .arm, .armeb, .thumb, .thumbeb => 15,
14351435 .csky => 64,
14361436 .hexagon => 76,
1437 .kvx => 64,
14371438 .lanai => 2,
14381439 .loongarch32, .loongarch64 => 64,
14391440 .m68k => 26,
......@@ -1457,6 +1458,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
14571458 .arm, .armeb, .thumb, .thumbeb => 11,
14581459 .csky => 14,
14591460 .hexagon => 30,
1461 .kvx => 14,
14601462 .lanai => 5,
14611463 .loongarch32, .loongarch64 => 22,
14621464 .m68k => 14,
......@@ -1480,6 +1482,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
14801482 .arm, .armeb, .thumb, .thumbeb => 13,
14811483 .csky => 14,
14821484 .hexagon => 29,
1485 .kvx => 12,
14831486 .lanai => 4,
14841487 .loongarch32, .loongarch64 => 3,
14851488 .m68k => 15,
lib/std/debug/cpu_context.zig+66
......@@ -9,6 +9,7 @@ else switch (native_arch) {
99 .arm, .armeb, .thumb, .thumbeb => Arm,
1010 .csky => Csky,
1111 .hexagon => Hexagon,
12 .kvx => Kvx,
1213 .lanai => Lanai,
1314 .loongarch32, .loongarch64 => LoongArch,
1415 .m68k => M68k,
......@@ -493,6 +494,71 @@ const Hexagon = extern struct {
493494 }
494495};
495496
497/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
498const Kvx = extern struct {
499 r: [64]u64,
500 ra: u64,
501 pc: u64,
502
503 pub inline fn current() Kvx {
504 var ctx: Kvx = undefined;
505 asm volatile (
506 \\ so (0)[$r32] = $r0r1r2r3
507 \\ ;;
508 \\ so (32)[$r32] = $r4r5r6r7
509 \\ ;;
510 \\ so (64)[$r32] = $r8r9r10r11
511 \\ ;;
512 \\ so (96)[$r32] = $r12r13r14r15
513 \\ ;;
514 \\ so (128)[$r32] = $r16r17r18r19
515 \\ ;;
516 \\ so (160)[$r32] = $r20r21r22r23
517 \\ ;;
518 \\ so (192)[$r32] = $r24r25r26r27
519 \\ ;;
520 \\ so (224)[$r32] = $r28r29r30r31
521 \\ ;;
522 \\ so (256)[$r32] = $r32r33r34r35
523 \\ ;;
524 \\ so (288)[$r32] = $r36r37r38r39
525 \\ ;;
526 \\ so (320)[$r32] = $r40r41r42r43
527 \\ ;;
528 \\ so (352)[$r32] = $r44r45r46r47
529 \\ ;;
530 \\ so (384)[$r32] = $r48r49r50r51
531 \\ ;;
532 \\ so (416)[$r32] = $r52r53r54r55
533 \\ ;;
534 \\ so (448)[$r32] = $r56r57r58r59
535 \\ get $r34 = $pc
536 \\ ;;
537 \\ so (480)[$r32] = $r60r61r62r63
538 \\ get $r35 = $ra
539 \\ ;;
540 \\ sq (512)[$r32] = $r34r35
541 :
542 : [ctx] "{r32}" (&ctx),
543 : .{ .r34 = true, .r35 = true, .memory = true });
544 return ctx;
545 }
546
547 pub fn dwarfRegisterBytes(ctx: *Kvx, register_num: u16) DwarfRegisterError![]u8 {
548 switch (register_num) {
549 0...63 => return @ptrCast(&ctx.r[register_num]),
550 64 => return @ptrCast(&ctx.pc),
551 67 => return @ptrCast(&ctx.ra),
552
553 65...66 => return error.UnsupportedRegister, // SFRs
554 68...255 => return error.UnsupportedRegister, // SFRs
555 256...767 => return error.UnsupportedRegister, // XCRs
556
557 else => return error.InvalidRegister,
558 }
559 }
560};
561
496562/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
497563const Lanai = extern struct {
498564 r: [32]u32,
lib/std/pie.zig+8
......@@ -11,6 +11,7 @@ const R_ARM_RELATIVE = 23;
1111const R_AARCH64_RELATIVE = 1027;
1212const R_CSKY_RELATIVE = 9;
1313const R_HEXAGON_RELATIVE = 35;
14const R_KVX_RELATIVE = 39;
1415const R_LARCH_RELATIVE = 3;
1516const R_68K_RELATIVE = 22;
1617const R_MICROBLAZE_REL = 16;
......@@ -31,6 +32,7 @@ const R_RELATIVE = switch (builtin.cpu.arch) {
3132 .alpha => R_ALPHA_RELATIVE,
3233 .csky => R_CSKY_RELATIVE,
3334 .hexagon => R_HEXAGON_RELATIVE,
35 .kvx => R_KVX_RELATIVE,
3436 .loongarch32, .loongarch64 => R_LARCH_RELATIVE,
3537 .m68k => R_68K_RELATIVE,
3638 .microblaze, .microblazeel => R_MICROBLAZE_REL,
......@@ -118,6 +120,12 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
118120 : [ret] "=r" (-> [*]const elf.Dyn),
119121 :
120122 : .{ .r1 = true }),
123 .kvx => asm volatile (
124 \\ .weak _DYNAMIC
125 \\ .hidden _DYNAMIC
126 \\ pcrel %[ret] = @pcrel(_DYNAMIC)
127 : [ret] "=r" (-> [*]const elf.Dyn),
128 ),
121129 .loongarch32, .loongarch64 => asm volatile (
122130 \\ .weak _DYNAMIC
123131 \\ .hidden _DYNAMIC
lib/std/simd.zig+2
......@@ -68,6 +68,8 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
6868 if (cpu.has(.s390x, .vector)) break :blk 128;
6969 } else if (cpu.arch.isSPARC()) {
7070 if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64;
71 } else if (cpu.arch == .kvx) {
72 break :blk 1024;
7173 } else if (cpu.arch == .ve) {
7274 if (cpu.has(.ve, .vpu)) break :blk 2048;
7375 } else if (cpu.arch.isWasm()) {
lib/std/start.zig+10
......@@ -205,6 +205,7 @@ fn _start() callconv(.naked) noreturn {
205205 .arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891
206206 .csky => ".cfi_undefined lr",
207207 .hexagon => ".cfi_undefined r31",
208 .kvx => ".cfi_undefined r14",
208209 .loongarch32, .loongarch64 => ".cfi_undefined 1",
209210 .m68k => ".cfi_undefined %%pc",
210211 .microblaze, .microblazeel => ".cfi_undefined r15",
......@@ -318,6 +319,15 @@ fn _start() callconv(.naked) noreturn {
318319 \\ r29 = add(r29, #-8)
319320 \\ call %[posixCallMainAndExit]
320321 ,
322 .kvx =>
323 \\ make $fp = 0
324 \\ ;;
325 \\ set $ra = $fp
326 \\ copyd $r0 = $sp
327 \\ andd $sp = $sp, -32
328 \\ ;;
329 \\ goto %[posixCallMainAndExit]
330 ,
321331 .loongarch32, .loongarch64 =>
322332 \\ move $fp, $zero
323333 \\ move $ra, $zero
lib/zig.h+4-2
......@@ -28,6 +28,8 @@
2828#define zig_arm
2929#elif defined(__hexagon__)
3030#define zig_hexagon
31#elif defined(__kvx__)
32#define zig_kvx
3133#elif defined(__loongarch32)
3234#define zig_loongarch32
3335#define zig_loongarch
......@@ -383,7 +385,7 @@
383385#define zig_trap() __asm__ volatile("udf #0xfdee")
384386#elif defined(zig_hexagon)
385387#define zig_trap() __asm__ volatile("r27:26 = memd(#0xbadc0fee)")
386#elif defined(zig_loongarch) || defined(zig_powerpc)
388#elif defined(zig_kvx) || defined(zig_loongarch) || defined(zig_powerpc)
387389#define zig_trap() __asm__ volatile(".word 0x0")
388390#elif defined(zig_mips)
389391#define zig_trap() __asm__ volatile(".word 0x3d")
......@@ -419,7 +421,7 @@
419421#define zig_breakpoint() __asm__ volatile("brk #0xf000")
420422#elif defined(zig_hexagon)
421423#define zig_breakpoint() __asm__ volatile("brkpt")
422#elif defined(zig_loongarch)
424#elif defined(zig_kvx) || defined(zig_loongarch)
423425#define zig_breakpoint() __asm__ volatile("break 0x0")
424426#elif defined(zig_mips)
425427#define zig_breakpoint() __asm__ volatile("break")
src/Sema.zig+2
......@@ -9091,6 +9091,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
90919091 .hexagon_sysv_hvx,
90929092 .hppa_elf,
90939093 .hppa64_elf,
9094 .kvx_lp64,
9095 .kvx_ilp32,
90949096 .lanai_sysv,
90959097 .loongarch64_lp64,
90969098 .loongarch32_ilp32,
src/codegen/c.zig+3-2
......@@ -5781,8 +5781,9 @@ fn airAsm(f: *Function, inst: Air.Inst.Index) !CValue {
57815781 c_name_buf[0] = '$';
57825782 break :name c_name;
57835783 } else if ((target.cpu.arch.isMIPS() and (mem.startsWith(u8, field_name, "fcc") or field_name[0] == 'w')) or
5784 ((target.cpu.arch.isMIPS() or target.cpu.arch == .alpha) and field_name[0] == 'f')) name: {
5785 // "$" prefix for FCC, W and F registers
5784 ((target.cpu.arch.isMIPS() or target.cpu.arch == .alpha) and field_name[0] == 'f') or
5785 (target.cpu.arch == .kvx and !mem.eql(u8, field_name, "memory"))) name: {
5786 // "$" prefix for these registers
57865787 c_name_buf[0] = '$';
57875788 @memcpy((&c_name_buf)[1..][0..field_name.len], field_name);
57885789 break :name (&c_name_buf)[0 .. 1 + field_name.len];
src/codegen/llvm.zig+5
......@@ -111,6 +111,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
111111 .hppa,
112112 .hppa64,
113113 .kalimba,
114 .kvx,
114115 .microblaze,
115116 .microblazeel,
116117 .or1k,
......@@ -477,6 +478,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
477478 .hppa,
478479 .hppa64,
479480 .kalimba,
481 .kvx,
480482 .microblaze,
481483 .microblazeel,
482484 .or1k,
......@@ -11931,6 +11933,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
1193111933 .hexagon_sysv_hvx,
1193211934 .hppa_elf,
1193311935 .hppa64_elf,
11936 .kvx_lp64,
11937 .kvx_ilp32,
1193411938 .lanai_sysv,
1193511939 .loongarch64_lp64,
1193611940 .loongarch32_ilp32,
......@@ -13114,6 +13118,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1311413118 .hppa,
1311513119 .hppa64,
1311613120 .kalimba,
13121 .kvx,
1311713122 .microblaze,
1311813123 .microblazeel,
1311913124 .or1k,
src/target.zig+2
......@@ -219,6 +219,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
219219 .hppa,
220220 .hppa64,
221221 .kalimba,
222 .kvx,
222223 .microblaze,
223224 .microblazeel,
224225 .or1k,
......@@ -755,6 +756,7 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
755756 => .@"4",
756757 .bpfeb,
757758 .bpfel,
759 .kvx,
758760 .mips64,
759761 .mips64el,
760762 => .@"8",
tools/update_cpu_features.zig+37
......@@ -973,6 +973,43 @@ const targets = [_]ArchTarget{
973973 .td_name = "Hexagon",
974974 },
975975 },
976 .{
977 .zig_name = "kvx",
978 .llvm = null,
979 .extra_features = &.{
980 .{
981 .zig_name = "v3_1",
982 .desc = "Enable ISA v3.1",
983 .deps = &.{},
984 },
985 .{
986 .zig_name = "v3_2",
987 .desc = "Enable ISA v3.2",
988 .deps = &.{"v3_1"},
989 },
990 .{
991 .zig_name = "v4_1",
992 .desc = "Enable ISA v4.1",
993 .deps = &.{"v3_2"},
994 },
995 },
996 .extra_cpus = &.{
997 .{
998 .llvm_name = null,
999 .zig_name = "coolidge_v1",
1000 .features = &.{
1001 "v3_1",
1002 },
1003 },
1004 .{
1005 .llvm_name = null,
1006 .zig_name = "coolidge_v2",
1007 .features = &.{
1008 "v3_2",
1009 },
1010 },
1011 },
1012 },
9761013 .{
9771014 .zig_name = "lanai",
9781015 .llvm = .{