authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-06 09:09:09+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-06 10:31:01+02:00
logd30609829eb744b28a26a5161c2788dfdef3618d
tree2a2914deef232732ce5cf63abefc19ba82632d61
parent3cf655356c388ce00a4b6fbf9fbb411f1481250e
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.openbsd: bail aarch64 detection if we don't get all registers

1 files changed, 22 insertions(+), 20 deletions(-)

lib/std/zig/system/openbsd.zig+22-20
......@@ -4,7 +4,7 @@ const std = @import("std");
44const native_arch = builtin.target.cpu.arch;
55
66const aarch64 = struct {
7 fn sysctlReg(key: c_int) u64 {
7 fn sysctlReg(key: c_int) ?u64 {
88 const mib: [2]c_int = [_]c_int{
99 std.c.CTL.MACHDEP,
1010 key,
......@@ -17,33 +17,35 @@ const aarch64 = struct {
1717 error.PermissionDenied => unreachable,
1818 error.SystemResources => unreachable,
1919 error.UnknownName => unreachable,
20 error.Unexpected => return 0,
20 error.Unexpected => return null,
2121 };
2222
2323 return value;
2424 }
25
26 fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
27 const registers = [12]u64{
28 0, // MIDR_EL1
29 sysctlReg(std.c.CPU.AA64PFR0) orelse return null,
30 sysctlReg(std.c.CPU.AA64PFR1) orelse return null,
31 0, // ID_AA64DFR0_EL1
32 0, // ID_AA64DFR1_EL1
33 0, // ID_AA64AFR0_EL1
34 0, // ID_AA64AFR1_EL1
35 sysctlReg(std.c.CPU.ID_AA64ISAR0) orelse return null,
36 sysctlReg(std.c.CPU.ID_AA64ISAR1) orelse return null,
37 sysctlReg(std.c.CPU.ID_AA64MMFR0) orelse return null,
38 sysctlReg(std.c.CPU.ID_AA64MMFR1) orelse return null,
39 sysctlReg(std.c.CPU.ID_AA64MMFR2) orelse return null,
40 };
41
42 return @import("arm.zig").aarch64.detectNativeCpuAndFeatures(arch, registers);
43 }
2544};
2645
2746pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
2847 return switch (native_arch) {
29 .aarch64, .aarch64_be => b: {
30 const registers = [12]u64{
31 0, // MIDR_EL1
32 aarch64.sysctlReg(std.c.CPU.AA64PFR0),
33 aarch64.sysctlReg(std.c.CPU.AA64PFR1),
34 0, // ID_AA64DFR0_EL1
35 0, // ID_AA64DFR1_EL1
36 0, // ID_AA64AFR0_EL1
37 0, // ID_AA64AFR1_EL1
38 aarch64.sysctlReg(std.c.CPU.ID_AA64ISAR0),
39 aarch64.sysctlReg(std.c.CPU.ID_AA64ISAR1),
40 aarch64.sysctlReg(std.c.CPU.ID_AA64MMFR0),
41 aarch64.sysctlReg(std.c.CPU.ID_AA64MMFR1),
42 aarch64.sysctlReg(std.c.CPU.ID_AA64MMFR2),
43 };
44
45 break :b @import("arm.zig").aarch64.detectNativeCpuAndFeatures(native_arch, registers);
46 },
48 .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch),
4749 else => null,
4850 };
4951}