authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-15 01:50:35-07:00
committergravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-07-26 04:05:40-07:00
logd3f75522d7e18188748558c2ae20928b83d173bf
treefc691c36c0adfbd14d426c53f9422c5a562542de
parentc78ebeb44ce078a165e3302b629432eeee6a656d
signaturelock-open Commit is signed but in an unrecognized format.

lower: fix logic bug in `cmp_gt`

1 files changed, 1 insertions(+), 3 deletions(-)

src/arch/riscv64/Lower.zig+1-3
......@@ -304,7 +304,6 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index, options: struct {
304304 };
305305
306306 const is_unsigned = ty.isUnsignedInt(pt.zcu);
307
308307 const less_than: Encoding.Mnemonic = if (is_unsigned) .sltu else .slt;
309308
310309 switch (class) {
......@@ -338,8 +337,8 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index, options: struct {
338337 .gt => {
339338 try lower.emit(less_than, &.{
340339 .{ .reg = rd },
341 .{ .reg = rs1 },
342340 .{ .reg = rs2 },
341 .{ .reg = rs1 },
343342 });
344343 },
345344 .gte => {
......@@ -348,7 +347,6 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index, options: struct {
348347 .{ .reg = rs1 },
349348 .{ .reg = rs2 },
350349 });
351
352350 try lower.emit(.xori, &.{
353351 .{ .reg = rd },
354352 .{ .reg = rd },