authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-02-05 12:44:32+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-02-05 15:58:46+01:00
logd4c3475f3dce8ecf81ba2baaf97b6d25426919ec
tree887b11ac9d5103e3e7bb8f0d85a21e561d61472f
parentf2a82bafae414e9b454b77f6d0bcf768cfa9089b

stage2 ARM: clarify usage of unfreezeRegs in airSliceElemVal

1 files changed, 5 insertions(+), 7 deletions(-)

src/arch/arm/CodeGen.zig+5-7
...@@ -1247,7 +1247,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1247,7 +1247,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
1247 else => return self.fail("TODO slice_elem_val when slice is {}", .{slice_mcv}),1247 else => return self.fail("TODO slice_elem_val when slice is {}", .{slice_mcv}),
1248 };1248 };
1249 self.register_manager.freezeRegs(&.{base_mcv.register});1249 self.register_manager.freezeRegs(&.{base_mcv.register});
1250 defer self.register_manager.unfreezeRegs(&.{base_mcv.register});
12511250
1252 switch (elem_size) {1251 switch (elem_size) {
1253 1, 4 => {1252 1, 4 => {
...@@ -1283,6 +1282,8 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1283,6 +1282,8 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
1283 } },1282 } },
1284 });1283 });
12851284
1285 self.register_manager.unfreezeRegs(&.{base_mcv.register});
1286
1286 break :result dst_mcv;1287 break :result dst_mcv;
1287 },1288 },
1288 else => {1289 else => {
...@@ -1291,7 +1292,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1291,7 +1292,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
1291 const offset_mcv = try self.genArmMulConstant(bin_op.rhs, @intCast(u32, elem_size));1292 const offset_mcv = try self.genArmMulConstant(bin_op.rhs, @intCast(u32, elem_size));
1292 assert(offset_mcv == .register); // result of multiplication should always be register1293 assert(offset_mcv == .register); // result of multiplication should always be register
1293 self.register_manager.freezeRegs(&.{offset_mcv.register});1294 self.register_manager.freezeRegs(&.{offset_mcv.register});
1294 defer self.register_manager.unfreezeRegs(&.{offset_mcv.register});
12951295
1296 const addr_reg = try self.register_manager.allocReg(null);1296 const addr_reg = try self.register_manager.allocReg(null);
1297 self.register_manager.freezeRegs(&.{addr_reg});1297 self.register_manager.freezeRegs(&.{addr_reg});
...@@ -1299,11 +1299,9 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1299,11 +1299,9 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12991299
1300 try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);1300 try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
13011301
1302 // I know we will unfreeze these registers at the end of1302 // At this point in time, neither the base register
1303 // the scope of :result. However, at this point in time,1303 // nor the offset register contains any valuable data
1304 // neither the base register nor the offset register1304 // anymore.
1305 // contains any valuable data anymore. In order to reduce
1306 // register pressure, unfreeze them prematurely
1307 self.register_manager.unfreezeRegs(&.{ base_mcv.register, offset_mcv.register });1305 self.register_manager.unfreezeRegs(&.{ base_mcv.register, offset_mcv.register });
13081306
1309 try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);1307 try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);