| ... | ... | @@ -2114,6 +2114,47 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 2114 | 2114 | return MCValue.none; |
| 2115 | 2115 | } |
| 2116 | 2116 | }, |
| 2117 | .aarch64 => { |
| 2118 | for (inst.inputs) |input, i| { |
| 2119 | if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') { |
| 2120 | return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input}); |
| 2121 | } |
| 2122 | const reg_name = input[1 .. input.len - 1]; |
| 2123 | const reg = parseRegName(reg_name) orelse |
| 2124 | return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name}); |
| 2125 | const arg = try self.resolveInst(inst.args[i]); |
| 2126 | try self.genSetReg(inst.base.src, reg, arg); |
| 2127 | } |
| 2128 | |
| 2129 | // TODO move this to lib/std/{elf, macho}.zig, etc. |
| 2130 | const is_syscall_inst = switch (self.bin_file.tag) { |
| 2131 | .macho => mem.eql(u8, inst.asm_source, "svc #0x80"), |
| 2132 | .elf => mem.eql(u8, inst.asm_source, "svc #0"), |
| 2133 | else => |tag| return self.fail(inst.base.src, "TODO implement aarch64 support for other syscall instructions for file format: '{}'", .{tag}), |
| 2134 | }; |
| 2135 | if (is_syscall_inst) { |
| 2136 | const imm16: u16 = switch (self.bin_file.tag) { |
| 2137 | .macho => 0x80, |
| 2138 | .elf => 0, |
| 2139 | else => unreachable, |
| 2140 | }; |
| 2141 | mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.svc(imm16).toU32()); |
| 2142 | } else { |
| 2143 | return self.fail(inst.base.src, "TODO implement support for more aarch64 assembly instructions", .{}); |
| 2144 | } |
| 2145 | |
| 2146 | if (inst.output) |output| { |
| 2147 | if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') { |
| 2148 | return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output}); |
| 2149 | } |
| 2150 | const reg_name = output[2 .. output.len - 1]; |
| 2151 | const reg = parseRegName(reg_name) orelse |
| 2152 | return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name}); |
| 2153 | return MCValue{ .register = reg }; |
| 2154 | } else { |
| 2155 | return MCValue.none; |
| 2156 | } |
| 2157 | }, |
| 2117 | 2158 | .riscv64 => { |
| 2118 | 2159 | for (inst.inputs) |input, i| { |
| 2119 | 2160 | if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') { |
Jakub Konka <kubkon@jakubkonka.com> 2020-10-31 23:52:48+01:00
src