| ... | ... | @@ -6542,28 +6542,19 @@ fn airPrefetch(self: *FuncGen, inst: Air.Inst.Index) Allocator.Error!Builder.Val |
| 6542 | 6542 | comptime assert(@backingInt(std.lang.PrefetchOptions.Cache.instruction) == 0); |
| 6543 | 6543 | comptime assert(@backingInt(std.lang.PrefetchOptions.Cache.data) == 1); |
| 6544 | 6544 | |
| 6545 | | // LLVM fails during codegen of instruction cache prefetchs for these architectures. |
| 6546 | | // This is an LLVM bug as the prefetch intrinsic should be a noop if not supported |
| 6547 | | // by the target. |
| 6548 | | // To work around this, don't emit llvm.prefetch in this case. |
| 6549 | | // See https://bugs.llvm.org/show_bug.cgi?id=21037 |
| 6550 | 6545 | const zcu = self.object.zcu; |
| 6551 | 6546 | const target = zcu.getTarget(); |
| 6552 | 6547 | switch (prefetch.cache) { |
| 6553 | 6548 | .instruction => switch (target.cpu.arch) { |
| 6549 | // https://github.com/llvm/llvm-project/issues/218236 |
| 6554 | 6550 | .x86_64, |
| 6555 | 6551 | .x86, |
| 6552 | // https://github.com/llvm/llvm-project/issues/218239 |
| 6556 | 6553 | .powerpc, |
| 6557 | 6554 | .powerpcle, |
| 6558 | 6555 | .powerpc64, |
| 6559 | 6556 | .powerpc64le, |
| 6560 | 6557 | => return .none, |
| 6561 | | .arm, .armeb, .thumb, .thumbeb => { |
| 6562 | | switch (prefetch.rw) { |
| 6563 | | .write => return .none, |
| 6564 | | else => {}, |
| 6565 | | } |
| 6566 | | }, |
| 6567 | 6558 | else => {}, |
| 6568 | 6559 | }, |
| 6569 | 6560 | .data => {}, |