| ... | ... | @@ -36,6 +36,7 @@ const abi = @import("abi.zig"); |
| 36 | 36 | const bits = @import("bits.zig"); |
| 37 | 37 | const errUnionErrorOffset = codegen.errUnionErrorOffset; |
| 38 | 38 | const errUnionPayloadOffset = codegen.errUnionPayloadOffset; |
| 39 | const encoder = @import("encoder.zig"); |
| 39 | 40 | |
| 40 | 41 | const Condition = bits.Condition; |
| 41 | 42 | const Immediate = bits.Immediate; |
| ... | ... | @@ -1188,6 +1189,74 @@ fn formatWipMir( |
| 1188 | 1189 | try writer.print(" | {}", .{lowered_inst}); |
| 1189 | 1190 | first = false; |
| 1190 | 1191 | } |
| 1192 | if (first) { |
| 1193 | const ip = &data.self.pt.zcu.intern_pool; |
| 1194 | const mir_inst = lower.mir.instructions.get(data.inst); |
| 1195 | try writer.print(" | .{s}", .{@tagName(mir_inst.ops)}); |
| 1196 | switch (mir_inst.ops) { |
| 1197 | else => unreachable, |
| 1198 | .pseudo_dbg_prologue_end_none, |
| 1199 | .pseudo_dbg_line_line_column, |
| 1200 | .pseudo_dbg_epilogue_begin_none, |
| 1201 | .pseudo_dbg_enter_block_none, |
| 1202 | .pseudo_dbg_leave_block_none, |
| 1203 | .pseudo_dbg_var_args_none, |
| 1204 | .pseudo_dead_none, |
| 1205 | => {}, |
| 1206 | .pseudo_dbg_enter_inline_func, .pseudo_dbg_leave_inline_func => try writer.print(" {}", .{ |
| 1207 | ip.getNav(ip.indexToKey(mir_inst.data.func).func.owner_nav).name.fmt(ip), |
| 1208 | }), |
| 1209 | .pseudo_dbg_local_a => try writer.print(" {}", .{mir_inst.data.a.air_inst}), |
| 1210 | .pseudo_dbg_local_ai_s => try writer.print(" {}, {d}", .{ |
| 1211 | mir_inst.data.ai.air_inst, |
| 1212 | @as(i32, @bitCast(mir_inst.data.ai.i)), |
| 1213 | }), |
| 1214 | .pseudo_dbg_local_ai_u => try writer.print(" {}, {d}", .{ |
| 1215 | mir_inst.data.ai.air_inst, |
| 1216 | mir_inst.data.ai.i, |
| 1217 | }), |
| 1218 | .pseudo_dbg_local_ai_64 => try writer.print(" {}, {d}", .{ |
| 1219 | mir_inst.data.ai.air_inst, |
| 1220 | lower.mir.extraData(Mir.Imm64, mir_inst.data.ai.i).data.decode(), |
| 1221 | }), |
| 1222 | .pseudo_dbg_local_as => { |
| 1223 | const mem_op: Instruction.Operand = .{ .mem = .initSib(.qword, .{ |
| 1224 | .base = .{ .reloc = mir_inst.data.as.sym_index }, |
| 1225 | }) }; |
| 1226 | try writer.print(" {}, {}", .{ mir_inst.data.as.air_inst, mem_op.fmt(.m) }); |
| 1227 | }, |
| 1228 | .pseudo_dbg_local_aso => { |
| 1229 | const sym_off = lower.mir.extraData(bits.SymbolOffset, mir_inst.data.ax.payload).data; |
| 1230 | const mem_op: Instruction.Operand = .{ .mem = .initSib(.qword, .{ |
| 1231 | .base = .{ .reloc = sym_off.sym_index }, |
| 1232 | .disp = sym_off.off, |
| 1233 | }) }; |
| 1234 | try writer.print(" {}, {}", .{ mir_inst.data.ax.air_inst, mem_op.fmt(.m) }); |
| 1235 | }, |
| 1236 | .pseudo_dbg_local_aro => { |
| 1237 | const air_off = lower.mir.extraData(Mir.AirOffset, mir_inst.data.rx.payload).data; |
| 1238 | const mem_op: Instruction.Operand = .{ .mem = .initSib(.qword, .{ |
| 1239 | .base = .{ .reg = mir_inst.data.rx.r1 }, |
| 1240 | .disp = air_off.off, |
| 1241 | }) }; |
| 1242 | try writer.print(" {}, {}", .{ air_off.air_inst, mem_op.fmt(.m) }); |
| 1243 | }, |
| 1244 | .pseudo_dbg_local_af => { |
| 1245 | const frame_addr = lower.mir.extraData(bits.FrameAddr, mir_inst.data.ax.payload).data; |
| 1246 | const mem_op: Instruction.Operand = .{ .mem = .initSib(.qword, .{ |
| 1247 | .base = .{ .frame = frame_addr.index }, |
| 1248 | .disp = frame_addr.off, |
| 1249 | }) }; |
| 1250 | try writer.print(" {}, {d}", .{ mir_inst.data.ax.air_inst, mem_op.fmt(.m) }); |
| 1251 | }, |
| 1252 | .pseudo_dbg_local_am => { |
| 1253 | const mem_op: Instruction.Operand = .{ |
| 1254 | .mem = lower.mir.extraData(Mir.Memory, mir_inst.data.ax.payload).data.decode(), |
| 1255 | }; |
| 1256 | try writer.print(" {}, {}", .{ mir_inst.data.ax.air_inst, mem_op.fmt(.m) }); |
| 1257 | }, |
| 1258 | } |
| 1259 | } |
| 1191 | 1260 | } |
| 1192 | 1261 | fn fmtWipMir(self: *Self, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir) { |
| 1193 | 1262 | return .{ .data = .{ .self = self, .inst = inst } }; |
Jacob Young <jacobly@ziglang.org> 2024-09-15 20:36:11-04:00
src