authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2021-04-08 14:20:05+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-04-08 13:39:11-07:00
logd7a89f98765381b4be2ce7626addad07ecfa7208
tree2dd0f4f4b6e8b9452267ea3c55fdc9d5ffc4cb5d
parentab5a445d252ba090d25ae0c49a9b0820ffbb73d3

stage2 AArch64: Add conditional branch instructions

3 files changed, 179 insertions(+), 50 deletions(-)

src/codegen/aarch64.zig+171-42
......@@ -200,7 +200,7 @@ test "FloatingPointRegister.toX" {
200200
201201/// Represents an instruction in the AArch64 instruction set
202202pub const Instruction = union(enum) {
203 MoveWideImmediate: packed struct {
203 move_wide_immediate: packed struct {
204204 rd: u5,
205205 imm16: u16,
206206 hw: u2,
......@@ -208,14 +208,14 @@ pub const Instruction = union(enum) {
208208 opc: u2,
209209 sf: u1,
210210 },
211 PCRelativeAddress: packed struct {
211 pc_relative_address: packed struct {
212212 rd: u5,
213213 immhi: u19,
214214 fixed: u5 = 0b10000,
215215 immlo: u2,
216216 op: u1,
217217 },
218 LoadStoreRegister: packed struct {
218 load_store_register: packed struct {
219219 rt: u5,
220220 rn: u5,
221221 offset: u12,
......@@ -225,7 +225,7 @@ pub const Instruction = union(enum) {
225225 fixed: u3 = 0b111,
226226 size: u2,
227227 },
228 LoadStorePairOfRegisters: packed struct {
228 load_store_register_pair: packed struct {
229229 rt1: u5,
230230 rn: u5,
231231 rt2: u5,
......@@ -235,20 +235,20 @@ pub const Instruction = union(enum) {
235235 fixed: u5 = 0b101_0_0,
236236 opc: u2,
237237 },
238 LoadLiteral: packed struct {
238 load_literal: packed struct {
239239 rt: u5,
240240 imm19: u19,
241241 fixed: u6 = 0b011_0_00,
242242 opc: u2,
243243 },
244 ExceptionGeneration: packed struct {
244 exception_generation: packed struct {
245245 ll: u2,
246246 op2: u3,
247247 imm16: u16,
248248 opc: u3,
249249 fixed: u8 = 0b1101_0100,
250250 },
251 UnconditionalBranchRegister: packed struct {
251 unconditional_branch_register: packed struct {
252252 op4: u5,
253253 rn: u5,
254254 op3: u6,
......@@ -256,15 +256,15 @@ pub const Instruction = union(enum) {
256256 opc: u4,
257257 fixed: u7 = 0b1101_011,
258258 },
259 UnconditionalBranchImmediate: packed struct {
259 unconditional_branch_immediate: packed struct {
260260 imm26: u26,
261261 fixed: u5 = 0b00101,
262262 op: u1,
263263 },
264 NoOperation: packed struct {
264 no_operation: packed struct {
265265 fixed: u32 = 0b1101010100_0_00_011_0010_0000_000_11111,
266266 },
267 LogicalShiftedRegister: packed struct {
267 logical_shifted_register: packed struct {
268268 rd: u5,
269269 rn: u5,
270270 imm6: u6,
......@@ -275,7 +275,7 @@ pub const Instruction = union(enum) {
275275 opc: u2,
276276 sf: u1,
277277 },
278 AddSubtractImmediate: packed struct {
278 add_subtract_immediate: packed struct {
279279 rd: u5,
280280 rn: u5,
281281 imm12: u12,
......@@ -285,6 +285,20 @@ pub const Instruction = union(enum) {
285285 op: u1,
286286 sf: u1,
287287 },
288 conditional_branch: struct {
289 cond: u4,
290 o0: u1,
291 imm19: u19,
292 o1: u1,
293 fixed: u7 = 0b0101010,
294 },
295 compare_and_branch: struct {
296 rt: u5,
297 imm19: u19,
298 op: u1,
299 fixed: u6 = 0b011010,
300 sf: u1,
301 },
288302
289303 pub const Shift = struct {
290304 shift: Type = .lsl,
......@@ -303,19 +317,73 @@ pub const Instruction = union(enum) {
303317 };
304318 };
305319
320 pub const Condition = enum(u4) {
321 /// Integer: Equal
322 /// Floating point: Equal
323 eq,
324 /// Integer: Not equal
325 /// Floating point: Not equal or unordered
326 ne,
327 /// Integer: Carry set
328 /// Floating point: Greater than, equal, or unordered
329 cs,
330 /// Integer: Carry clear
331 /// Floating point: Less than
332 cc,
333 /// Integer: Minus, negative
334 /// Floating point: Less than
335 mi,
336 /// Integer: Plus, positive or zero
337 /// Floating point: Greater than, equal, or unordered
338 pl,
339 /// Integer: Overflow
340 /// Floating point: Unordered
341 vs,
342 /// Integer: No overflow
343 /// Floating point: Ordered
344 vc,
345 /// Integer: Unsigned higher
346 /// Floating point: Greater than, or unordered
347 hi,
348 /// Integer: Unsigned lower or same
349 /// Floating point: Less than or equal
350 ls,
351 /// Integer: Signed greater than or equal
352 /// Floating point: Greater than or equal
353 ge,
354 /// Integer: Signed less than
355 /// Floating point: Less than, or unordered
356 lt,
357 /// Integer: Signed greater than
358 /// Floating point: Greater than
359 gt,
360 /// Integer: Signed less than or equal
361 /// Floating point: Less than, equal, or unordered
362 le,
363 /// Integer: Always
364 /// Floating point: Always
365 al,
366 /// Integer: Always
367 /// Floating point: Always
368 nv,
369 };
370
306371 pub fn toU32(self: Instruction) u32 {
307372 return switch (self) {
308 .MoveWideImmediate => |v| @bitCast(u32, v),
309 .PCRelativeAddress => |v| @bitCast(u32, v),
310 .LoadStoreRegister => |v| @bitCast(u32, v),
311 .LoadStorePairOfRegisters => |v| @bitCast(u32, v),
312 .LoadLiteral => |v| @bitCast(u32, v),
313 .ExceptionGeneration => |v| @bitCast(u32, v),
314 .UnconditionalBranchRegister => |v| @bitCast(u32, v),
315 .UnconditionalBranchImmediate => |v| @bitCast(u32, v),
316 .NoOperation => |v| @bitCast(u32, v),
317 .LogicalShiftedRegister => |v| @bitCast(u32, v),
318 .AddSubtractImmediate => |v| @bitCast(u32, v),
373 .move_wide_immediate => |v| @bitCast(u32, v),
374 .pc_relative_address => |v| @bitCast(u32, v),
375 .load_store_register => |v| @bitCast(u32, v),
376 .load_store_register_pair => |v| @bitCast(u32, v),
377 .load_literal => |v| @bitCast(u32, v),
378 .exception_generation => |v| @bitCast(u32, v),
379 .unconditional_branch_register => |v| @bitCast(u32, v),
380 .unconditional_branch_immediate => |v| @bitCast(u32, v),
381 .no_operation => |v| @bitCast(u32, v),
382 .logical_shifted_register => |v| @bitCast(u32, v),
383 .add_subtract_immediate => |v| @bitCast(u32, v),
384 // TODO once packed structs work, this can be refactored
385 .conditional_branch => |v| @as(u32, v.cond) | (@as(u32, v.o0) << 4) | (@as(u32, v.imm19) << 5) | (@as(u32, v.o1) << 24) | (@as(u32, v.fixed) << 25),
386 .compare_and_branch => |v| @as(u32, v.rt) | (@as(u32, v.imm19) << 5) | (@as(u32, v.op) << 24) | (@as(u32, v.fixed) << 25) | (@as(u32, v.sf) << 31),
319387 };
320388 }
321389
......@@ -329,7 +397,7 @@ pub const Instruction = union(enum) {
329397 32 => {
330398 assert(shift % 16 == 0 and shift <= 16);
331399 return Instruction{
332 .MoveWideImmediate = .{
400 .move_wide_immediate = .{
333401 .rd = rd.id(),
334402 .imm16 = imm16,
335403 .hw = @intCast(u2, shift / 16),
......@@ -341,7 +409,7 @@ pub const Instruction = union(enum) {
341409 64 => {
342410 assert(shift % 16 == 0 and shift <= 48);
343411 return Instruction{
344 .MoveWideImmediate = .{
412 .move_wide_immediate = .{
345413 .rd = rd.id(),
346414 .imm16 = imm16,
347415 .hw = @intCast(u2, shift / 16),
......@@ -358,7 +426,7 @@ pub const Instruction = union(enum) {
358426 assert(rd.size() == 64);
359427 const imm21_u = @bitCast(u21, imm21);
360428 return Instruction{
361 .PCRelativeAddress = .{
429 .pc_relative_address = .{
362430 .rd = rd.id(),
363431 .immlo = @truncate(u2, imm21_u),
364432 .immhi = @truncate(u19, imm21_u >> 2),
......@@ -522,7 +590,7 @@ pub const Instruction = union(enum) {
522590 .str, .strh, .strb => 0b00,
523591 };
524592 return Instruction{
525 .LoadStoreRegister = .{
593 .load_store_register = .{
526594 .rt = rt.id(),
527595 .rn = rn.id(),
528596 .offset = off,
......@@ -544,7 +612,7 @@ pub const Instruction = union(enum) {
544612 };
545613 }
546614
547 fn loadStorePairOfRegisters(
615 fn loadStoreRegisterPair(
548616 rt1: Register,
549617 rt2: Register,
550618 rn: Register,
......@@ -557,7 +625,7 @@ pub const Instruction = union(enum) {
557625 assert(-256 <= offset and offset <= 252);
558626 const imm7 = @truncate(u7, @bitCast(u9, offset >> 2));
559627 return Instruction{
560 .LoadStorePairOfRegisters = .{
628 .load_store_register_pair = .{
561629 .rt1 = rt1.id(),
562630 .rn = rn.id(),
563631 .rt2 = rt2.id(),
......@@ -572,7 +640,7 @@ pub const Instruction = union(enum) {
572640 assert(-512 <= offset and offset <= 504);
573641 const imm7 = @truncate(u7, @bitCast(u9, offset >> 3));
574642 return Instruction{
575 .LoadStorePairOfRegisters = .{
643 .load_store_register_pair = .{
576644 .rt1 = rt1.id(),
577645 .rn = rn.id(),
578646 .rt2 = rt2.id(),
......@@ -591,7 +659,7 @@ pub const Instruction = union(enum) {
591659 switch (rt.size()) {
592660 32 => {
593661 return Instruction{
594 .LoadLiteral = .{
662 .load_literal = .{
595663 .rt = rt.id(),
596664 .imm19 = imm19,
597665 .opc = 0b00,
......@@ -600,7 +668,7 @@ pub const Instruction = union(enum) {
600668 },
601669 64 => {
602670 return Instruction{
603 .LoadLiteral = .{
671 .load_literal = .{
604672 .rt = rt.id(),
605673 .imm19 = imm19,
606674 .opc = 0b01,
......@@ -618,7 +686,7 @@ pub const Instruction = union(enum) {
618686 imm16: u16,
619687 ) Instruction {
620688 return Instruction{
621 .ExceptionGeneration = .{
689 .exception_generation = .{
622690 .ll = ll,
623691 .op2 = op2,
624692 .imm16 = imm16,
......@@ -637,7 +705,7 @@ pub const Instruction = union(enum) {
637705 assert(rn.size() == 64);
638706
639707 return Instruction{
640 .UnconditionalBranchRegister = .{
708 .unconditional_branch_register = .{
641709 .op4 = op4,
642710 .rn = rn.id(),
643711 .op3 = op3,
......@@ -652,7 +720,7 @@ pub const Instruction = union(enum) {
652720 offset: i28,
653721 ) Instruction {
654722 return Instruction{
655 .UnconditionalBranchImmediate = .{
723 .unconditional_branch_immediate = .{
656724 .imm26 = @bitCast(u26, @intCast(i26, offset >> 2)),
657725 .op = op,
658726 },
......@@ -671,7 +739,7 @@ pub const Instruction = union(enum) {
671739 32 => {
672740 assert(shift.amount < 32);
673741 return Instruction{
674 .LogicalShiftedRegister = .{
742 .logical_shifted_register = .{
675743 .rd = rd.id(),
676744 .rn = rn.id(),
677745 .imm6 = shift.amount,
......@@ -685,7 +753,7 @@ pub const Instruction = union(enum) {
685753 },
686754 64 => {
687755 return Instruction{
688 .LogicalShiftedRegister = .{
756 .logical_shifted_register = .{
689757 .rd = rd.id(),
690758 .rn = rn.id(),
691759 .imm6 = shift.amount,
......@@ -710,7 +778,7 @@ pub const Instruction = union(enum) {
710778 shift: bool,
711779 ) Instruction {
712780 return Instruction{
713 .AddSubtractImmediate = .{
781 .add_subtract_immediate = .{
714782 .rd = rd.id(),
715783 .rn = rn.id(),
716784 .imm12 = imm12,
......@@ -726,6 +794,43 @@ pub const Instruction = union(enum) {
726794 };
727795 }
728796
797 fn conditionalBranch(
798 o0: u1,
799 o1: u1,
800 cond: Condition,
801 offset: i21,
802 ) Instruction {
803 assert(offset & 0b11 == 0b00);
804 return Instruction{
805 .conditional_branch = .{
806 .cond = @enumToInt(cond),
807 .o0 = o0,
808 .imm19 = @bitCast(u19, @intCast(i19, offset >> 2)),
809 .o1 = o1,
810 },
811 };
812 }
813
814 fn compareAndBranch(
815 op: u1,
816 rt: Register,
817 offset: i21,
818 ) Instruction {
819 assert(offset & 0b11 == 0b00);
820 return Instruction{
821 .compare_and_branch = .{
822 .rt = rt.id(),
823 .imm19 = @bitCast(u19, @intCast(i19, offset >> 2)),
824 .op = op,
825 .sf = switch (rt.size()) {
826 32 => 0b0,
827 64 => 0b1,
828 else => unreachable, // unexpected register size
829 },
830 },
831 };
832 }
833
729834 // Helper functions for assembly syntax functions
730835
731836 // Move wide (immediate)
......@@ -821,19 +926,19 @@ pub const Instruction = union(enum) {
821926 };
822927
823928 pub fn ldp(rt1: Register, rt2: Register, rn: Register, offset: LoadStorePairOffset) Instruction {
824 return loadStorePairOfRegisters(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), true);
929 return loadStoreRegisterPair(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), true);
825930 }
826931
827932 pub fn ldnp(rt1: Register, rt2: Register, rn: Register, offset: i9) Instruction {
828 return loadStorePairOfRegisters(rt1, rt2, rn, offset, 0, true);
933 return loadStoreRegisterPair(rt1, rt2, rn, offset, 0, true);
829934 }
830935
831936 pub fn stp(rt1: Register, rt2: Register, rn: Register, offset: LoadStorePairOffset) Instruction {
832 return loadStorePairOfRegisters(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), false);
937 return loadStoreRegisterPair(rt1, rt2, rn, offset.offset, @enumToInt(offset.encoding), false);
833938 }
834939
835940 pub fn stnp(rt1: Register, rt2: Register, rn: Register, offset: i9) Instruction {
836 return loadStorePairOfRegisters(rt1, rt2, rn, offset, 0, false);
941 return loadStoreRegisterPair(rt1, rt2, rn, offset, 0, false);
837942 }
838943
839944 // Exception generation
......@@ -885,7 +990,7 @@ pub const Instruction = union(enum) {
885990 // Nop
886991
887992 pub fn nop() Instruction {
888 return Instruction{ .NoOperation = .{} };
993 return Instruction{ .no_operation = .{} };
889994 }
890995
891996 // Logical (shifted register)
......@@ -939,6 +1044,22 @@ pub const Instruction = union(enum) {
9391044 pub fn subs(rd: Register, rn: Register, imm: u12, shift: bool) Instruction {
9401045 return addSubtractImmediate(0b1, 0b1, rd, rn, imm, shift);
9411046 }
1047
1048 // Conditional branch
1049
1050 pub fn bCond(cond: Condition, offset: i21) Instruction {
1051 return conditionalBranch(0b0, 0b0, cond, offset);
1052 }
1053
1054 // Compare and branch
1055
1056 pub fn cbz(rt: Register, offset: i21) Instruction {
1057 return compareAndBranch(0b0, rt, offset);
1058 }
1059
1060 pub fn cbnz(rt: Register, offset: i21) Instruction {
1061 return compareAndBranch(0b1, rt, offset);
1062 }
9421063};
9431064
9441065test {
......@@ -1092,6 +1213,14 @@ test "serialize instructions" {
10921213 .inst = Instruction.subs(.x0, .x5, 11, true),
10931214 .expected = 0b1_1_1_100010_1_0000_0000_1011_00101_00000,
10941215 },
1216 .{ // b.hi #-4
1217 .inst = Instruction.bCond(.hi, -4),
1218 .expected = 0b0101010_0_1111111111111111111_0_1000,
1219 },
1220 .{ // cbz x10, #40
1221 .inst = Instruction.cbz(.x10, 40),
1222 .expected = 0b1_011010_0_0000000000000001010_01010,
1223 },
10951224 };
10961225
10971226 for (testcases) |case| {
src/link/MachO.zig+2-2
......@@ -1256,7 +1256,7 @@ pub fn updateDecl(self: *MachO, module: *Module, decl: *Module.Decl) !void {
12561256 const inst = code_buffer.items[fixup.offset..][0..4];
12571257 var parsed = mem.bytesAsValue(meta.TagPayload(
12581258 aarch64.Instruction,
1259 aarch64.Instruction.PCRelativeAddress,
1259 aarch64.Instruction.pc_relative_address,
12601260 ), inst);
12611261 const this_page = @intCast(i32, this_addr >> 12);
12621262 const target_page = @intCast(i32, target_addr >> 12);
......@@ -1268,7 +1268,7 @@ pub fn updateDecl(self: *MachO, module: *Module, decl: *Module.Decl) !void {
12681268 const inst = code_buffer.items[fixup.offset + 4 ..][0..4];
12691269 var parsed = mem.bytesAsValue(meta.TagPayload(
12701270 aarch64.Instruction,
1271 aarch64.Instruction.LoadStoreRegister,
1271 aarch64.Instruction.load_store_register,
12721272 ), inst);
12731273 const narrowed = @truncate(u12, target_addr);
12741274 const offset = try math.divExact(u12, narrowed, 8);
src/link/MachO/Zld.zig+6-6
......@@ -1668,7 +1668,7 @@ fn doRelocs(self: *Zld) !void {
16681668 var parsed = mem.bytesAsValue(
16691669 meta.TagPayload(
16701670 aarch64.Instruction,
1671 aarch64.Instruction.UnconditionalBranchImmediate,
1671 aarch64.Instruction.unconditional_branch_immediate,
16721672 ),
16731673 inst,
16741674 );
......@@ -1688,7 +1688,7 @@ fn doRelocs(self: *Zld) !void {
16881688 var parsed = mem.bytesAsValue(
16891689 meta.TagPayload(
16901690 aarch64.Instruction,
1691 aarch64.Instruction.PCRelativeAddress,
1691 aarch64.Instruction.pc_relative_address,
16921692 ),
16931693 inst,
16941694 );
......@@ -1706,7 +1706,7 @@ fn doRelocs(self: *Zld) !void {
17061706 var parsed = mem.bytesAsValue(
17071707 meta.TagPayload(
17081708 aarch64.Instruction,
1709 aarch64.Instruction.AddSubtractImmediate,
1709 aarch64.Instruction.add_subtract_immediate,
17101710 ),
17111711 inst,
17121712 );
......@@ -1719,7 +1719,7 @@ fn doRelocs(self: *Zld) !void {
17191719 var parsed = mem.bytesAsValue(
17201720 meta.TagPayload(
17211721 aarch64.Instruction,
1722 aarch64.Instruction.LoadStoreRegister,
1722 aarch64.Instruction.load_store_register,
17231723 ),
17241724 inst,
17251725 );
......@@ -1774,7 +1774,7 @@ fn doRelocs(self: *Zld) !void {
17741774 const curr = mem.bytesAsValue(
17751775 meta.TagPayload(
17761776 aarch64.Instruction,
1777 aarch64.Instruction.AddSubtractImmediate,
1777 aarch64.Instruction.add_subtract_immediate,
17781778 ),
17791779 inst,
17801780 );
......@@ -1783,7 +1783,7 @@ fn doRelocs(self: *Zld) !void {
17831783 const curr = mem.bytesAsValue(
17841784 meta.TagPayload(
17851785 aarch64.Instruction,
1786 aarch64.Instruction.LoadStoreRegister,
1786 aarch64.Instruction.load_store_register,
17871787 ),
17881788 inst,
17891789 );