authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-08-23 16:54:32+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-05 14:54:31+02:00
logdb5a56da2488d9acec5e7aff4a678ea016a04338
tree144ef338a18bf7153438428c3d90109d12969386
parent902d83be653e2e9e72cdc4afc169c6e6245e5da4
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

test-behavior: re-enable float `vector cmp` tests on powerpc64

1 files changed, 0 insertions(+), 3 deletions(-)

test/behavior/floatop.zig-3
...@@ -228,7 +228,6 @@ test "vector cmp f32" {...@@ -228,7 +228,6 @@ test "vector cmp f32" {
228 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO228 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
229 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;229 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
230 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isArm()) return error.SkipZigTest;230 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isArm()) return error.SkipZigTest;
231 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
232 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;231 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
233232
234 try testCmpVector(f32);233 try testCmpVector(f32);
...@@ -250,7 +249,6 @@ test "vector cmp f128" {...@@ -250,7 +249,6 @@ test "vector cmp f128" {
250 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO249 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
251 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;250 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
252 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;251 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
253 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
254 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;252 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
255253
256 try testCmpVector(f128);254 try testCmpVector(f128);
...@@ -260,7 +258,6 @@ test "vector cmp f128" {...@@ -260,7 +258,6 @@ test "vector cmp f128" {
260test "vector cmp f80/c_longdouble" {258test "vector cmp f80/c_longdouble" {
261 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;259 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
262 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;260 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
263 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198
264 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;261 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
265 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;262 if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
266263