| ... | ... | @@ -228,7 +228,6 @@ test "vector cmp f32" { |
| 228 | 228 | if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO |
| 229 | 229 | if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; |
| 230 | 230 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isArm()) return error.SkipZigTest; |
| 231 | | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198 |
| 232 | 231 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; |
| 233 | 232 | |
| 234 | 233 | try testCmpVector(f32); |
| ... | ... | @@ -250,7 +249,6 @@ test "vector cmp f128" { |
| 250 | 249 | if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO |
| 251 | 250 | if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest; |
| 252 | 251 | if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; |
| 253 | | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198 |
| 254 | 252 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; |
| 255 | 253 | |
| 256 | 254 | try testCmpVector(f128); |
| ... | ... | @@ -260,7 +258,6 @@ test "vector cmp f128" { |
| 260 | 258 | test "vector cmp f80/c_longdouble" { |
| 261 | 259 | if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; |
| 262 | 260 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; |
| 263 | | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; // https://github.com/llvm/llvm-project/issues/214198 |
| 264 | 261 | if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; |
| 265 | 262 | if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest; |
| 266 | 263 | |