authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-16 13:35:30+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-18 00:36:52+02:00
logde3947608ceb6e4603e3d249fb07183e3a431536
tree4682e6e7c3f2285d82d882197dfc12a01583ce14
parent81fe640dd21c1ba2d8406f4e9bb996d32f30df80
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.debug: add CPU context and DWARF mappings for csky

3 files changed, 44 insertions(+), 1 deletions(-)

lib/std/debug/Dwarf.zig+3
...@@ -1431,6 +1431,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {...@@ -1431,6 +1431,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1431 return switch (arch) {1431 return switch (arch) {
1432 .aarch64, .aarch64_be => 32,1432 .aarch64, .aarch64_be => 32,
1433 .arm, .armeb, .thumb, .thumbeb => 15,1433 .arm, .armeb, .thumb, .thumbeb => 15,
1434 .csky => 64,
1434 .hexagon => 76,1435 .hexagon => 76,
1435 .lanai => 2,1436 .lanai => 2,
1436 .loongarch32, .loongarch64 => 64,1437 .loongarch32, .loongarch64 => 64,
...@@ -1450,6 +1451,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1450,6 +1451,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
1450 return switch (arch) {1451 return switch (arch) {
1451 .aarch64, .aarch64_be => 29,1452 .aarch64, .aarch64_be => 29,
1452 .arm, .armeb, .thumb, .thumbeb => 11,1453 .arm, .armeb, .thumb, .thumbeb => 11,
1454 .csky => 14,
1453 .hexagon => 30,1455 .hexagon => 30,
1454 .lanai => 5,1456 .lanai => 5,
1455 .loongarch32, .loongarch64 => 22,1457 .loongarch32, .loongarch64 => 22,
...@@ -1469,6 +1471,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1469,6 +1471,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
1469 return switch (arch) {1471 return switch (arch) {
1470 .aarch64, .aarch64_be => 31,1472 .aarch64, .aarch64_be => 31,
1471 .arm, .armeb, .thumb, .thumbeb => 13,1473 .arm, .armeb, .thumb, .thumbeb => 13,
1474 .csky => 14,
1472 .hexagon => 29,1475 .hexagon => 29,
1473 .lanai => 4,1476 .lanai => 4,
1474 .loongarch32, .loongarch64 => 3,1477 .loongarch32, .loongarch64 => 3,
lib/std/debug/SelfInfo/Elf.zig+2-1
...@@ -101,10 +101,11 @@ pub const can_unwind: bool = s: {...@@ -101,10 +101,11 @@ pub const can_unwind: bool = s: {
101 .x86,101 .x86,
102 .x86_64,102 .x86_64,
103 },103 },
104 // Not supported yet: arc, arm/armeb/thumb/thumbeb, csky, m68k, or1k, xtensa104 // Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, or1k, xtensa
105 .linux => &.{105 .linux => &.{
106 .aarch64,106 .aarch64,
107 .aarch64_be,107 .aarch64_be,
108 .csky,
108 .loongarch64,109 .loongarch64,
109 .mips,110 .mips,
110 .mipsel,111 .mipsel,
lib/std/debug/cpu_context.zig+39
...@@ -6,6 +6,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont...@@ -6,6 +6,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
6else switch (native_arch) {6else switch (native_arch) {
7 .aarch64, .aarch64_be => Aarch64,7 .aarch64, .aarch64_be => Aarch64,
8 .arm, .armeb, .thumb, .thumbeb => Arm,8 .arm, .armeb, .thumb, .thumbeb => Arm,
9 .csky => Csky,
9 .hexagon => Hexagon,10 .hexagon => Hexagon,
10 .lanai => Lanai,11 .lanai => Lanai,
11 .loongarch32, .loongarch64 => LoongArch,12 .loongarch32, .loongarch64 => LoongArch,
...@@ -74,6 +75,13 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {...@@ -74,6 +75,13 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
74 .sp = uc.mcontext.sp,75 .sp = uc.mcontext.sp,
75 .pc = uc.mcontext.pc,76 .pc = uc.mcontext.pc,
76 },77 },
78 .csky => .{
79 .r = uc.mcontext.r0_13 ++
80 [_]u32{ uc.mcontext.r14, uc.mcontext.r15 } ++
81 uc.mcontext.r16_30 ++
82 [_]u32{uc.mcontext.r31},
83 .pc = uc.mcontext.pc,
84 },
77 .hexagon, .loongarch32, .loongarch64, .mips, .mipsel, .mips64, .mips64el, .or1k => .{85 .hexagon, .loongarch32, .loongarch64, .mips, .mipsel, .mips64, .mips64el, .or1k => .{
78 .r = uc.mcontext.r,86 .r = uc.mcontext.r,
79 .pc = uc.mcontext.pc,87 .pc = uc.mcontext.pc,
...@@ -433,6 +441,37 @@ const Aarch64 = extern struct {...@@ -433,6 +441,37 @@ const Aarch64 = extern struct {
433 }441 }
434};442};
435443
444/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
445const Csky = extern struct {
446 /// The numbered general-purpose registers r0 - r31.
447 r: [32]u32,
448 pc: u32,
449
450 pub inline fn current() Csky {
451 var ctx: Csky = undefined;
452 asm volatile (
453 \\ stm r0-r31, (t0)
454 \\ grs t1, 1f
455 \\1:
456 \\ st32.w t1, (t0, 128)
457 :
458 : [ctx] "{r12}" (&ctx),
459 : .{ .r13 = true, .memory = true });
460 return ctx;
461 }
462
463 pub fn dwarfRegisterBytes(ctx: *Csky, register_num: u16) DwarfRegisterError![]u8 {
464 switch (register_num) {
465 0...31 => return @ptrCast(&ctx.r[register_num]),
466 64 => return @ptrCast(&ctx.pc),
467
468 32...63 => return error.UnsupportedRegister, // f0 - f31
469
470 else => return error.InvalidRegister,
471 }
472 }
473};
474
436/// This is an `extern struct` so that inline assembly in `current` can use field offsets.475/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
437const Hexagon = extern struct {476const Hexagon = extern struct {
438 /// The numbered general-purpose registers r0 - r31.477 /// The numbered general-purpose registers r0 - r31.