| ... | @@ -1117,13 +1117,11 @@ fn truncRegister( | ... | @@ -1117,13 +1117,11 @@ fn truncRegister( |
| 1117 | }); | 1117 | }); |
| 1118 | }, | 1118 | }, |
| 1119 | 32, 64 => { | 1119 | 32, 64 => { |
| 1120 | assert(dest_reg.size() == operand_reg.size()); | | |
| 1121 | | | |
| 1122 | _ = try self.addInst(.{ | 1120 | _ = try self.addInst(.{ |
| 1123 | .tag = .mov_register, | 1121 | .tag = .mov_register, |
| 1124 | .data = .{ .rr = .{ | 1122 | .data = .{ .rr = .{ |
| 1125 | .rd = dest_reg, | 1123 | .rd = if (int_bits == 32) dest_reg.toW() else dest_reg.toX(), |
| 1126 | .rn = operand_reg, | 1124 | .rn = if (int_bits == 32) operand_reg.toW() else operand_reg.toX(), |
| 1127 | } }, | 1125 | } }, |
| 1128 | }); | 1126 | }); |
| 1129 | }, | 1127 | }, |