| author | |
| committer | |
| log | df0212bf47974b4e676a5bb97aac5ab381d6cbf3 |
| tree | cdd682df95b9c9ec015f55d92e26654c82dfc92a |
| parent | 1d680459197e7ba5e163d99e07fdfe54c2ad9225 |
1 files changed, 2 insertions(+), 4 deletions(-)
src/arch/aarch64/CodeGen.zig+2-4| ... | ... | @@ -1117,13 +1117,11 @@ fn truncRegister( |
| 1117 | 1117 | }); |
| 1118 | 1118 | }, |
| 1119 | 1119 | 32, 64 => { |
| 1120 | assert(dest_reg.size() == operand_reg.size()); | |
| 1121 | ||
| 1122 | 1120 | _ = try self.addInst(.{ |
| 1123 | 1121 | .tag = .mov_register, |
| 1124 | 1122 | .data = .{ .rr = .{ |
| 1125 | .rd = dest_reg, | |
| 1126 | .rn = operand_reg, | |
| 1123 | .rd = if (int_bits == 32) dest_reg.toW() else dest_reg.toX(), | |
| 1124 | .rn = if (int_bits == 32) operand_reg.toW() else operand_reg.toX(), | |
| 1127 | 1125 | } }, |
| 1128 | 1126 | }); |
| 1129 | 1127 | }, |