authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-09-03 20:36:01+02:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-09-07 22:42:57+02:00
loge0167ae0e3f0e6c6a667b372b21c322d47ccd92d
tree27b8d51339716708ae8398f7683aa7f57e48e245
parent619d82234ecbb8a130e827e9de6f545288649a58

x86_64: allow for any index register in complex SIB encodings

This relieves register pressure, and reduce generated code size (since now we can use the same index register for both `mov_scale_src` and `mov_scale_dst` MIR instructions). Fix lowering of ModRM + SIB encodings where index register is extended - previously, we would carelessly ignore the fact generating incorrect encodings.

3 files changed, 154 insertions(+), 106 deletions(-)

src/arch/x86_64/CodeGen.zig+38-66
......@@ -5932,7 +5932,6 @@ const InlineMemcpyOpts = struct {
59325932 dest_stack_base: ?Register = null,
59335933};
59345934
5935/// Spills .rax and .rcx.
59365935fn genInlineMemcpy(
59375936 self: *Self,
59385937 dst_ptr: MCValue,
......@@ -5940,19 +5939,6 @@ fn genInlineMemcpy(
59405939 len: MCValue,
59415940 opts: InlineMemcpyOpts,
59425941) InnerError!void {
5943 // TODO: Preserve contents of .rax and .rcx if not free and locked, and then restore
5944 // How can we do this without context if the value inside .rax or .rcx we preserve contains
5945 // value needed to perform the memcpy in the first place?
5946 // I think we should have an accumulator-based context that we pass with each subsequent helper
5947 // call until we resolve the entire instruction.
5948 try self.register_manager.getReg(.rax, null);
5949 try self.register_manager.getReg(.rcx, null);
5950
5951 const reg_locks = self.register_manager.lockRegsAssumeUnused(2, .{ .rax, .rcx });
5952 defer for (reg_locks) |lock| {
5953 self.register_manager.unlockReg(lock);
5954 };
5955
59565942 const ssbase_lock: ?RegisterLock = if (opts.source_stack_base) |reg|
59575943 self.register_manager.lockReg(reg)
59585944 else
......@@ -5965,7 +5951,13 @@ fn genInlineMemcpy(
59655951 null;
59665952 defer if (dsbase_lock) |lock| self.register_manager.unlockReg(lock);
59675953
5968 const dst_addr_reg = try self.register_manager.allocReg(null, gp);
5954 const regs = try self.register_manager.allocRegs(5, .{ null, null, null, null, null }, gp);
5955 const dst_addr_reg = regs[0];
5956 const src_addr_reg = regs[1];
5957 const index_reg = regs[2].to64();
5958 const count_reg = regs[3].to64();
5959 const tmp_reg = regs[4].to8();
5960
59695961 switch (dst_ptr) {
59705962 .memory,
59715963 .got_load,
......@@ -5998,10 +5990,7 @@ fn genInlineMemcpy(
59985990 return self.fail("TODO implement memcpy for setting stack when dest is {}", .{dst_ptr});
59995991 },
60005992 }
6001 const dst_addr_reg_lock = self.register_manager.lockRegAssumeUnused(dst_addr_reg);
6002 defer self.register_manager.unlockReg(dst_addr_reg_lock);
60035993
6004 const src_addr_reg = try self.register_manager.allocReg(null, gp);
60055994 switch (src_ptr) {
60065995 .memory,
60075996 .got_load,
......@@ -6034,26 +6023,13 @@ fn genInlineMemcpy(
60346023 return self.fail("TODO implement memcpy for setting stack when src is {}", .{src_ptr});
60356024 },
60366025 }
6037 const src_addr_reg_lock = self.register_manager.lockRegAssumeUnused(src_addr_reg);
6038 defer self.register_manager.unlockReg(src_addr_reg_lock);
6039
6040 const regs = try self.register_manager.allocRegs(2, .{ null, null }, gp);
6041 const count_reg = regs[0].to64();
6042 const tmp_reg = regs[1].to8();
60436026
60446027 try self.genSetReg(Type.usize, count_reg, len);
60456028
6046 // mov rcx, 0
6047 _ = try self.addInst(.{
6048 .tag = .mov,
6049 .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rcx }),
6050 .data = .{ .imm = 0 },
6051 });
6052
6053 // mov rax, 0
6029 // mov index_reg, 0
60546030 _ = try self.addInst(.{
60556031 .tag = .mov,
6056 .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
6032 .ops = Mir.Inst.Ops.encode(.{ .reg1 = index_reg }),
60576033 .data = .{ .imm = 0 },
60586034 });
60596035
......@@ -6075,37 +6051,30 @@ fn genInlineMemcpy(
60756051 } },
60766052 });
60776053
6078 // mov tmp, [addr + rcx]
6054 // mov tmp, [addr + index_reg]
60796055 _ = try self.addInst(.{
60806056 .tag = .mov_scale_src,
60816057 .ops = Mir.Inst.Ops.encode(.{
60826058 .reg1 = tmp_reg.to8(),
60836059 .reg2 = src_addr_reg,
60846060 }),
6085 .data = .{ .imm = 0 },
6061 .data = .{ .payload = try self.addExtra(Mir.IndexRegisterDisp.encode(index_reg, 0)) },
60866062 });
60876063
6088 // mov [stack_offset + rax], tmp
6064 // mov [stack_offset + index_reg], tmp
60896065 _ = try self.addInst(.{
60906066 .tag = .mov_scale_dst,
60916067 .ops = Mir.Inst.Ops.encode(.{
60926068 .reg1 = dst_addr_reg,
60936069 .reg2 = tmp_reg.to8(),
60946070 }),
6095 .data = .{ .imm = 0 },
6071 .data = .{ .payload = try self.addExtra(Mir.IndexRegisterDisp.encode(index_reg, 0)) },
60966072 });
60976073
6098 // add rcx, 1
6074 // add index_reg, 1
60996075 _ = try self.addInst(.{
61006076 .tag = .add,
6101 .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rcx }),
6102 .data = .{ .imm = 1 },
6103 });
6104
6105 // add rax, 1
6106 _ = try self.addInst(.{
6107 .tag = .add,
6108 .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
6077 .ops = Mir.Inst.Ops.encode(.{ .reg1 = index_reg }),
61096078 .data = .{ .imm = 1 },
61106079 });
61116080
......@@ -6127,7 +6096,6 @@ fn genInlineMemcpy(
61276096 try self.performReloc(loop_reloc);
61286097}
61296098
6130/// Spills .rax register.
61316099fn genInlineMemset(
61326100 self: *Self,
61336101 dst_ptr: MCValue,
......@@ -6135,12 +6103,22 @@ fn genInlineMemset(
61356103 len: MCValue,
61366104 opts: InlineMemcpyOpts,
61376105) InnerError!void {
6138 // TODO preserve contents of .rax and then restore
6139 try self.register_manager.getReg(.rax, null);
6140 const rax_lock = self.register_manager.lockRegAssumeUnused(.rax);
6141 defer self.register_manager.unlockReg(rax_lock);
6106 const ssbase_lock: ?RegisterLock = if (opts.source_stack_base) |reg|
6107 self.register_manager.lockReg(reg)
6108 else
6109 null;
6110 defer if (ssbase_lock) |reg| self.register_manager.unlockReg(reg);
6111
6112 const dsbase_lock: ?RegisterLock = if (opts.dest_stack_base) |reg|
6113 self.register_manager.lockReg(reg)
6114 else
6115 null;
6116 defer if (dsbase_lock) |lock| self.register_manager.unlockReg(lock);
6117
6118 const regs = try self.register_manager.allocRegs(2, .{ null, null }, gp);
6119 const addr_reg = regs[0];
6120 const index_reg = regs[1].to64();
61426121
6143 const addr_reg = try self.register_manager.allocReg(null, gp);
61446122 switch (dst_ptr) {
61456123 .memory,
61466124 .got_load,
......@@ -6173,17 +6151,15 @@ fn genInlineMemset(
61736151 return self.fail("TODO implement memcpy for setting stack when dest is {}", .{dst_ptr});
61746152 },
61756153 }
6176 const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
6177 defer self.register_manager.unlockReg(addr_reg_lock);
61786154
6179 try self.genSetReg(Type.usize, .rax, len);
6180 try self.genBinOpMir(.sub, Type.usize, .{ .register = .rax }, .{ .immediate = 1 });
6155 try self.genSetReg(Type.usize, index_reg, len);
6156 try self.genBinOpMir(.sub, Type.usize, .{ .register = index_reg }, .{ .immediate = 1 });
61816157
61826158 // loop:
6183 // cmp rax, -1
6159 // cmp index_reg, -1
61846160 const loop_start = try self.addInst(.{
61856161 .tag = .cmp,
6186 .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
6162 .ops = Mir.Inst.Ops.encode(.{ .reg1 = index_reg }),
61876163 .data = .{ .imm = @bitCast(u32, @as(i32, -1)) },
61886164 });
61896165
......@@ -6202,24 +6178,20 @@ fn genInlineMemset(
62026178 if (x > math.maxInt(i32)) {
62036179 return self.fail("TODO inline memset for value immediate larger than 32bits", .{});
62046180 }
6205 // mov byte ptr [rbp + rax + stack_offset], imm
6206 const payload = try self.addExtra(Mir.ImmPair{
6207 .dest_off = 0,
6208 .operand = @truncate(u32, x),
6209 });
6181 // mov byte ptr [rbp + index_reg + stack_offset], imm
62106182 _ = try self.addInst(.{
62116183 .tag = .mov_mem_index_imm,
62126184 .ops = Mir.Inst.Ops.encode(.{ .reg1 = addr_reg }),
6213 .data = .{ .payload = payload },
6185 .data = .{ .payload = try self.addExtra(Mir.IndexRegisterDispImm.encode(index_reg, 0, @truncate(u32, x))) },
62146186 });
62156187 },
62166188 else => return self.fail("TODO inline memset for value of type {}", .{value}),
62176189 }
62186190
6219 // sub rax, 1
6191 // sub index_reg, 1
62206192 _ = try self.addInst(.{
62216193 .tag = .sub,
6222 .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
6194 .ops = Mir.Inst.Ops.encode(.{ .reg1 = index_reg }),
62236195 .data = .{ .imm = 1 },
62246196 });
62256197
src/arch/x86_64/Emit.zig+39-30
......@@ -615,14 +615,15 @@ inline fn immOpSize(u_imm: u32) u6 {
615615fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
616616 const ops = emit.mir.instructions.items(.ops)[inst].decode();
617617 const scale = ops.flags;
618 const imm = emit.mir.instructions.items(.data)[inst].imm;
619 // OP reg1, [reg2 + scale*rcx + imm32]
618 const payload = emit.mir.instructions.items(.data)[inst].payload;
619 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();
620 // OP reg1, [reg2 + scale*index + imm32]
620621 const scale_index = ScaleIndex{
621622 .scale = scale,
622 .index = .rcx,
623 .index = index_reg_disp.index,
623624 };
624625 return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
625 .disp = imm,
626 .disp = index_reg_disp.disp,
626627 .base = ops.reg2,
627628 .scale_index = scale_index,
628629 }), emit.code);
......@@ -631,22 +632,16 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
631632fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
632633 const ops = emit.mir.instructions.items(.ops)[inst].decode();
633634 const scale = ops.flags;
634 const imm = emit.mir.instructions.items(.data)[inst].imm;
635 const payload = emit.mir.instructions.items(.data)[inst].payload;
636 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();
635637 const scale_index = ScaleIndex{
636638 .scale = scale,
637 .index = .rax,
639 .index = index_reg_disp.index,
638640 };
639 if (ops.reg2 == .none) {
640 // OP qword ptr [reg1 + scale*rax + 0], imm32
641 return lowerToMiEnc(tag, RegisterOrMemory.mem(.qword_ptr, .{
642 .disp = 0,
643 .base = ops.reg1,
644 .scale_index = scale_index,
645 }), imm, emit.code);
646 }
647 // OP [reg1 + scale*rax + imm32], reg2
641 assert(ops.reg2 != .none);
642 // OP [reg1 + scale*index + imm32], reg2
648643 return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg2.size()), .{
649 .disp = imm,
644 .disp = index_reg_disp.disp,
650645 .base = ops.reg1,
651646 .scale_index = scale_index,
652647 }), ops.reg2, emit.code);
......@@ -656,24 +651,24 @@ fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
656651 const ops = emit.mir.instructions.items(.ops)[inst].decode();
657652 const scale = ops.flags;
658653 const payload = emit.mir.instructions.items(.data)[inst].payload;
659 const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
654 const index_reg_disp_imm = emit.mir.extraData(Mir.IndexRegisterDispImm, payload).data.decode();
660655 const scale_index = ScaleIndex{
661656 .scale = scale,
662 .index = .rax,
657 .index = index_reg_disp_imm.index,
663658 };
664 // OP qword ptr [reg1 + scale*rax + imm32], imm32
659 // OP qword ptr [reg1 + scale*index + imm32], imm32
665660 return lowerToMiEnc(tag, RegisterOrMemory.mem(.qword_ptr, .{
666 .disp = imm_pair.dest_off,
661 .disp = index_reg_disp_imm.disp,
667662 .base = ops.reg1,
668663 .scale_index = scale_index,
669 }), imm_pair.operand, emit.code);
664 }), index_reg_disp_imm.imm, emit.code);
670665}
671666
672667fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
673668 const ops = emit.mir.instructions.items(.ops)[inst].decode();
674669 assert(ops.reg2 == .none);
675670 const payload = emit.mir.instructions.items(.data)[inst].payload;
676 const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
671 const index_reg_disp_imm = emit.mir.extraData(Mir.IndexRegisterDispImm, payload).data.decode();
677672 const ptr_size: Memory.PtrSize = switch (ops.flags) {
678673 0b00 => .byte_ptr,
679674 0b01 => .word_ptr,
......@@ -682,14 +677,14 @@ fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!v
682677 };
683678 const scale_index = ScaleIndex{
684679 .scale = 0,
685 .index = .rax,
680 .index = index_reg_disp_imm.index,
686681 };
687 // OP ptr [reg1 + rax*1 + imm32], imm32
682 // OP ptr [reg1 + index + imm32], imm32
688683 return lowerToMiEnc(tag, RegisterOrMemory.mem(ptr_size, .{
689 .disp = imm_pair.dest_off,
684 .disp = index_reg_disp_imm.disp,
690685 .base = ops.reg1,
691686 .scale_index = scale_index,
692 }), imm_pair.operand, emit.code);
687 }), index_reg_disp_imm.imm, emit.code);
693688}
694689
695690fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
......@@ -957,18 +952,19 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
957952 mem.writeIntLittle(i32, emit.code.items[end_offset - 4 ..][0..4], disp);
958953 },
959954 0b10 => {
960 // lea reg, [rbp + rcx + imm32]
961 const imm = emit.mir.instructions.items(.data)[inst].imm;
955 // lea reg, [rbp + index + imm32]
956 const payload = emit.mir.instructions.items(.data)[inst].payload;
957 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();
962958 const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;
963959 const scale_index = ScaleIndex{
964960 .scale = 0,
965 .index = .rcx,
961 .index = index_reg_disp.index,
966962 };
967963 return lowerToRmEnc(
968964 .lea,
969965 ops.reg1,
970966 RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
971 .disp = imm,
967 .disp = index_reg_disp.disp,
972968 .base = src_reg,
973969 .scale_index = scale_index,
974970 }),
......@@ -2255,6 +2251,7 @@ fn lowerToMxEnc(tag: Tag, reg_or_mem: RegisterOrMemory, enc: Encoding, code: *st
22552251 encoder.rex(.{
22562252 .w = wide,
22572253 .b = base.isExtended(),
2254 .x = if (mem_op.scale_index) |si| si.index.isExtended() else false,
22582255 });
22592256 }
22602257 opc.encode(encoder);
......@@ -2360,10 +2357,12 @@ fn lowerToMiXEnc(
23602357 encoder.rex(.{
23612358 .w = dst_mem.ptr_size == .qword_ptr,
23622359 .b = base.isExtended(),
2360 .x = if (dst_mem.scale_index) |si| si.index.isExtended() else false,
23632361 });
23642362 } else {
23652363 encoder.rex(.{
23662364 .w = dst_mem.ptr_size == .qword_ptr,
2365 .x = if (dst_mem.scale_index) |si| si.index.isExtended() else false,
23672366 });
23682367 }
23692368 opc.encode(encoder);
......@@ -2415,11 +2414,13 @@ fn lowerToRmEnc(
24152414 .w = setRexWRegister(reg),
24162415 .r = reg.isExtended(),
24172416 .b = base.isExtended(),
2417 .x = if (src_mem.scale_index) |si| si.index.isExtended() else false,
24182418 });
24192419 } else {
24202420 encoder.rex(.{
24212421 .w = setRexWRegister(reg),
24222422 .r = reg.isExtended(),
2423 .x = if (src_mem.scale_index) |si| si.index.isExtended() else false,
24232424 });
24242425 }
24252426 opc.encode(encoder);
......@@ -2460,11 +2461,13 @@ fn lowerToMrEnc(
24602461 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
24612462 .r = reg.isExtended(),
24622463 .b = base.isExtended(),
2464 .x = if (dst_mem.scale_index) |si| si.index.isExtended() else false,
24632465 });
24642466 } else {
24652467 encoder.rex(.{
24662468 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
24672469 .r = reg.isExtended(),
2470 .x = if (dst_mem.scale_index) |si| si.index.isExtended() else false,
24682471 });
24692472 }
24702473 opc.encode(encoder);
......@@ -2504,11 +2507,13 @@ fn lowerToRmiEnc(
25042507 .w = setRexWRegister(reg),
25052508 .r = reg.isExtended(),
25062509 .b = base.isExtended(),
2510 .x = if (src_mem.scale_index) |si| si.index.isExtended() else false,
25072511 });
25082512 } else {
25092513 encoder.rex(.{
25102514 .w = setRexWRegister(reg),
25112515 .r = reg.isExtended(),
2516 .x = if (src_mem.scale_index) |si| si.index.isExtended() else false,
25122517 });
25132518 }
25142519 opc.encode(encoder);
......@@ -2545,10 +2550,12 @@ fn lowerToVmEnc(
25452550 vex.rex(.{
25462551 .r = reg.isExtended(),
25472552 .b = base.isExtended(),
2553 .x = if (src_mem.scale_index) |si| si.index.isExtended() else false,
25482554 });
25492555 } else {
25502556 vex.rex(.{
25512557 .r = reg.isExtended(),
2558 .x = if (src_mem.scale_index) |si| si.index.isExtended() else false,
25522559 });
25532560 }
25542561 encoder.vex(enc.prefix);
......@@ -2585,10 +2592,12 @@ fn lowerToMvEnc(
25852592 vex.rex(.{
25862593 .r = reg.isExtended(),
25872594 .b = base.isExtended(),
2595 .x = if (dst_mem.scale_index) |si| si.index.isExtended() else false,
25882596 });
25892597 } else {
25902598 vex.rex(.{
25912599 .r = reg.isExtended(),
2600 .x = if (dst_mem.scale_index) |si| si.index.isExtended() else false,
25922601 });
25932602 }
25942603 encoder.vex(enc.prefix);
src/arch/x86_64/Mir.zig+77-10
......@@ -44,25 +44,28 @@ pub const Inst = struct {
4444 /// 0b01 word ptr [reg1 + imm32], imm16
4545 /// 0b10 dword ptr [reg1 + imm32], imm32
4646 /// 0b11 qword ptr [reg1 + imm32], imm32 (sign-extended to imm64)
47 /// Notes:
48 /// * Uses `ImmPair` as payload
4749 adc_mem_imm,
4850
49 /// form: reg1, [reg2 + scale*rcx + imm32]
51 /// form: reg1, [reg2 + scale*index + imm32]
5052 /// ops flags scale
5153 /// 0b00 1
5254 /// 0b01 2
5355 /// 0b10 4
5456 /// 0b11 8
57 /// Notes:
58 /// * Uses `IndexRegisterDisp` as payload
5559 adc_scale_src,
5660
57 /// form: [reg1 + scale*rax + imm32], reg2
58 /// form: [reg1 + scale*rax + 0], imm32
61 /// form: [reg1 + scale*index + imm32], reg2
5962 /// ops flags scale
6063 /// 0b00 1
6164 /// 0b01 2
6265 /// 0b10 4
6366 /// 0b11 8
6467 /// Notes:
65 /// * If reg2 is `none` then it means Data field `imm` is used as the immediate.
68 /// * Uses `IndexRegisterDisp` payload.
6669 adc_scale_dst,
6770
6871 /// form: [reg1 + scale*rax + imm32], imm32
......@@ -72,14 +75,16 @@ pub const Inst = struct {
7275 /// 0b10 4
7376 /// 0b11 8
7477 /// Notes:
75 /// * Data field `payload` points at `ImmPair`.
78 /// * Uses `IndexRegisterDispImm` payload.
7679 adc_scale_imm,
7780
7881 /// ops flags: form:
79 /// 0b00 byte ptr [reg1 + rax + imm32], imm8
80 /// 0b01 word ptr [reg1 + rax + imm32], imm16
81 /// 0b10 dword ptr [reg1 + rax + imm32], imm32
82 /// 0b11 qword ptr [reg1 + rax + imm32], imm32 (sign-extended to imm64)
82 /// 0b00 byte ptr [reg1 + index + imm32], imm8
83 /// 0b01 word ptr [reg1 + index + imm32], imm16
84 /// 0b10 dword ptr [reg1 + index + imm32], imm32
85 /// 0b11 qword ptr [reg1 + index + imm32], imm32 (sign-extended to imm64)
86 /// Notes:
87 /// * Uses `IndexRegisterDispImm` payload.
8388 adc_mem_index_imm,
8489
8590 // The following instructions all have the same encoding as `adc`.
......@@ -174,7 +179,9 @@ pub const Inst = struct {
174179 /// 0b00 reg1, [reg2 + imm32]
175180 /// 0b00 reg1, [ds:imm32]
176181 /// 0b01 reg1, [rip + imm32]
177 /// 0b10 reg1, [reg2 + rcx + imm32]
182 /// 0b10 reg1, [reg2 + index + imm32]
183 /// Notes:
184 /// * 0b10 uses `IndexRegisterDisp` payload
178185 lea,
179186
180187 /// ops flags: form:
......@@ -461,6 +468,66 @@ pub const Inst = struct {
461468 }
462469};
463470
471pub const IndexRegisterDisp = struct {
472 /// Index register to use with SIB-based encoding
473 index: u32,
474
475 /// Displacement value
476 disp: u32,
477
478 pub fn encode(index: Register, disp: u32) IndexRegisterDisp {
479 return .{
480 .index = @enumToInt(index),
481 .disp = disp,
482 };
483 }
484
485 pub fn decode(this: IndexRegisterDisp) struct {
486 index: Register,
487 disp: u32,
488 } {
489 return .{
490 .index = @intToEnum(Register, this.index),
491 .disp = this.disp,
492 };
493 }
494};
495
496/// TODO: would it be worth making `IndexRegisterDisp` and `IndexRegisterDispImm` a variable length list
497/// instead of having two structs, one a superset of the other one?
498pub const IndexRegisterDispImm = struct {
499 /// Index register to use with SIB-based encoding
500 index: u32,
501
502 /// Displacement value
503 disp: u32,
504
505 /// Immediate
506 imm: u32,
507
508 pub fn encode(index: Register, disp: u32, imm: u32) IndexRegisterDispImm {
509 return .{
510 .index = @enumToInt(index),
511 .disp = disp,
512 .imm = imm,
513 };
514 }
515
516 pub fn decode(this: IndexRegisterDispImm) struct {
517 index: Register,
518 disp: u32,
519 imm: u32,
520 } {
521 return .{
522 .index = @intToEnum(Register, this.index),
523 .disp = this.disp,
524 .imm = this.imm,
525 };
526 }
527};
528
529/// Used in conjunction with `SaveRegisterList` payload to transfer a list of used registers
530/// in a compact manner.
464531pub const RegisterList = struct {
465532 bitset: BitSet = BitSet.initEmpty(),
466533