| ... | ... | @@ -20,6 +20,7 @@ pub const Register = enum(u8) { |
| 20 | 20 | al, bl, cl, dl, ah, ch, dh, bh, |
| 21 | 21 | r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b, |
| 22 | 22 | |
| 23 | /// Returns the bit-width of the register. |
| 23 | 24 | pub fn size(self: @This()) u7 { |
| 24 | 25 | return switch (@enumToInt(self)) { |
| 25 | 26 | 0...15 => 64, |
| ... | ... | @@ -30,10 +31,20 @@ pub const Register = enum(u8) { |
| 30 | 31 | }; |
| 31 | 32 | } |
| 32 | 33 | |
| 34 | /// Returns whether the register is *extended*. Extended registers are the |
| 35 | /// new registers added with amd64, r8 through r15. This also includes any |
| 36 | /// other variant of access to those registers, such as r8b, r15d, and so |
| 37 | /// on. This is needed because access to these registers requires special |
| 38 | /// handling via the REX prefix, via the B or R bits, depending on context. |
| 33 | 39 | pub fn isExtended(self: @This()) bool { |
| 34 | 40 | return @enumToInt(self) & 0x08 != 0; |
| 35 | 41 | } |
| 36 | 42 | |
| 43 | /// This returns the 4-bit register ID, which is used in practically every |
| 44 | /// opcode. Note that bit 3 (the highest bit) is *never* used directly in |
| 45 | /// an instruction (@see isExtended), and requires special handling. The |
| 46 | /// lower three bits are often embedded directly in instructions (such as |
| 47 | /// the B8 variant of moves), or used in R/M bytes. |
| 37 | 48 | pub fn id(self: @This()) u4 { |
| 38 | 49 | return @truncate(u4, @enumToInt(self)); |
| 39 | 50 | } |