authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-03-10 19:32:48+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-03-11 20:05:50+01:00
loge34e7d5ad1a61c66c145af612e11b7c6500caf79
treee79c62e0ef8f1ce885b7dea6b842ccf58ef4db07
parentfe1fab4a8ee8d908ab592c63bbc35bbbaa1ed0bf

x86_64: add missing decodings for .movsx

2 files changed, 11 insertions(+), 1 deletions(-)

src/arch/x86_64/CodeGen.zig+1-1
......@@ -5841,7 +5841,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
58415841 if (intrinsicsAllowed(self.target.*, ty)) {
58425842 const tag: Mir.Inst.Tag = switch (ty.tag()) {
58435843 .f32 => .movss,
5844 .f64 => .movsx,
5844 .f64 => .movsd,
58455845 else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
58465846 };
58475847 const ptr_size: Memory.PtrSize = switch (ty.tag()) {
src/arch/x86_64/Emit.zig+10
......@@ -328,6 +328,16 @@ fn mirMovsx(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
328328 op1 = .{ .reg = data.rr.r1 };
329329 op2 = .{ .reg = data.rr.r2 };
330330 },
331 .rm_sib => {
332 const msib = emit.mir.extraData(Mir.MemorySib, data.rx.payload).data;
333 op1 = .{ .reg = data.rx.r1 };
334 op2 = .{ .mem = Mir.MemorySib.decode(msib) };
335 },
336 .rm_rip => {
337 const mrip = emit.mir.extraData(Mir.MemoryRip, data.rx.payload).data;
338 op1 = .{ .reg = data.rx.r1 };
339 op2 = .{ .mem = Mir.MemoryRip.decode(mrip) };
340 },
331341 else => unreachable, // TODO
332342 }
333343