authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-06-22 22:13:49-07:00
committergravatar for mlugg@mlugg.co.ukMatthew Lugg <mlugg@mlugg.co.uk> 2024-06-23 15:26:14+01:00
loge73ae94b3640ef74c9614c2da6a0200ff444f3e8
tree247f825ed81e6f85eb35ed69cdbaad076d53d0ec
parentf3655fd07dbd30d3c7ed95d92df192a78b081a3a

riscv: remove deprecated `Module` usages

4 files changed, 14 insertions(+), 22 deletions(-)

src/arch/riscv64/CodeGen.zig+8-10
...@@ -11,12 +11,10 @@ const Type = @import("../../type.zig").Type;...@@ -11,12 +11,10 @@ const Type = @import("../../type.zig").Type;
11const Value = @import("../../Value.zig");11const Value = @import("../../Value.zig");
12const link = @import("../../link.zig");12const link = @import("../../link.zig");
13const Zcu = @import("../../Zcu.zig");13const Zcu = @import("../../Zcu.zig");
14/// Deprecated.
15const Module = Zcu;
16const Package = @import("../../Package.zig");14const Package = @import("../../Package.zig");
17const InternPool = @import("../../InternPool.zig");15const InternPool = @import("../../InternPool.zig");
18const Compilation = @import("../../Compilation.zig");16const Compilation = @import("../../Compilation.zig");
19const ErrorMsg = Module.ErrorMsg;17const ErrorMsg = Zcu.ErrorMsg;
20const Target = std.Target;18const Target = std.Target;
21const Allocator = mem.Allocator;19const Allocator = mem.Allocator;
22const trace = @import("../../tracy.zig").trace;20const trace = @import("../../tracy.zig").trace;
...@@ -61,7 +59,7 @@ args: []MCValue,...@@ -61,7 +59,7 @@ args: []MCValue,
61ret_mcv: InstTracking,59ret_mcv: InstTracking,
62fn_type: Type,60fn_type: Type,
63arg_index: usize,61arg_index: usize,
64src_loc: Module.SrcLoc,62src_loc: Zcu.SrcLoc,
6563
66/// MIR Instructions64/// MIR Instructions
67mir_instructions: std.MultiArrayList(Mir.Inst) = .{},65mir_instructions: std.MultiArrayList(Mir.Inst) = .{},
...@@ -543,13 +541,13 @@ const FrameAlloc = struct {...@@ -543,13 +541,13 @@ const FrameAlloc = struct {
543 .ref_count = 0,541 .ref_count = 0,
544 };542 };
545 }543 }
546 fn initType(ty: Type, zcu: *Module) FrameAlloc {544 fn initType(ty: Type, zcu: *Zcu) FrameAlloc {
547 return init(.{545 return init(.{
548 .size = ty.abiSize(zcu),546 .size = ty.abiSize(zcu),
549 .alignment = ty.abiAlignment(zcu),547 .alignment = ty.abiAlignment(zcu),
550 });548 });
551 }549 }
552 fn initSpill(ty: Type, zcu: *Module) FrameAlloc {550 fn initSpill(ty: Type, zcu: *Zcu) FrameAlloc {
553 const abi_size = ty.abiSize(zcu);551 const abi_size = ty.abiSize(zcu);
554 const spill_size = if (abi_size < 8)552 const spill_size = if (abi_size < 8)
555 math.ceilPowerOfTwoAssert(u64, abi_size)553 math.ceilPowerOfTwoAssert(u64, abi_size)
...@@ -698,7 +696,7 @@ const CallView = enum(u1) {...@@ -698,7 +696,7 @@ const CallView = enum(u1) {
698696
699pub fn generate(697pub fn generate(
700 bin_file: *link.File,698 bin_file: *link.File,
701 src_loc: Module.SrcLoc,699 src_loc: Zcu.SrcLoc,
702 func_index: InternPool.Index,700 func_index: InternPool.Index,
703 air: Air,701 air: Air,
704 liveness: Liveness,702 liveness: Liveness,
...@@ -922,7 +920,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir)...@@ -922,7 +920,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir)
922}920}
923921
924const FormatDeclData = struct {922const FormatDeclData = struct {
925 mod: *Module,923 mod: *Zcu,
926 decl_index: InternPool.DeclIndex,924 decl_index: InternPool.DeclIndex,
927};925};
928fn formatDecl(926fn formatDecl(
...@@ -6636,7 +6634,7 @@ fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool {...@@ -6636,7 +6634,7 @@ fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool {
6636 return Target.riscv.featureSetHas(func.target.cpu.features, feature);6634 return Target.riscv.featureSetHas(func.target.cpu.features, feature);
6637}6635}
66386636
6639pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {6637pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Zcu) u64 {
6640 if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;6638 if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;
6641 const payload_align = payload_ty.abiAlignment(zcu);6639 const payload_align = payload_ty.abiAlignment(zcu);
6642 const error_align = Type.anyerror.abiAlignment(zcu);6640 const error_align = Type.anyerror.abiAlignment(zcu);
...@@ -6647,7 +6645,7 @@ pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {...@@ -6647,7 +6645,7 @@ pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {
6647 }6645 }
6648}6646}
66496647
6650pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Module) u64 {6648pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Zcu) u64 {
6651 if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;6649 if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;
6652 const payload_align = payload_ty.abiAlignment(zcu);6650 const payload_align = payload_ty.abiAlignment(zcu);
6653 const error_align = Type.anyerror.abiAlignment(zcu);6651 const error_align = Type.anyerror.abiAlignment(zcu);
src/arch/riscv64/Lower.zig+2-4
...@@ -8,7 +8,7 @@ allocator: Allocator,...@@ -8,7 +8,7 @@ allocator: Allocator,
8mir: Mir,8mir: Mir,
9cc: std.builtin.CallingConvention,9cc: std.builtin.CallingConvention,
10err_msg: ?*ErrorMsg = null,10err_msg: ?*ErrorMsg = null,
11src_loc: Module.SrcLoc,11src_loc: Zcu.SrcLoc,
12result_insts_len: u8 = undefined,12result_insts_len: u8 = undefined,
13result_relocs_len: u8 = undefined,13result_relocs_len: u8 = undefined,
14result_insts: [14result_insts: [
...@@ -520,10 +520,8 @@ const log = std.log.scoped(.lower);...@@ -520,10 +520,8 @@ const log = std.log.scoped(.lower);
520520
521const Air = @import("../../Air.zig");521const Air = @import("../../Air.zig");
522const Allocator = std.mem.Allocator;522const Allocator = std.mem.Allocator;
523const ErrorMsg = Module.ErrorMsg;523const ErrorMsg = Zcu.ErrorMsg;
524const Mir = @import("Mir.zig");524const Mir = @import("Mir.zig");
525const Zcu = @import("../../Zcu.zig");525const Zcu = @import("../../Zcu.zig");
526/// Deprecated.
527const Module = Zcu;
528const Instruction = encoder.Instruction;526const Instruction = encoder.Instruction;
529const Immediate = bits.Immediate;527const Immediate = bits.Immediate;
src/arch/riscv64/abi.zig+3-5
...@@ -5,13 +5,11 @@ const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;...@@ -5,13 +5,11 @@ const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
5const Type = @import("../../type.zig").Type;5const Type = @import("../../type.zig").Type;
6const InternPool = @import("../../InternPool.zig");6const InternPool = @import("../../InternPool.zig");
7const Zcu = @import("../../Zcu.zig");7const Zcu = @import("../../Zcu.zig");
8/// Deprecated.
9const Module = Zcu;
10const assert = std.debug.assert;8const assert = std.debug.assert;
119
12pub const Class = enum { memory, byval, integer, double_integer, fields };10pub const Class = enum { memory, byval, integer, double_integer, fields };
1311
14pub fn classifyType(ty: Type, mod: *Module) Class {12pub fn classifyType(ty: Type, mod: *Zcu) Class {
15 const target = mod.getTarget();13 const target = mod.getTarget();
16 std.debug.assert(ty.hasRuntimeBitsIgnoreComptime(mod));14 std.debug.assert(ty.hasRuntimeBitsIgnoreComptime(mod));
1715
...@@ -99,7 +97,7 @@ pub const SystemClass = enum { integer, float, memory, none };...@@ -99,7 +97,7 @@ pub const SystemClass = enum { integer, float, memory, none };
9997
100/// There are a maximum of 8 possible return slots. Returned values are in98/// There are a maximum of 8 possible return slots. Returned values are in
101/// the beginning of the array; unused slots are filled with .none.99/// the beginning of the array; unused slots are filled with .none.
102pub fn classifySystem(ty: Type, zcu: *Module) [8]SystemClass {100pub fn classifySystem(ty: Type, zcu: *Zcu) [8]SystemClass {
103 var result = [1]SystemClass{.none} ** 8;101 var result = [1]SystemClass{.none} ** 8;
104 const memory_class = [_]SystemClass{102 const memory_class = [_]SystemClass{
105 .memory, .none, .none, .none,103 .memory, .none, .none, .none,
...@@ -202,7 +200,7 @@ fn classifyStruct(...@@ -202,7 +200,7 @@ fn classifyStruct(
202 result: *[8]Class,200 result: *[8]Class,
203 byte_offset: *u64,201 byte_offset: *u64,
204 loaded_struct: InternPool.LoadedStructType,202 loaded_struct: InternPool.LoadedStructType,
205 zcu: *Module,203 zcu: *Zcu,
206) void {204) void {
207 const ip = &zcu.intern_pool;205 const ip = &zcu.intern_pool;
208 var field_it = loaded_struct.iterateRuntimeOrder(ip);206 var field_it = loaded_struct.iterateRuntimeOrder(ip);
src/arch/riscv64/bits.zig+1-3
...@@ -5,8 +5,6 @@ const testing = std.testing;...@@ -5,8 +5,6 @@ const testing = std.testing;
5const Target = std.Target;5const Target = std.Target;
66
7const Zcu = @import("../../Zcu.zig");7const Zcu = @import("../../Zcu.zig");
8/// Deprecated.
9const Module = Zcu;
10const Encoding = @import("Encoding.zig");8const Encoding = @import("Encoding.zig");
11const Mir = @import("Mir.zig");9const Mir = @import("Mir.zig");
12const abi = @import("abi.zig");10const abi = @import("abi.zig");
...@@ -202,7 +200,7 @@ pub const Register = enum(u8) {...@@ -202,7 +200,7 @@ pub const Register = enum(u8) {
202 return @as(u8, reg.id());200 return @as(u8, reg.id());
203 }201 }
204202
205 pub fn bitSize(reg: Register, zcu: *const Module) u32 {203 pub fn bitSize(reg: Register, zcu: *const Zcu) u32 {
206 const features = zcu.getTarget().cpu.features;204 const features = zcu.getTarget().cpu.features;
207205
208 return switch (@intFromEnum(reg)) {206 return switch (@intFromEnum(reg)) {