| author |  David Rubin <david@vortan.dev> 2024-06-22 22:13:49-07:00 |
| committer |  Matthew Lugg <mlugg@mlugg.co.uk> 2024-06-23 15:26:14+01:00 |
| log | e73ae94b3640ef74c9614c2da6a0200ff444f3e8 |
| tree | 247f825ed81e6f85eb35ed69cdbaad076d53d0ec |
| parent | f3655fd07dbd30d3c7ed95d92df192a78b081a3a |
riscv: remove deprecated `Module` usages
4 files changed, 14 insertions(+), 22 deletions(-)
src- arch
src/arch/riscv64/CodeGen.zig+8-10
| ... | @@ -11,12 +11,10 @@ const Type = @import("../../type.zig").Type; | ... | @@ -11,12 +11,10 @@ const Type = @import("../../type.zig").Type; |
| 11 | const Value = @import("../../Value.zig"); | 11 | const Value = @import("../../Value.zig"); |
| 12 | const link = @import("../../link.zig"); | 12 | const link = @import("../../link.zig"); |
| 13 | const Zcu = @import("../../Zcu.zig"); | 13 | const Zcu = @import("../../Zcu.zig"); |
| 14 | /// Deprecated. | ||
| 15 | const Module = Zcu; | ||
| 16 | const Package = @import("../../Package.zig"); | 14 | const Package = @import("../../Package.zig"); |
| 17 | const InternPool = @import("../../InternPool.zig"); | 15 | const InternPool = @import("../../InternPool.zig"); |
| 18 | const Compilation = @import("../../Compilation.zig"); | 16 | const Compilation = @import("../../Compilation.zig"); |
| 19 | const ErrorMsg = Module.ErrorMsg; | 17 | const ErrorMsg = Zcu.ErrorMsg; |
| 20 | const Target = std.Target; | 18 | const Target = std.Target; |
| 21 | const Allocator = mem.Allocator; | 19 | const Allocator = mem.Allocator; |
| 22 | const trace = @import("../../tracy.zig").trace; | 20 | const trace = @import("../../tracy.zig").trace; |
| ... | @@ -61,7 +59,7 @@ args: []MCValue, | ... | @@ -61,7 +59,7 @@ args: []MCValue, |
| 61 | ret_mcv: InstTracking, | 59 | ret_mcv: InstTracking, |
| 62 | fn_type: Type, | 60 | fn_type: Type, |
| 63 | arg_index: usize, | 61 | arg_index: usize, |
| 64 | src_loc: Module.SrcLoc, | 62 | src_loc: Zcu.SrcLoc, |
| 65 | 63 | ||
| 66 | /// MIR Instructions | 64 | /// MIR Instructions |
| 67 | mir_instructions: std.MultiArrayList(Mir.Inst) = .{}, | 65 | mir_instructions: std.MultiArrayList(Mir.Inst) = .{}, |
| ... | @@ -543,13 +541,13 @@ const FrameAlloc = struct { | ... | @@ -543,13 +541,13 @@ const FrameAlloc = struct { |
| 543 | .ref_count = 0, | 541 | .ref_count = 0, |
| 544 | }; | 542 | }; |
| 545 | } | 543 | } |
| 546 | fn initType(ty: Type, zcu: *Module) FrameAlloc { | 544 | fn initType(ty: Type, zcu: *Zcu) FrameAlloc { |
| 547 | return init(.{ | 545 | return init(.{ |
| 548 | .size = ty.abiSize(zcu), | 546 | .size = ty.abiSize(zcu), |
| 549 | .alignment = ty.abiAlignment(zcu), | 547 | .alignment = ty.abiAlignment(zcu), |
| 550 | }); | 548 | }); |
| 551 | } | 549 | } |
| 552 | fn initSpill(ty: Type, zcu: *Module) FrameAlloc { | 550 | fn initSpill(ty: Type, zcu: *Zcu) FrameAlloc { |
| 553 | const abi_size = ty.abiSize(zcu); | 551 | const abi_size = ty.abiSize(zcu); |
| 554 | const spill_size = if (abi_size < 8) | 552 | const spill_size = if (abi_size < 8) |
| 555 | math.ceilPowerOfTwoAssert(u64, abi_size) | 553 | math.ceilPowerOfTwoAssert(u64, abi_size) |
| ... | @@ -698,7 +696,7 @@ const CallView = enum(u1) { | ... | @@ -698,7 +696,7 @@ const CallView = enum(u1) { |
| 698 | 696 | ||
| 699 | pub fn generate( | 697 | pub fn generate( |
| 700 | bin_file: *link.File, | 698 | bin_file: *link.File, |
| 701 | src_loc: Module.SrcLoc, | 699 | src_loc: Zcu.SrcLoc, |
| 702 | func_index: InternPool.Index, | 700 | func_index: InternPool.Index, |
| 703 | air: Air, | 701 | air: Air, |
| 704 | liveness: Liveness, | 702 | liveness: Liveness, |
| ... | @@ -922,7 +920,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir) | ... | @@ -922,7 +920,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir) |
| 922 | } | 920 | } |
| 923 | 921 | ||
| 924 | const FormatDeclData = struct { | 922 | const FormatDeclData = struct { |
| 925 | mod: *Module, | 923 | mod: *Zcu, |
| 926 | decl_index: InternPool.DeclIndex, | 924 | decl_index: InternPool.DeclIndex, |
| 927 | }; | 925 | }; |
| 928 | fn formatDecl( | 926 | fn formatDecl( |
| ... | @@ -6636,7 +6634,7 @@ fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool { | ... | @@ -6636,7 +6634,7 @@ fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool { |
| 6636 | return Target.riscv.featureSetHas(func.target.cpu.features, feature); | 6634 | return Target.riscv.featureSetHas(func.target.cpu.features, feature); |
| 6637 | } | 6635 | } |
| 6638 | 6636 | ||
| 6639 | pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 { | 6637 | pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Zcu) u64 { |
| 6640 | if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0; | 6638 | if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0; |
| 6641 | const payload_align = payload_ty.abiAlignment(zcu); | 6639 | const payload_align = payload_ty.abiAlignment(zcu); |
| 6642 | const error_align = Type.anyerror.abiAlignment(zcu); | 6640 | const error_align = Type.anyerror.abiAlignment(zcu); |
| ... | @@ -6647,7 +6645,7 @@ pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 { | ... | @@ -6647,7 +6645,7 @@ pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 { |
| 6647 | } | 6645 | } |
| 6648 | } | 6646 | } |
| 6649 | 6647 | ||
| 6650 | pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Module) u64 { | 6648 | pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Zcu) u64 { |
| 6651 | if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0; | 6649 | if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0; |
| 6652 | const payload_align = payload_ty.abiAlignment(zcu); | 6650 | const payload_align = payload_ty.abiAlignment(zcu); |
| 6653 | const error_align = Type.anyerror.abiAlignment(zcu); | 6651 | const error_align = Type.anyerror.abiAlignment(zcu); |
src/arch/riscv64/Lower.zig+2-4
| ... | @@ -8,7 +8,7 @@ allocator: Allocator, | ... | @@ -8,7 +8,7 @@ allocator: Allocator, |
| 8 | mir: Mir, | 8 | mir: Mir, |
| 9 | cc: std.builtin.CallingConvention, | 9 | cc: std.builtin.CallingConvention, |
| 10 | err_msg: ?*ErrorMsg = null, | 10 | err_msg: ?*ErrorMsg = null, |
| 11 | src_loc: Module.SrcLoc, | 11 | src_loc: Zcu.SrcLoc, |
| 12 | result_insts_len: u8 = undefined, | 12 | result_insts_len: u8 = undefined, |
| 13 | result_relocs_len: u8 = undefined, | 13 | result_relocs_len: u8 = undefined, |
| 14 | result_insts: [ | 14 | result_insts: [ |
| ... | @@ -520,10 +520,8 @@ const log = std.log.scoped(.lower); | ... | @@ -520,10 +520,8 @@ const log = std.log.scoped(.lower); |
| 520 | 520 | ||
| 521 | const Air = @import("../../Air.zig"); | 521 | const Air = @import("../../Air.zig"); |
| 522 | const Allocator = std.mem.Allocator; | 522 | const Allocator = std.mem.Allocator; |
| 523 | const ErrorMsg = Module.ErrorMsg; | 523 | const ErrorMsg = Zcu.ErrorMsg; |
| 524 | const Mir = @import("Mir.zig"); | 524 | const Mir = @import("Mir.zig"); |
| 525 | const Zcu = @import("../../Zcu.zig"); | 525 | const Zcu = @import("../../Zcu.zig"); |
| 526 | /// Deprecated. | ||
| 527 | const Module = Zcu; | ||
| 528 | const Instruction = encoder.Instruction; | 526 | const Instruction = encoder.Instruction; |
| 529 | const Immediate = bits.Immediate; | 527 | const Immediate = bits.Immediate; |
src/arch/riscv64/abi.zig+3-5
| ... | @@ -5,13 +5,11 @@ const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager; | ... | @@ -5,13 +5,11 @@ const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager; |
| 5 | const Type = @import("../../type.zig").Type; | 5 | const Type = @import("../../type.zig").Type; |
| 6 | const InternPool = @import("../../InternPool.zig"); | 6 | const InternPool = @import("../../InternPool.zig"); |
| 7 | const Zcu = @import("../../Zcu.zig"); | 7 | const Zcu = @import("../../Zcu.zig"); |
| 8 | /// Deprecated. | ||
| 9 | const Module = Zcu; | ||
| 10 | const assert = std.debug.assert; | 8 | const assert = std.debug.assert; |
| 11 | 9 | ||
| 12 | pub const Class = enum { memory, byval, integer, double_integer, fields }; | 10 | pub const Class = enum { memory, byval, integer, double_integer, fields }; |
| 13 | 11 | ||
| 14 | pub fn classifyType(ty: Type, mod: *Module) Class { | 12 | pub fn classifyType(ty: Type, mod: *Zcu) Class { |
| 15 | const target = mod.getTarget(); | 13 | const target = mod.getTarget(); |
| 16 | std.debug.assert(ty.hasRuntimeBitsIgnoreComptime(mod)); | 14 | std.debug.assert(ty.hasRuntimeBitsIgnoreComptime(mod)); |
| 17 | 15 | ||
| ... | @@ -99,7 +97,7 @@ pub const SystemClass = enum { integer, float, memory, none }; | ... | @@ -99,7 +97,7 @@ pub const SystemClass = enum { integer, float, memory, none }; |
| 99 | 97 | ||
| 100 | /// There are a maximum of 8 possible return slots. Returned values are in | 98 | /// There are a maximum of 8 possible return slots. Returned values are in |
| 101 | /// the beginning of the array; unused slots are filled with .none. | 99 | /// the beginning of the array; unused slots are filled with .none. |
| 102 | pub fn classifySystem(ty: Type, zcu: *Module) [8]SystemClass { | 100 | pub fn classifySystem(ty: Type, zcu: *Zcu) [8]SystemClass { |
| 103 | var result = [1]SystemClass{.none} ** 8; | 101 | var result = [1]SystemClass{.none} ** 8; |
| 104 | const memory_class = [_]SystemClass{ | 102 | const memory_class = [_]SystemClass{ |
| 105 | .memory, .none, .none, .none, | 103 | .memory, .none, .none, .none, |
| ... | @@ -202,7 +200,7 @@ fn classifyStruct( | ... | @@ -202,7 +200,7 @@ fn classifyStruct( |
| 202 | result: *[8]Class, | 200 | result: *[8]Class, |
| 203 | byte_offset: *u64, | 201 | byte_offset: *u64, |
| 204 | loaded_struct: InternPool.LoadedStructType, | 202 | loaded_struct: InternPool.LoadedStructType, |
| 205 | zcu: *Module, | 203 | zcu: *Zcu, |
| 206 | ) void { | 204 | ) void { |
| 207 | const ip = &zcu.intern_pool; | 205 | const ip = &zcu.intern_pool; |
| 208 | var field_it = loaded_struct.iterateRuntimeOrder(ip); | 206 | var field_it = loaded_struct.iterateRuntimeOrder(ip); |
src/arch/riscv64/bits.zig+1-3
| ... | @@ -5,8 +5,6 @@ const testing = std.testing; | ... | @@ -5,8 +5,6 @@ const testing = std.testing; |
| 5 | const Target = std.Target; | 5 | const Target = std.Target; |
| 6 | 6 | ||
| 7 | const Zcu = @import("../../Zcu.zig"); | 7 | const Zcu = @import("../../Zcu.zig"); |
| 8 | /// Deprecated. | ||
| 9 | const Module = Zcu; | ||
| 10 | const Encoding = @import("Encoding.zig"); | 8 | const Encoding = @import("Encoding.zig"); |
| 11 | const Mir = @import("Mir.zig"); | 9 | const Mir = @import("Mir.zig"); |
| 12 | const abi = @import("abi.zig"); | 10 | const abi = @import("abi.zig"); |
| ... | @@ -202,7 +200,7 @@ pub const Register = enum(u8) { | ... | @@ -202,7 +200,7 @@ pub const Register = enum(u8) { |
| 202 | return @as(u8, reg.id()); | 200 | return @as(u8, reg.id()); |
| 203 | } | 201 | } |
| 204 | 202 | ||
| 205 | pub fn bitSize(reg: Register, zcu: *const Module) u32 { | 203 | pub fn bitSize(reg: Register, zcu: *const Zcu) u32 { |
| 206 | const features = zcu.getTarget().cpu.features; | 204 | const features = zcu.getTarget().cpu.features; |
| 207 | 205 | ||
| 208 | return switch (@intFromEnum(reg)) { | 206 | return switch (@intFromEnum(reg)) { |