authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2020-12-09 08:07:47+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2020-12-09 17:21:17+01:00
loge91dbab256354477fdac0849f43766f43a7df8f0
treeb1fdea092b35e2f62d07e83e7261bb995469e30e
parenteca0727417833b6c60cb2b30ba492ef816f4a4bc

stage2+aarch64: fix stage2 tests

2 files changed, 25 insertions(+), 25 deletions(-)

src/codegen.zig+4-4
......@@ -2768,8 +2768,8 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
27682768 .x0,
27692769 .x28,
27702770 Register.sp,
2771 -2,
2772 .SignedOffset,
2771 -16,
2772 .PreIndex,
27732773 ).toU32());
27742774 // adr x28, #8
27752775 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.adr(.x28, 8).toU32());
......@@ -2795,8 +2795,8 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
27952795 .x0,
27962796 .x28,
27972797 Register.sp,
2798 2,
2799 .SignedOffset,
2798 16,
2799 .PostIndex,
28002800 ).toU32());
28012801 }
28022802 } else {
src/codegen/aarch64.zig+21-21
......@@ -560,19 +560,20 @@ pub const Instruction = union(enum) {
560560 rt1: Register,
561561 rt2: Register,
562562 rn: Register,
563 imm7: i7,
563 offset: i9,
564564 encoding: u2,
565565 load: bool,
566566 ) Instruction {
567 const imm7_u: u7 = @bitCast(u7, imm7);
568567 switch (rt1.size()) {
569568 32 => {
569 assert(-256 <= offset and offset <= 252);
570 const imm7 = @truncate(u7, @bitCast(u9, offset >> 2));
570571 return Instruction{
571572 .LoadStorePairOfRegisters = .{
572573 .rt1 = rt1.id(),
573574 .rn = rn.id(),
574575 .rt2 = rt2.id(),
575 .imm7 = imm7_u,
576 .imm7 = imm7,
576577 .load = @boolToInt(load),
577578 .encoding = encoding,
578579 .opc = 0b00,
......@@ -580,12 +581,14 @@ pub const Instruction = union(enum) {
580581 };
581582 },
582583 64 => {
584 assert(-512 <= offset and offset <= 504);
585 const imm7 = @truncate(u7, @bitCast(u9, offset >> 3));
583586 return Instruction{
584587 .LoadStorePairOfRegisters = .{
585588 .rt1 = rt1.id(),
586589 .rn = rn.id(),
587590 .rt2 = rt2.id(),
588 .imm7 = imm7_u,
591 .imm7 = imm7,
589592 .load = @boolToInt(load),
590593 .encoding = encoding,
591594 .opc = 0b10,
......@@ -731,20 +734,20 @@ pub const Instruction = union(enum) {
731734 SignedOffset = 0b10,
732735 PreIndex = 0b11,
733736 };
734 pub fn ldp(rt1: Register, rt2: Register, rn: Register, imm: i7, encoding: LoadStorePairEncoding) Instruction {
735 return loadStorePairOfRegisters(rt1, rt2, rn, imm, @enumToInt(encoding), true);
737 pub fn ldp(rt1: Register, rt2: Register, rn: Register, offset: i9, encoding: LoadStorePairEncoding) Instruction {
738 return loadStorePairOfRegisters(rt1, rt2, rn, offset, @enumToInt(encoding), true);
736739 }
737740
738 pub fn ldnp(rt1: Register, rt2: Register, rn: Register, imm: i7) Instruction {
739 return loadStorePairOfRegisters(rt1, rt2, rn, imm, 0, true);
741 pub fn ldnp(rt1: Register, rt2: Register, rn: Register, offset: i9) Instruction {
742 return loadStorePairOfRegisters(rt1, rt2, rn, offset, 0, true);
740743 }
741744
742 pub fn stp(rt1: Register, rt2: Register, rn: Register, imm: i7, encoding: LoadStorePairEncoding) Instruction {
743 return loadStorePairOfRegisters(rt1, rt2, rn, imm, @enumToInt(encoding), false);
745 pub fn stp(rt1: Register, rt2: Register, rn: Register, offset: i9, encoding: LoadStorePairEncoding) Instruction {
746 return loadStorePairOfRegisters(rt1, rt2, rn, offset, @enumToInt(encoding), false);
744747 }
745748
746 pub fn stnp(rt1: Register, rt2: Register, rn: Register, imm: i7) Instruction {
747 return loadStorePairOfRegisters(rt1, rt2, rn, imm, 0, false);
749 pub fn stnp(rt1: Register, rt2: Register, rn: Register, offset: i9) Instruction {
750 return loadStorePairOfRegisters(rt1, rt2, rn, offset, 0, false);
748751 }
749752
750753 // Exception generation
......@@ -903,29 +906,26 @@ test "serialize instructions" {
903906 .inst = Instruction.adrp(.x2, -0x8),
904907 .expected = 0b1_00_10000_1111111111111111110_00010,
905908 },
906 .{ // stp x1, x2, [sp, #1]
907 .inst = Instruction.stp(.x1, .x2, Register.sp, 1, .SignedOffset),
909 .{ // stp x1, x2, [sp, #8]
910 .inst = Instruction.stp(.x1, .x2, Register.sp, 8, .SignedOffset),
908911 .expected = 0b10_101_0_010_0_0000001_00010_11111_00001,
909912 },
910913 .{ // stp x1, x2, [sp, #-16]
911914 .inst = Instruction.stp(.x1, .x2, Register.sp, -16, .SignedOffset),
912 .expected = 0b10_101_0_010_0_1110000_00010_11111_00001,
915 .expected = 0b10_101_0_010_0_1111110_00010_11111_00001,
913916 },
914 .{ // ldp x1, x2, [sp, #1]
915 .inst = Instruction.ldp(.x1, .x2, Register.sp, 1, .SignedOffset),
917 .{ // ldp x1, x2, [sp, #8]
918 .inst = Instruction.ldp(.x1, .x2, Register.sp, 8, .SignedOffset),
916919 .expected = 0b10_101_0_010_1_0000001_00010_11111_00001,
917920 },
918921 .{ // ldp x1, x2, [sp, #16]
919922 .inst = Instruction.ldp(.x1, .x2, Register.sp, 16, .SignedOffset),
920 .expected = 0b10_101_0_010_1_0010000_00010_11111_00001,
923 .expected = 0b10_101_0_010_1_0000010_00010_11111_00001,
921924 },
922925 };
923926
924927 for (testcases) |case| {
925928 const actual = case.inst.toU32();
926 if (case.expected != actual) {
927 std.debug.print("0b{b} != 0b{b}\n", .{ case.expected, actual });
928 }
929929 testing.expectEqual(case.expected, actual);
930930 }
931931}