| ... | ... | @@ -1460,6 +1460,15 @@ fn asmMemoryRegister(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, reg: Regist |
| 1460 | 1460 | } |
| 1461 | 1461 | |
| 1462 | 1462 | fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immediate) !void { |
| 1463 | const payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) { |
| 1464 | .signed => |s| @bitCast(u32, s), |
| 1465 | .unsigned => |u| @intCast(u32, u), |
| 1466 | } }); |
| 1467 | assert(payload + 1 == switch (m) { |
| 1468 | .sib => try self.addExtra(Mir.MemorySib.encode(m)), |
| 1469 | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), |
| 1470 | else => unreachable, |
| 1471 | }); |
| 1463 | 1472 | _ = try self.addInst(.{ |
| 1464 | 1473 | .tag = tag[1], |
| 1465 | 1474 | .ops = switch (m) { |
| ... | ... | @@ -1475,17 +1484,9 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immed |
| 1475 | 1484 | }, |
| 1476 | 1485 | .data = .{ .x = .{ |
| 1477 | 1486 | .fixes = tag[0], |
| 1478 | | .payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) { |
| 1479 | | .signed => |s| @bitCast(u32, s), |
| 1480 | | .unsigned => |u| @intCast(u32, u), |
| 1481 | | } }), |
| 1487 | .payload = payload, |
| 1482 | 1488 | } }, |
| 1483 | 1489 | }); |
| 1484 | | _ = switch (m) { |
| 1485 | | .sib => try self.addExtra(Mir.MemorySib.encode(m)), |
| 1486 | | .rip => try self.addExtra(Mir.MemoryRip.encode(m)), |
| 1487 | | else => unreachable, |
| 1488 | | }; |
| 1489 | 1490 | } |
| 1490 | 1491 | |
| 1491 | 1492 | fn asmMemoryRegisterRegister( |
Jacob Young <jacobly@ziglang.org> 2023-05-08 18:34:45-04:00
src