| author | |
| committer | |
| log | ea3cc777ccccf3113d7724898c35473343f71080 |
| tree | ded18b131d8e1c1cbcb1958a0d067aa60f8b336b |
| parent | e3352db9860ab14f7f5fc8a41f97305c049ab0fe |
3 files changed, 38 insertions(+), 17 deletions(-)
src-self-hosted/codegen.zig+2-5| ... | @@ -588,7 +588,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { | ... | @@ -588,7 +588,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 588 | entry.value = .dead; | 588 | entry.value = .dead; |
| 589 | switch (prev_value) { | 589 | switch (prev_value) { |
| 590 | .register => |reg| { | 590 | .register => |reg| { |
| 591 | const reg64 = reg.to64(); | 591 | const reg64 = if (arch == .x86_64) reg.to64() else reg; |
| 592 | _ = branch.registers.remove(reg64); | 592 | _ = branch.registers.remove(reg64); |
| 593 | branch.markRegFree(reg64); | 593 | branch.markRegFree(reg64); |
| 594 | }, | 594 | }, |
| ... | @@ -1585,10 +1585,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { | ... | @@ -1585,10 +1585,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 1585 | if (!self.wantSafety()) | 1585 | if (!self.wantSafety()) |
| 1586 | return; // The already existing value will do just fine. | 1586 | return; // The already existing value will do just fine. |
| 1587 | // Write the debug undefined value. | 1587 | // Write the debug undefined value. |
| 1588 | switch (reg.size()) { | 1588 | return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaaaaaaaaaa }); |
| 1589 | 64 => return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaaaaaaaaaa }), | ||
| 1590 | else => unreachable, | ||
| 1591 | } | ||
| 1592 | }, | 1589 | }, |
| 1593 | .immediate => |unsigned_x| { | 1590 | .immediate => |unsigned_x| { |
| 1594 | const x = @bitCast(i64, unsigned_x); | 1591 | const x = @bitCast(i64, unsigned_x); |
src-self-hosted/codegen/riscv64.zig-12| ... | @@ -71,18 +71,6 @@ pub const Register = enum(u8) { | ... | @@ -71,18 +71,6 @@ pub const Register = enum(u8) { |
| 71 | return null; | 71 | return null; |
| 72 | } | 72 | } |
| 73 | 73 | ||
| 74 | /// Returns the bit-width of the register. | ||
| 75 | pub fn size(self: @This()) u7 { | ||
| 76 | return switch (@enumToInt(self)) { | ||
| 77 | 0...31 => 64, | ||
| 78 | else => unreachable, | ||
| 79 | }; | ||
| 80 | } | ||
| 81 | |||
| 82 | pub fn to64(self: @This()) Register { | ||
| 83 | return self; | ||
| 84 | } | ||
| 85 | |||
| 86 | /// Returns the register's id. | 74 | /// Returns the register's id. |
| 87 | pub fn id(self: @This()) u5 { | 75 | pub fn id(self: @This()) u5 { |
| 88 | return @truncate(u5, @enumToInt(self)); | 76 | return @truncate(u5, @enumToInt(self)); |
test/stage2/compare_output.zig+36| ... | @@ -403,4 +403,40 @@ pub fn addCases(ctx: *TestContext) !void { | ... | @@ -403,4 +403,40 @@ pub fn addCases(ctx: *TestContext) !void { |
| 403 | "", | 403 | "", |
| 404 | ); | 404 | ); |
| 405 | } | 405 | } |
| 406 | |||
| 407 | { | ||
| 408 | var case = ctx.exe("hello world with updates", riscv64); | ||
| 409 | // Regular old hello world | ||
| 410 | case.addCompareOutput( | ||
| 411 | \\export fn _start() noreturn { | ||
| 412 | \\ print(); | ||
| 413 | \\ | ||
| 414 | \\ exit(); | ||
| 415 | \\} | ||
| 416 | \\ | ||
| 417 | \\fn print() void { | ||
| 418 | \\ asm volatile ("ecall" | ||
| 419 | \\ : | ||
| 420 | \\ : [number] "{a7}" (64), | ||
| 421 | \\ [arg1] "{a0}" (1), | ||
| 422 | \\ [arg2] "{a1}" (@ptrToInt("Hello, World!\n")), | ||
| 423 | \\ [arg3] "{a2}" ("Hello, World!\n".len) | ||
| 424 | \\ : "rcx", "r11", "memory" | ||
| 425 | \\ ); | ||
| 426 | \\ return; | ||
| 427 | \\} | ||
| 428 | \\ | ||
| 429 | \\fn exit() noreturn { | ||
| 430 | \\ asm volatile ("ecall" | ||
| 431 | \\ : | ||
| 432 | \\ : [number] "{a7}" (94), | ||
| 433 | \\ [arg1] "{a0}" (0) | ||
| 434 | \\ : "rcx", "r11", "memory" | ||
| 435 | \\ ); | ||
| 436 | \\ unreachable; | ||
| 437 | \\} | ||
| 438 | , | ||
| 439 | "Hello, World!\n", | ||
| 440 | ); | ||
| 441 | } | ||
| 406 | } | 442 | } |