authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-16 15:56:32+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-18 00:36:52+02:00
logeb36a45ed9fbdf5ab92c3cdb650375a13eaaa648
tree79019b131472eb6c157755f5b603a53a0a1ce7d9
parentde3947608ceb6e4603e3d249fb07183e3a431536
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.debug: add CPU context and DWARF mappings for or1k

3 files changed, 66 insertions(+), 1 deletions(-)

lib/std/debug/Dwarf.zig+3
...@@ -1436,6 +1436,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {...@@ -1436,6 +1436,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1436 .lanai => 2,1436 .lanai => 2,
1437 .loongarch32, .loongarch64 => 64,1437 .loongarch32, .loongarch64 => 64,
1438 .mips, .mipsel, .mips64, .mips64el => 66,1438 .mips, .mipsel, .mips64, .mips64el => 66,
1439 .or1k => 35,
1439 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,1440 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
1440 .riscv32, .riscv32be, .riscv64, .riscv64be => 65,1441 .riscv32, .riscv32be, .riscv64, .riscv64be => 65,
1441 .s390x => 65,1442 .s390x => 65,
...@@ -1456,6 +1457,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1456,6 +1457,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
1456 .lanai => 5,1457 .lanai => 5,
1457 .loongarch32, .loongarch64 => 22,1458 .loongarch32, .loongarch64 => 22,
1458 .mips, .mipsel, .mips64, .mips64el => 30,1459 .mips, .mipsel, .mips64, .mips64el => 30,
1460 .or1k => 2,
1459 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,1461 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
1460 .riscv32, .riscv32be, .riscv64, .riscv64be => 8,1462 .riscv32, .riscv32be, .riscv64, .riscv64be => 8,
1461 .s390x => 11,1463 .s390x => 11,
...@@ -1476,6 +1478,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {...@@ -1476,6 +1478,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
1476 .lanai => 4,1478 .lanai => 4,
1477 .loongarch32, .loongarch64 => 3,1479 .loongarch32, .loongarch64 => 3,
1478 .mips, .mipsel, .mips64, .mips64el => 29,1480 .mips, .mipsel, .mips64, .mips64el => 29,
1481 .or1k => 1,
1479 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,1482 .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
1480 .riscv32, .riscv32be, .riscv64, .riscv64be => 2,1483 .riscv32, .riscv32be, .riscv64, .riscv64be => 2,
1481 .s390x => 15,1484 .s390x => 15,
lib/std/debug/SelfInfo/Elf.zig+2-1
...@@ -101,7 +101,7 @@ pub const can_unwind: bool = s: {...@@ -101,7 +101,7 @@ pub const can_unwind: bool = s: {
101 .x86,101 .x86,
102 .x86_64,102 .x86_64,
103 },103 },
104 // Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, or1k, xtensa104 // Not supported yet: arc, arm/armeb/thumb/thumbeb, m68k, xtensa
105 .linux => &.{105 .linux => &.{
106 .aarch64,106 .aarch64,
107 .aarch64_be,107 .aarch64_be,
...@@ -111,6 +111,7 @@ pub const can_unwind: bool = s: {...@@ -111,6 +111,7 @@ pub const can_unwind: bool = s: {
111 .mipsel,111 .mipsel,
112 .mips64,112 .mips64,
113 .mips64el,113 .mips64el,
114 .or1k,
114 .riscv32,115 .riscv32,
115 .riscv64,116 .riscv64,
116 .s390x,117 .s390x,
lib/std/debug/cpu_context.zig+61
...@@ -11,6 +11,7 @@ else switch (native_arch) {...@@ -11,6 +11,7 @@ else switch (native_arch) {
11 .lanai => Lanai,11 .lanai => Lanai,
12 .loongarch32, .loongarch64 => LoongArch,12 .loongarch32, .loongarch64 => LoongArch,
13 .mips, .mipsel, .mips64, .mips64el => Mips,13 .mips, .mipsel, .mips64, .mips64el => Mips,
14 .or1k => Or1k,
14 .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,15 .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
15 .sparc, .sparc64 => Sparc,16 .sparc, .sparc64 => Sparc,
16 .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,17 .riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,
...@@ -818,6 +819,66 @@ const Mips = extern struct {...@@ -818,6 +819,66 @@ const Mips = extern struct {
818 }819 }
819};820};
820821
822/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
823const Or1k = extern struct {
824 /// The numbered general-purpose registers r0 - r31.
825 r: [32]u32,
826 pc: u32,
827
828 pub inline fn current() Or1k {
829 var ctx: Or1k = undefined;
830 asm volatile (
831 \\ l.sw 0(r15), r0
832 \\ l.sw 4(r15), r1
833 \\ l.sw 8(r15), r2
834 \\ l.sw 12(r15), r3
835 \\ l.sw 16(r15), r4
836 \\ l.sw 20(r15), r5
837 \\ l.sw 24(r15), r6
838 \\ l.sw 28(r15), r7
839 \\ l.sw 32(r15), r8
840 \\ l.sw 36(r15), r9
841 \\ l.sw 40(r15), r10
842 \\ l.sw 44(r15), r11
843 \\ l.sw 48(r15), r12
844 \\ l.sw 52(r15), r13
845 \\ l.sw 56(r15), r14
846 \\ l.sw 60(r15), r15
847 \\ l.sw 64(r15), r16
848 \\ l.sw 68(r15), r17
849 \\ l.sw 72(r15), r18
850 \\ l.sw 76(r15), r19
851 \\ l.sw 80(r15), r20
852 \\ l.sw 84(r15), r21
853 \\ l.sw 88(r15), r22
854 \\ l.sw 92(r15), r23
855 \\ l.sw 96(r15), r24
856 \\ l.sw 100(r15), r25
857 \\ l.sw 104(r15), r26
858 \\ l.sw 108(r15), r27
859 \\ l.sw 112(r15), r28
860 \\ l.sw 116(r15), r29
861 \\ l.sw 120(r15), r30
862 \\ l.sw 124(r15), r31
863 \\ l.jal 1f
864 \\1:
865 \\ l.sw 128(r15), r9
866 :
867 : [ctx] "{r15}" (&ctx),
868 : .{ .r9 = true, .memory = true });
869 return ctx;
870 }
871
872 pub fn dwarfRegisterBytes(ctx: *Or1k, register_num: u16) DwarfRegisterError![]u8 {
873 switch (register_num) {
874 0...31 => return @ptrCast(&ctx.r[register_num]),
875 35 => return @ptrCast(&ctx.pc),
876
877 else => return error.InvalidRegister,
878 }
879 }
880};
881
821/// This is an `extern struct` so that inline assembly in `current` can use field offsets.882/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
822const Powerpc = extern struct {883const Powerpc = extern struct {
823 /// The numbered general-purpose registers r0 - r31.884 /// The numbered general-purpose registers r0 - r31.