authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-04-11 22:17:04+02:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-04-13 11:47:51+02:00
logee6b4fad4714d596255f034c0b000438ee6ca943
tree71539c5df0db2d9370a1b028f615feb4c72746df
parent382de7bf1de8314e97eb67426b693b966f2c4e1b

x86_64: remove loadMemPtrIntoRegister in genSetReg

Add two emit helpers for linker reloc based `lea` and `mov` instructions: `asmMovLinker` and `asmLeaLinker`.

4 files changed, 90 insertions(+), 20 deletions(-)

src/arch/x86_64/CodeGen.zig+77-19
......@@ -731,6 +731,40 @@ fn asmMemoryRegisterImmediate(
731731 });
732732}
733733
734fn asmMovLinker(self: *Self, reg: Register, atom_index: u32, linker_load: codegen.LinkerLoad) !void {
735 const ops: Mir.Inst.Ops = switch (linker_load.type) {
736 .got => .got_reloc,
737 .direct => .direct_reloc,
738 .import => .import_reloc,
739 };
740 _ = try self.addInst(.{
741 .tag = .mov_linker,
742 .ops = ops,
743 .data = .{ .payload = try self.addExtra(Mir.LeaRegisterReloc{
744 .reg = @enumToInt(reg),
745 .atom_index = atom_index,
746 .sym_index = linker_load.sym_index,
747 }) },
748 });
749}
750
751fn asmLeaLinker(self: *Self, reg: Register, atom_index: u32, linker_load: codegen.LinkerLoad) !void {
752 const ops: Mir.Inst.Ops = switch (linker_load.type) {
753 .got => .got_reloc,
754 .direct => .direct_reloc,
755 .import => .import_reloc,
756 };
757 _ = try self.addInst(.{
758 .tag = .lea_linker,
759 .ops = ops,
760 .data = .{ .payload = try self.addExtra(Mir.LeaRegisterReloc{
761 .reg = @enumToInt(reg),
762 .atom_index = atom_index,
763 .sym_index = linker_load.sym_index,
764 }) },
765 });
766}
767
734768fn gen(self: *Self) InnerError!void {
735769 const cc = self.fn_type.fnCallingConvention();
736770 if (cc != .Naked) {
......@@ -7454,10 +7488,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
74547488
74557489 try self.asmRegisterRegister(.mov, registerAlias(reg, abi_size), registerAlias(src_reg, abi_size));
74567490 },
7457 .memory, .linker_load => switch (ty.zigTypeTag()) {
7491 .memory => |addr| switch (ty.zigTypeTag()) {
74587492 .Float => {
7459 const base_reg = try self.register_manager.allocReg(null, gp);
7460 try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
7493 const base_reg = (try self.register_manager.allocReg(null, gp)).to64();
7494 try self.genSetReg(Type.usize, base_reg, .{ .immediate = addr });
74617495
74627496 if (intrinsicsAllowed(self.target.*, ty)) {
74637497 return self.asmRegisterMemory(
......@@ -7469,29 +7503,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
74697503 }),
74707504 },
74717505 reg.to128(),
7472 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base_reg.to64() }),
7506 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base_reg }),
74737507 );
74747508 }
74757509
74767510 return self.fail("TODO genSetReg from memory for float with no intrinsics", .{});
74777511 },
7478 else => switch (mcv) {
7479 else => unreachable,
7480 .linker_load => {
7481 try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
7482 try self.asmRegisterMemory(
7483 .mov,
7484 registerAlias(reg, abi_size),
7485 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = reg.to64() }),
7486 );
7487 },
7488 .memory => |x| if (x <= math.maxInt(i32)) {
7512 else => {
7513 if (addr <= math.maxInt(i32)) {
74897514 try self.asmRegisterMemory(
74907515 .mov,
74917516 registerAlias(reg, abi_size),
74927517 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
74937518 .base = .ds,
7494 .disp = @intCast(i32, x),
7519 .disp = @intCast(i32, addr),
74957520 }),
74967521 );
74977522 } else {
......@@ -7501,20 +7526,53 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
75017526 _ = try self.addInst(.{
75027527 .tag = .mov_moffs,
75037528 .ops = .rax_moffs,
7504 .data = .{ .payload = try self.addExtra(Mir.MemoryMoffs.encode(.ds, x)) },
7529 .data = .{ .payload = try self.addExtra(Mir.MemoryMoffs.encode(.ds, addr)) },
75057530 });
75067531 } else {
75077532 // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue.
7508 try self.genSetReg(ty, reg, MCValue{ .immediate = x });
7533 try self.genSetReg(Type.usize, reg, MCValue{ .immediate = addr });
75097534 try self.asmRegisterMemory(
75107535 .mov,
75117536 registerAlias(reg, abi_size),
75127537 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = reg.to64() }),
75137538 );
75147539 }
7515 },
7540 }
75167541 },
75177542 },
7543 .linker_load => |load_struct| {
7544 const atom_index = if (self.bin_file.cast(link.File.MachO)) |macho_file| blk: {
7545 const atom = try macho_file.getOrCreateAtomForDecl(self.mod_fn.owner_decl);
7546 break :blk macho_file.getAtom(atom).getSymbolIndex().?;
7547 } else if (self.bin_file.cast(link.File.Coff)) |coff_file| blk: {
7548 const atom = try coff_file.getOrCreateAtomForDecl(self.mod_fn.owner_decl);
7549 break :blk coff_file.getAtom(atom).getSymbolIndex().?;
7550 } else unreachable;
7551
7552 switch (ty.zigTypeTag()) {
7553 .Float => {
7554 const base_reg = (try self.register_manager.allocReg(null, gp)).to64();
7555 try self.asmLeaLinker(base_reg, atom_index, load_struct);
7556
7557 if (intrinsicsAllowed(self.target.*, ty)) {
7558 return self.asmRegisterMemory(
7559 switch (ty.tag()) {
7560 .f32 => .movss,
7561 .f64 => .movsd,
7562 else => return self.fail("TODO genSetReg from memory for {}", .{
7563 ty.fmt(self.bin_file.options.module.?),
7564 }),
7565 },
7566 reg.to128(),
7567 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base_reg.to64() }),
7568 );
7569 }
7570
7571 return self.fail("TODO genSetReg from memory for float with no intrinsics", .{});
7572 },
7573 else => try self.asmMovLinker(registerAlias(reg, abi_size), atom_index, load_struct),
7574 }
7575 },
75187576 .stack_offset => |off| {
75197577 switch (ty.zigTypeTag()) {
75207578 .Int => switch (ty.intInfo(self.target.*).signedness) {
src/arch/x86_64/Emit.zig+1-1
......@@ -65,7 +65,7 @@ pub fn emitMir(emit: *Emit) Error!void {
6565 });
6666 } else return emit.fail("TODO implement {} for {}", .{ inst.tag, emit.bin_file.tag }),
6767
68 .lea_linker => if (emit.bin_file.cast(link.File.MachO)) |macho_file| {
68 .mov_linker, .lea_linker => if (emit.bin_file.cast(link.File.MachO)) |macho_file| {
6969 const metadata =
7070 emit.lower.mir.extraData(Mir.LeaRegisterReloc, inst.data.payload).data;
7171 const reloc_type = switch (inst.ops) {
src/arch/x86_64/Lower.zig+10
......@@ -127,6 +127,7 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
127127 .call_extern => try lower.emit(.none, .call, &.{.{ .imm = Immediate.s(0) }}),
128128
129129 .lea_linker => try lower.mirLeaLinker(inst),
130 .mov_linker => try lower.mirMovLinker(inst),
130131
131132 .mov_moffs => try lower.mirMovMoffs(inst),
132133
......@@ -444,6 +445,15 @@ fn mirLeaLinker(lower: *Lower, inst: Mir.Inst) Error!void {
444445 });
445446}
446447
448fn mirMovLinker(lower: *Lower, inst: Mir.Inst) Error!void {
449 const metadata = lower.mir.extraData(Mir.LeaRegisterReloc, inst.data.payload).data;
450 const reg = @intToEnum(Register, metadata.reg);
451 try lower.emit(.none, .mov, &.{
452 .{ .reg = reg },
453 .{ .mem = Memory.rip(Memory.PtrSize.fromBitSize(reg.bitSize()), 0) },
454 });
455}
456
447457const abi = @import("abi.zig");
448458const assert = std.debug.assert;
449459const bits = @import("bits.zig");
src/arch/x86_64/Mir.zig+2
......@@ -233,6 +233,8 @@ pub const Inst = struct {
233233
234234 /// Load effective address of a symbol not yet allocated in VM.
235235 lea_linker,
236 /// Move address of a symbol not yet allocated in VM.
237 mov_linker,
236238
237239 /// End of prologue
238240 dbg_prologue_end,