authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-29 10:39:25+02:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-30 00:37:42+02:00
logee6e3aef5deb4aedd8f65e0ba7c44b4979ed6a96
tree301c48fa283706ba9cd402891e84d12c8a12401a
parentf9773ab622d84527ddfdb08d07443ec05cf28737

x64: redo @mulWithOverflow using rax/rdx based multiplication

2 files changed, 54 insertions(+), 30 deletions(-)

src/arch/x86_64/CodeGen.zig+51-25
......@@ -1254,7 +1254,7 @@ fn genPtrBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_r
12541254 offset_mcv.freezeIfRegister(&self.register_manager);
12551255 defer offset_mcv.unfreezeIfRegister(&self.register_manager);
12561256
1257 try self.genIMulOpMir(offset_ty, offset_mcv, .{ .immediate = elem_size });
1257 try self.genIntMulComplexOpMir(offset_ty, offset_mcv, .{ .immediate = elem_size });
12581258
12591259 const tag = self.air.instructions.items(.tag)[inst];
12601260 switch (tag) {
......@@ -1396,10 +1396,27 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
13961396
13971397fn airMul(self: *Self, inst: Air.Inst.Index) !void {
13981398 const bin_op = self.air.instructions.items(.data)[inst].bin_op;
1399 const result: MCValue = if (self.liveness.isUnused(inst))
1400 .dead
1401 else
1402 try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
1399 const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
1400 const ty = self.air.typeOfIndex(inst);
1401
1402 if (ty.zigTypeTag() != .Int) {
1403 return self.fail("TODO implement 'mul' for operands of dst type {}", .{ty.zigTypeTag()});
1404 }
1405
1406 // Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
1407 try self.register_manager.getReg(.rax, null);
1408 try self.register_manager.getReg(.rdx, null);
1409
1410 const lhs = try self.resolveInst(bin_op.lhs);
1411 const rhs = try self.resolveInst(bin_op.rhs);
1412
1413 const signedness = ty.intInfo(self.target.*).signedness;
1414 try self.genIntMulDivOpMir(switch (signedness) {
1415 .signed => .imul,
1416 .unsigned => .mul,
1417 }, ty, signedness, lhs, rhs);
1418 break :result MCValue{ .register = .rax };
1419 };
14031420 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
14041421}
14051422
......@@ -1474,23 +1491,31 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
14741491fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
14751492 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
14761493 const bin_op = self.air.extraData(Air.Bin, ty_pl.payload).data;
1494 const result = if (self.liveness.isUnused(inst)) .dead else result: {
1495 const ty = self.air.typeOf(bin_op.lhs);
1496 const signedness: std.builtin.Signedness = blk: {
1497 if (ty.zigTypeTag() != .Int) {
1498 return self.fail("TODO implement airMulWithOverflow for type {}", .{ty.fmtDebug()});
1499 }
1500 break :blk ty.intInfo(self.target.*).signedness;
1501 };
14771502
1478 if (self.liveness.isUnused(inst)) {
1479 return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
1480 }
1503 // Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
1504 try self.register_manager.getReg(.rax, null);
1505 try self.register_manager.getReg(.rdx, null);
14811506
1482 const ty = self.air.typeOf(bin_op.lhs);
1483 const signedness: std.builtin.Signedness = blk: {
1484 if (ty.zigTypeTag() != .Int) {
1485 return self.fail("TODO implement airMulWithOverflow for type {}", .{ty.fmtDebug()});
1486 }
1487 break :blk ty.intInfo(self.target.*).signedness;
1488 };
1507 const lhs = try self.resolveInst(bin_op.lhs);
1508 const rhs = try self.resolveInst(bin_op.rhs);
14891509
1490 const partial = try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
1491 const result: MCValue = switch (signedness) {
1492 .signed => .{ .register_overflow_signed = partial.register },
1493 .unsigned => .{ .register_overflow_unsigned = partial.register },
1510 try self.genIntMulDivOpMir(switch (signedness) {
1511 .signed => .imul,
1512 .unsigned => .mul,
1513 }, ty, signedness, lhs, rhs);
1514
1515 switch (signedness) {
1516 .signed => break :result MCValue{ .register_overflow_signed = .rax },
1517 .unsigned => break :result MCValue{ .register_overflow_unsigned = .rax },
1518 }
14941519 };
14951520
14961521 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
......@@ -1730,7 +1755,7 @@ fn airMod(self: *Self, inst: Air.Inst.Index) !void {
17301755 },
17311756 .signed => {
17321757 const div_floor = try self.genInlineIntDivFloor(ty, lhs, rhs);
1733 try self.genIMulOpMir(ty, div_floor, rhs);
1758 try self.genIntMulComplexOpMir(ty, div_floor, rhs);
17341759
17351760 const reg = try self.copyToTmpRegister(ty, lhs);
17361761 try self.genBinMathOpMir(.sub, ty, .{ .register = reg }, div_floor);
......@@ -2132,7 +2157,7 @@ fn airPtrSlicePtrPtr(self: *Self, inst: Air.Inst.Index) !void {
21322157
21332158fn elemOffset(self: *Self, index_ty: Type, index: MCValue, elem_size: u64) !Register {
21342159 const reg = try self.copyToTmpRegister(index_ty, index);
2135 try self.genIMulOpMir(index_ty, .{ .register = reg }, .{ .immediate = elem_size });
2160 try self.genIntMulComplexOpMir(index_ty, .{ .register = reg }, .{ .immediate = elem_size });
21362161 return reg;
21372162}
21382163
......@@ -3096,7 +3121,6 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
30963121 .bool_or, .bit_or => try self.genBinMathOpMir(.@"or", dst_ty, dst_mcv, src_mcv),
30973122 .bool_and, .bit_and => try self.genBinMathOpMir(.@"and", dst_ty, dst_mcv, src_mcv),
30983123 .xor, .not => try self.genBinMathOpMir(.xor, dst_ty, dst_mcv, src_mcv),
3099 .mul, .mulwrap, .mul_with_overflow => try self.genIMulOpMir(dst_ty, dst_mcv, src_mcv),
31003124 else => unreachable,
31013125 }
31023126 return dst_mcv;
......@@ -3252,8 +3276,10 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC
32523276 }
32533277}
32543278
3255// Performs integer multiplication between dst_mcv and src_mcv, storing the result in dst_mcv.
3256fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
3279/// Performs multi-operand integer multiplication between dst_mcv and src_mcv, storing the result in dst_mcv.
3280/// Does not use/spill .rax/.rdx.
3281/// Does not support byte-size operands.
3282fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
32573283 const abi_size = @intCast(u32, dst_ty.abiSize(self.target.*));
32583284 switch (dst_mcv) {
32593285 .none => unreachable,
......@@ -3299,7 +3325,7 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !
32993325 } else {
33003326 // TODO verify we don't spill and assign to the same register as dst_mcv
33013327 const src_reg = try self.copyToTmpRegister(dst_ty, src_mcv);
3302 return self.genIMulOpMir(dst_ty, dst_mcv, MCValue{ .register = src_reg });
3328 return self.genIntMulComplexOpMir(dst_ty, dst_mcv, MCValue{ .register = src_reg });
33033329 }
33043330 },
33053331 .stack_offset => |off| {
test/behavior/math.zig+3-5
......@@ -697,11 +697,9 @@ test "@mulWithOverflow" {
697697 try expect(!@mulWithOverflow(u8, a, b, &result));
698698 try expect(result == 246);
699699
700 if (builtin.zig_backend != .stage2_x86_64) { // TODO fix mul/imul on x86_64
701 b = 4;
702 try expect(@mulWithOverflow(u8, a, b, &result));
703 try expect(result == 236);
704 }
700 b = 4;
701 try expect(@mulWithOverflow(u8, a, b, &result));
702 try expect(result == 236);
705703}
706704
707705test "@subWithOverflow" {