| ... | @@ -1254,7 +1254,7 @@ fn genPtrBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_r | ... | @@ -1254,7 +1254,7 @@ fn genPtrBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_r |
| 1254 | offset_mcv.freezeIfRegister(&self.register_manager); | 1254 | offset_mcv.freezeIfRegister(&self.register_manager); |
| 1255 | defer offset_mcv.unfreezeIfRegister(&self.register_manager); | 1255 | defer offset_mcv.unfreezeIfRegister(&self.register_manager); |
| 1256 | | 1256 | |
| 1257 | try self.genIMulOpMir(offset_ty, offset_mcv, .{ .immediate = elem_size }); | 1257 | try self.genIntMulComplexOpMir(offset_ty, offset_mcv, .{ .immediate = elem_size }); |
| 1258 | | 1258 | |
| 1259 | const tag = self.air.instructions.items(.tag)[inst]; | 1259 | const tag = self.air.instructions.items(.tag)[inst]; |
| 1260 | switch (tag) { | 1260 | switch (tag) { |
| ... | @@ -1396,10 +1396,27 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -1396,10 +1396,27 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void { |
| 1396 | | 1396 | |
| 1397 | fn airMul(self: *Self, inst: Air.Inst.Index) !void { | 1397 | fn airMul(self: *Self, inst: Air.Inst.Index) !void { |
| 1398 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; | 1398 | const bin_op = self.air.instructions.items(.data)[inst].bin_op; |
| 1399 | const result: MCValue = if (self.liveness.isUnused(inst)) | 1399 | const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: { |
| 1400 | .dead | 1400 | const ty = self.air.typeOfIndex(inst); |
| 1401 | else | 1401 | |
| 1402 | try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs); | 1402 | if (ty.zigTypeTag() != .Int) { |
| | 1403 | return self.fail("TODO implement 'mul' for operands of dst type {}", .{ty.zigTypeTag()}); |
| | 1404 | } |
| | 1405 | |
| | 1406 | // Spill .rax and .rdx upfront to ensure we don't spill the operands too late. |
| | 1407 | try self.register_manager.getReg(.rax, null); |
| | 1408 | try self.register_manager.getReg(.rdx, null); |
| | 1409 | |
| | 1410 | const lhs = try self.resolveInst(bin_op.lhs); |
| | 1411 | const rhs = try self.resolveInst(bin_op.rhs); |
| | 1412 | |
| | 1413 | const signedness = ty.intInfo(self.target.*).signedness; |
| | 1414 | try self.genIntMulDivOpMir(switch (signedness) { |
| | 1415 | .signed => .imul, |
| | 1416 | .unsigned => .mul, |
| | 1417 | }, ty, signedness, lhs, rhs); |
| | 1418 | break :result MCValue{ .register = .rax }; |
| | 1419 | }; |
| 1403 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); | 1420 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); |
| 1404 | } | 1421 | } |
| 1405 | | 1422 | |
| ... | @@ -1474,23 +1491,31 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -1474,23 +1491,31 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void { |
| 1474 | fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void { | 1491 | fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void { |
| 1475 | const ty_pl = self.air.instructions.items(.data)[inst].ty_pl; | 1492 | const ty_pl = self.air.instructions.items(.data)[inst].ty_pl; |
| 1476 | const bin_op = self.air.extraData(Air.Bin, ty_pl.payload).data; | 1493 | const bin_op = self.air.extraData(Air.Bin, ty_pl.payload).data; |
| | 1494 | const result = if (self.liveness.isUnused(inst)) .dead else result: { |
| | 1495 | const ty = self.air.typeOf(bin_op.lhs); |
| | 1496 | const signedness: std.builtin.Signedness = blk: { |
| | 1497 | if (ty.zigTypeTag() != .Int) { |
| | 1498 | return self.fail("TODO implement airMulWithOverflow for type {}", .{ty.fmtDebug()}); |
| | 1499 | } |
| | 1500 | break :blk ty.intInfo(self.target.*).signedness; |
| | 1501 | }; |
| 1477 | | 1502 | |
| 1478 | if (self.liveness.isUnused(inst)) { | 1503 | // Spill .rax and .rdx upfront to ensure we don't spill the operands too late. |
| 1479 | return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none }); | 1504 | try self.register_manager.getReg(.rax, null); |
| 1480 | } | 1505 | try self.register_manager.getReg(.rdx, null); |
| 1481 | | 1506 | |
| 1482 | const ty = self.air.typeOf(bin_op.lhs); | 1507 | const lhs = try self.resolveInst(bin_op.lhs); |
| 1483 | const signedness: std.builtin.Signedness = blk: { | 1508 | const rhs = try self.resolveInst(bin_op.rhs); |
| 1484 | if (ty.zigTypeTag() != .Int) { | | |
| 1485 | return self.fail("TODO implement airMulWithOverflow for type {}", .{ty.fmtDebug()}); | | |
| 1486 | } | | |
| 1487 | break :blk ty.intInfo(self.target.*).signedness; | | |
| 1488 | }; | | |
| 1489 | | 1509 | |
| 1490 | const partial = try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs); | 1510 | try self.genIntMulDivOpMir(switch (signedness) { |
| 1491 | const result: MCValue = switch (signedness) { | 1511 | .signed => .imul, |
| 1492 | .signed => .{ .register_overflow_signed = partial.register }, | 1512 | .unsigned => .mul, |
| 1493 | .unsigned => .{ .register_overflow_unsigned = partial.register }, | 1513 | }, ty, signedness, lhs, rhs); |
| | 1514 | |
| | 1515 | switch (signedness) { |
| | 1516 | .signed => break :result MCValue{ .register_overflow_signed = .rax }, |
| | 1517 | .unsigned => break :result MCValue{ .register_overflow_unsigned = .rax }, |
| | 1518 | } |
| 1494 | }; | 1519 | }; |
| 1495 | | 1520 | |
| 1496 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); | 1521 | return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none }); |
| ... | @@ -1730,7 +1755,7 @@ fn airMod(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -1730,7 +1755,7 @@ fn airMod(self: *Self, inst: Air.Inst.Index) !void { |
| 1730 | }, | 1755 | }, |
| 1731 | .signed => { | 1756 | .signed => { |
| 1732 | const div_floor = try self.genInlineIntDivFloor(ty, lhs, rhs); | 1757 | const div_floor = try self.genInlineIntDivFloor(ty, lhs, rhs); |
| 1733 | try self.genIMulOpMir(ty, div_floor, rhs); | 1758 | try self.genIntMulComplexOpMir(ty, div_floor, rhs); |
| 1734 | | 1759 | |
| 1735 | const reg = try self.copyToTmpRegister(ty, lhs); | 1760 | const reg = try self.copyToTmpRegister(ty, lhs); |
| 1736 | try self.genBinMathOpMir(.sub, ty, .{ .register = reg }, div_floor); | 1761 | try self.genBinMathOpMir(.sub, ty, .{ .register = reg }, div_floor); |
| ... | @@ -2132,7 +2157,7 @@ fn airPtrSlicePtrPtr(self: *Self, inst: Air.Inst.Index) !void { | ... | @@ -2132,7 +2157,7 @@ fn airPtrSlicePtrPtr(self: *Self, inst: Air.Inst.Index) !void { |
| 2132 | | 2157 | |
| 2133 | fn elemOffset(self: *Self, index_ty: Type, index: MCValue, elem_size: u64) !Register { | 2158 | fn elemOffset(self: *Self, index_ty: Type, index: MCValue, elem_size: u64) !Register { |
| 2134 | const reg = try self.copyToTmpRegister(index_ty, index); | 2159 | const reg = try self.copyToTmpRegister(index_ty, index); |
| 2135 | try self.genIMulOpMir(index_ty, .{ .register = reg }, .{ .immediate = elem_size }); | 2160 | try self.genIntMulComplexOpMir(index_ty, .{ .register = reg }, .{ .immediate = elem_size }); |
| 2136 | return reg; | 2161 | return reg; |
| 2137 | } | 2162 | } |
| 2138 | | 2163 | |
| ... | @@ -3096,7 +3121,6 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: | ... | @@ -3096,7 +3121,6 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: |
| 3096 | .bool_or, .bit_or => try self.genBinMathOpMir(.@"or", dst_ty, dst_mcv, src_mcv), | 3121 | .bool_or, .bit_or => try self.genBinMathOpMir(.@"or", dst_ty, dst_mcv, src_mcv), |
| 3097 | .bool_and, .bit_and => try self.genBinMathOpMir(.@"and", dst_ty, dst_mcv, src_mcv), | 3122 | .bool_and, .bit_and => try self.genBinMathOpMir(.@"and", dst_ty, dst_mcv, src_mcv), |
| 3098 | .xor, .not => try self.genBinMathOpMir(.xor, dst_ty, dst_mcv, src_mcv), | 3123 | .xor, .not => try self.genBinMathOpMir(.xor, dst_ty, dst_mcv, src_mcv), |
| 3099 | .mul, .mulwrap, .mul_with_overflow => try self.genIMulOpMir(dst_ty, dst_mcv, src_mcv), | | |
| 3100 | else => unreachable, | 3124 | else => unreachable, |
| 3101 | } | 3125 | } |
| 3102 | return dst_mcv; | 3126 | return dst_mcv; |
| ... | @@ -3252,8 +3276,10 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC | ... | @@ -3252,8 +3276,10 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC |
| 3252 | } | 3276 | } |
| 3253 | } | 3277 | } |
| 3254 | | 3278 | |
| 3255 | // Performs integer multiplication between dst_mcv and src_mcv, storing the result in dst_mcv. | 3279 | /// Performs multi-operand integer multiplication between dst_mcv and src_mcv, storing the result in dst_mcv. |
| 3256 | fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void { | 3280 | /// Does not use/spill .rax/.rdx. |
| | 3281 | /// Does not support byte-size operands. |
| | 3282 | fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void { |
| 3257 | const abi_size = @intCast(u32, dst_ty.abiSize(self.target.*)); | 3283 | const abi_size = @intCast(u32, dst_ty.abiSize(self.target.*)); |
| 3258 | switch (dst_mcv) { | 3284 | switch (dst_mcv) { |
| 3259 | .none => unreachable, | 3285 | .none => unreachable, |
| ... | @@ -3299,7 +3325,7 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) ! | ... | @@ -3299,7 +3325,7 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) ! |
| 3299 | } else { | 3325 | } else { |
| 3300 | // TODO verify we don't spill and assign to the same register as dst_mcv | 3326 | // TODO verify we don't spill and assign to the same register as dst_mcv |
| 3301 | const src_reg = try self.copyToTmpRegister(dst_ty, src_mcv); | 3327 | const src_reg = try self.copyToTmpRegister(dst_ty, src_mcv); |
| 3302 | return self.genIMulOpMir(dst_ty, dst_mcv, MCValue{ .register = src_reg }); | 3328 | return self.genIntMulComplexOpMir(dst_ty, dst_mcv, MCValue{ .register = src_reg }); |
| 3303 | } | 3329 | } |
| 3304 | }, | 3330 | }, |
| 3305 | .stack_offset => |off| { | 3331 | .stack_offset => |off| { |
Jakub Konka <kubkon@jakubkonka.com> 2022-03-29 10:39:25+02:00
src