Commit ee72f06f47055ecf3fa650eae9ef49446745f509 | zig

author	Alex Rønne Petersen <alex@alexrp.com> 2025-10-20 03:43:03+02:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2025-10-23 09:27:17+02:00
log	ee72f06f47055ecf3fa650eae9ef49446745f509
tree	a97f16c8d6e40b487be730c32f8aca43445b5c3f
parent	c55e83eab1369373fe6db5072802c2fc1c4d7ebc
signature	Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: add tags and info for alpha, hppa, microblaze, sh

8 files changed, 561 insertions(+), 8 deletions(-)

lib
- std
  - Target.zig
  - builtin.zig
  - builtin
    assembly.zig
src
- Sema.zig
- codegen
  - c.zig
  - llvm.zig
- link
  - Dwarf.zig
- target.zig

lib/std/Target.zig+153-5

...	...	@@ -733,6 +733,7 @@ pub const Os = struct {
733	733	};
734	734
735	735	pub const aarch64 = @import("Target/aarch64.zig");
	736	pub const alpha = @import("Target/generic.zig");
736	737	pub const amdgcn = @import("Target/amdgcn.zig");
737	738	pub const arc = @import("Target/arc.zig");
738	739	pub const arm = @import("Target/arm.zig");
...	...	@@ -740,10 +741,12 @@ pub const avr = @import("Target/avr.zig");
740	741	pub const bpf = @import("Target/bpf.zig");
741	742	pub const csky = @import("Target/csky.zig");
742	743	pub const hexagon = @import("Target/hexagon.zig");
	744	pub const hppa = @import("Target/generic.zig");
743	745	pub const kalimba = @import("Target/generic.zig");
744	746	pub const lanai = @import("Target/lanai.zig");
745	747	pub const loongarch = @import("Target/loongarch.zig");
746	748	pub const m68k = @import("Target/m68k.zig");
	749	pub const microblaze = @import("Target/generic.zig");
747	750	pub const mips = @import("Target/mips.zig");
748	751	pub const msp430 = @import("Target/msp430.zig");
749	752	pub const nvptx = @import("Target/nvptx.zig");
...	...	@@ -752,6 +755,7 @@ pub const powerpc = @import("Target/powerpc.zig");
752	755	pub const propeller = @import("Target/propeller.zig");
753	756	pub const riscv = @import("Target/riscv.zig");
754	757	pub const s390x = @import("Target/s390x.zig");
	758	pub const sh = @import("Target/generic.zig");
755	759	pub const sparc = @import("Target/sparc.zig");
756	760	pub const spirv = @import("Target/spirv.zig");
757	761	pub const ve = @import("Target/ve.zig");
...	...	@@ -826,10 +830,13 @@ pub const Abi = enum {
826	830	.arm,
827	831	.armeb,
828	832	.csky,
	833	.hppa,
829	834	.mips,
830	835	.mipsel,
831	836	.powerpc,
832	837	.powerpcle,
	838	.sh,
	839	.sheb,
833	840	.thumb,
834	841	.thumbeb,
835	842	=> .eabi,
...	...	@@ -864,6 +871,10 @@ pub const Abi = enum {
864	871	=> .gnu,
865	872	.csky,
866	873	=> .gnueabi,
	874	.hppa,
	875	.sh,
	876	.sheb,
	877	=> .gnueabihf,
867	878
868	879	// No glibc or musl support.
869	880	.xtensa,
...	...	@@ -1064,6 +1075,7 @@ pub const ObjectFormat = enum {
1064	1075	pub fn toElfMachine(target: *const Target) std.elf.EM {
1065	1076	return switch (target.cpu.arch) {
1066	1077	.aarch64, .aarch64_be => .AARCH64,
	1078	.alpha => .ALPHA,
1067	1079	.amdgcn => .AMDGPU,
1068	1080	.arc, .arceb => .ARC_COMPACT,
1069	1081	.arm, .armeb, .thumb, .thumbeb => .ARM,
...	...	@@ -1071,10 +1083,12 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1071	1083	.bpfeb, .bpfel => .BPF,
1072	1084	.csky => .CSKY,
1073	1085	.hexagon => .QDSP6,
	1086	.hppa, .hppa64 => .PARISC,
1074	1087	.kalimba => .CSR_KALIMBA,
1075	1088	.lanai => .LANAI,
1076	1089	.loongarch32, .loongarch64 => .LOONGARCH,
1077	1090	.m68k => .@"68K",
	1091	.microblaze, .microblazeel => .MICROBLAZE,
1078	1092	.mips, .mips64, .mipsel, .mips64el => .MIPS,
1079	1093	.msp430 => .MSP430,
1080	1094	.or1k => .OR1K,
...	...	@@ -1083,6 +1097,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1083	1097	.propeller => .PROPELLER,
1084	1098	.riscv32, .riscv32be, .riscv64, .riscv64be => .RISCV,
1085	1099	.s390x => .S390,
	1100	.sh, .sheb => .SH,
1086	1101	.sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
1087	1102	.sparc64 => .SPARCV9,
1088	1103	.ve => .VE,
...	...	@@ -1103,6 +1118,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1103	1118
1104	1119	pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1105	1120	return switch (target.cpu.arch) {
	1121	.alpha => .ALPHA64,
1106	1122	.arm => .ARM,
1107	1123	.thumb => .ARMNT,
1108	1124	.aarch64 => .ARM64,
...	...	@@ -1114,6 +1130,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1114	1130	.powerpcle => .POWERPC,
1115	1131	.riscv32 => .RISCV32,
1116	1132	.riscv64 => .RISCV64,
	1133	.sh => .SH3,
1117	1134	.x86 => .I386,
1118	1135	.x86_64 => .AMD64,
1119	1136
...	...	@@ -1127,9 +1144,13 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1127	1144	.bpfel,
1128	1145	.csky,
1129	1146	.hexagon,
	1147	.hppa,
	1148	.hppa64,
1130	1149	.kalimba,
1131	1150	.lanai,
1132	1151	.m68k,
	1152	.microblaze,
	1153	.microblazeel,
1133	1154	.mips64,
1134	1155	.msp430,
1135	1156	.nvptx,
...	...	@@ -1142,6 +1163,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1142	1163	.riscv32be,
1143	1164	.riscv64be,
1144	1165	.s390x,
	1166	.sheb,
1145	1167	.sparc,
1146	1168	.sparc64,
1147	1169	.spirv32,
...	...	@@ -1323,6 +1345,7 @@ pub const Cpu = struct {
1323	1345	pub const Arch = enum {
1324	1346	aarch64,
1325	1347	aarch64_be,
	1348	alpha,
1326	1349	amdgcn,
1327	1350	arc,
1328	1351	arceb,
...	...	@@ -1333,11 +1356,15 @@ pub const Cpu = struct {
1333	1356	bpfel,
1334	1357	csky,
1335	1358	hexagon,
	1359	hppa,
	1360	hppa64,
1336	1361	kalimba,
1337	1362	lanai,
1338	1363	loongarch32,
1339	1364	loongarch64,
1340	1365	m68k,
	1366	microblaze,
	1367	microblazeel,
1341	1368	mips,
1342	1369	mipsel,
1343	1370	mips64,
...	...	@@ -1356,6 +1383,8 @@ pub const Cpu = struct {
1356	1383	riscv64,
1357	1384	riscv64be,
1358	1385	s390x,
	1386	sh,
	1387	sheb,
1359	1388	sparc,
1360	1389	sparc64,
1361	1390	spirv32,
...	...	@@ -1393,18 +1422,21 @@ pub const Cpu = struct {
1393	1422	/// For a given family tag, it is guaranteed that an `std.Target.<tag>` namespace exists
1394	1423	/// containing CPU model and feature data.
1395	1424	pub const Family = enum {
	1425	aarch64,
	1426	alpha,
1396	1427	amdgcn,
1397	1428	arc,
1398	1429	arm,
1399		aarch64,
1400	1430	avr,
1401	1431	bpf,
1402	1432	csky,
1403	1433	hexagon,
	1434	hppa,
1404	1435	kalimba,
1405	1436	lanai,
1406	1437	loongarch,
1407	1438	m68k,
	1439	microblaze,
1408	1440	mips,
1409	1441	msp430,
1410	1442	nvptx,
...	...	@@ -1413,6 +1445,7 @@ pub const Cpu = struct {
1413	1445	propeller,
1414	1446	riscv,
1415	1447	s390x,
	1448	sh,
1416	1449	sparc,
1417	1450	spirv,
1418	1451	ve,
...	...	@@ -1425,6 +1458,7 @@ pub const Cpu = struct {
1425	1458	pub inline fn family(arch: Arch) Family {
1426	1459	return switch (arch) {
1427	1460	.aarch64, .aarch64_be => .aarch64,
	1461	.alpha => .alpha,
1428	1462	.amdgcn => .amdgcn,
1429	1463	.arc, .arceb => .arc,
1430	1464	.arm, .armeb, .thumb, .thumbeb => .arm,
...	...	@@ -1432,10 +1466,12 @@ pub const Cpu = struct {
1432	1466	.bpfeb, .bpfel => .bpf,
1433	1467	.csky => .csky,
1434	1468	.hexagon => .hexagon,
	1469	.hppa, .hppa64 => .hppa,
1435	1470	.kalimba => .kalimba,
1436	1471	.lanai => .lanai,
1437	1472	.loongarch32, .loongarch64 => .loongarch,
1438	1473	.m68k => .m68k,
	1474	.microblaze, .microblazeel => .microblaze,
1439	1475	.mips, .mipsel, .mips64, .mips64el => .mips,
1440	1476	.msp430 => .msp430,
1441	1477	.or1k => .or1k,
...	...	@@ -1444,6 +1480,7 @@ pub const Cpu = struct {
1444	1480	.propeller => .propeller,
1445	1481	.riscv32, .riscv32be, .riscv64, .riscv64be => .riscv,
1446	1482	.s390x => .s390x,
	1483	.sh, .sheb => .sh,
1447	1484	.sparc, .sparc64 => .sparc,
1448	1485	.spirv32, .spirv64 => .spirv,
1449	1486	.ve => .ve,
...	...	@@ -1490,6 +1527,13 @@ pub const Cpu = struct {
1490	1527	};
1491	1528	}
1492	1529
	1530	pub inline fn isHppa(arch: Arch) bool {
	1531	return switch (arch) {
	1532	.hppa, .hppa64 => true,
	1533	else => false,
	1534	};
	1535	}
	1536
1493	1537	pub inline fn isWasm(arch: Arch) bool {
1494	1538	return switch (arch) {
1495	1539	.wasm32, .wasm64 => true,
...	...	@@ -1522,6 +1566,13 @@ pub const Cpu = struct {
1522	1566	};
1523	1567	}
1524	1568
	1569	pub inline fn isMicroblaze(arch: Arch) bool {
	1570	return switch (arch) {
	1571	.microblaze, .microblazeel => true,
	1572	else => false,
	1573	};
	1574	}
	1575
1525	1576	pub inline fn isMIPS(arch: Arch) bool {
1526	1577	return arch.isMIPS32() or arch.isMIPS64();
1527	1578	}
...	...	@@ -1572,6 +1623,13 @@ pub const Cpu = struct {
1572	1623	};
1573	1624	}
1574	1625
	1626	pub inline fn isSh(arch: Arch) bool {
	1627	return switch (arch) {
	1628	.sh, .sheb => true,
	1629	else => false,
	1630	};
	1631	}
	1632
1575	1633	pub inline fn isBpf(arch: Arch) bool {
1576	1634	return switch (arch) {
1577	1635	.bpfel, .bpfeb => true,
...	...	@@ -1605,6 +1663,7 @@ pub const Cpu = struct {
1605	1663	pub fn endian(arch: Arch) std.builtin.Endian {
1606	1664	return switch (arch) {
1607	1665	.aarch64,
	1666	.alpha,
1608	1667	.arm,
1609	1668	.arc,
1610	1669	.avr,
...	...	@@ -1614,6 +1673,7 @@ pub const Cpu = struct {
1614	1673	.kalimba,
1615	1674	.loongarch32,
1616	1675	.loongarch64,
	1676	.microblazeel,
1617	1677	.mipsel,
1618	1678	.mips64el,
1619	1679	.msp430,
...	...	@@ -1622,6 +1682,7 @@ pub const Cpu = struct {
1622	1682	.propeller,
1623	1683	.riscv32,
1624	1684	.riscv64,
	1685	.sh,
1625	1686	.thumb,
1626	1687	.ve,
1627	1688	.wasm32,
...	...	@@ -1636,8 +1697,11 @@ pub const Cpu = struct {
1636	1697	.arceb,
1637	1698	.armeb,
1638	1699	.bpfeb,
	1700	.hppa,
	1701	.hppa64,
1639	1702	.lanai,
1640	1703	.m68k,
	1704	.microblaze,
1641	1705	.mips,
1642	1706	.mips64,
1643	1707	.or1k,
...	...	@@ -1646,6 +1710,7 @@ pub const Cpu = struct {
1646	1710	.riscv32be,
1647	1711	.riscv64be,
1648	1712	.s390x,
	1713	.sheb,
1649	1714	.thumbeb,
1650	1715	.sparc,
1651	1716	.sparc64,
...	...	@@ -1748,6 +1813,9 @@ pub const Cpu = struct {
1748	1813	.aarch64_vfabi_sve,
1749	1814	=> &.{ .aarch64, .aarch64_be },
1750	1815
	1816	.alpha_osf,
	1817	=> &.{.alpha},
	1818
1751	1819	.arm_aapcs,
1752	1820	.arm_aapcs_vfp,
1753	1821	.arm_interrupt,
...	...	@@ -1813,6 +1881,12 @@ pub const Cpu = struct {
1813	1881	.hexagon_sysv_hvx,
1814	1882	=> &.{.hexagon},
1815	1883
	1884	.hppa_elf,
	1885	=> &.{.hppa},
	1886
	1887	.hppa64_elf,
	1888	=> &.{.hppa64},
	1889
1816	1890	.lanai_sysv,
1817	1891	=> &.{.lanai},
1818	1892
...	...	@@ -1828,6 +1902,9 @@ pub const Cpu = struct {
1828	1902	.m68k_interrupt,
1829	1903	=> &.{.m68k},
1830	1904
	1905	.microblaze_std,
	1906	=> &.{ .microblaze, .microblazeel },
	1907
1831	1908	.msp430_eabi,
1832	1909	=> &.{.msp430},
1833	1910
...	...	@@ -1841,6 +1918,10 @@ pub const Cpu = struct {
1841	1918	.s390x_sysv_vx,
1842	1919	=> &.{.s390x},
1843	1920
	1921	.sh_gnu,
	1922	.sh_renesas,
	1923	=> &.{ .sh, .sheb },
	1924
1844	1925	.ve_sysv,
1845	1926	=> &.{.ve},
1846	1927
...	...	@@ -2384,6 +2465,8 @@ pub const DynamicLinker = struct {
2384	2465	.aarch64_be,
2385	2466	.hexagon,
2386	2467	.m68k,
	2468	.microblaze,
	2469	.microblazeel,
2387	2470	.powerpc64,
2388	2471	.powerpc64le,
2389	2472	.s390x,
...	...	@@ -2419,6 +2502,17 @@ pub const DynamicLinker = struct {
2419	2502	else => return none,
2420	2503	}}),
2421	2504
	2505	.sh,
	2506	.sheb,
	2507	=> \|arch\| initFmt("/lib/ld-musl-{t}{s}.so.1", .{
	2508	arch,
	2509	switch (abi) {
	2510	.musleabi => "-nofpu",
	2511	.musleabihf => "",
	2512	else => return none,
	2513	},
	2514	}),
	2515
2422	2516	.riscv32,
2423	2517	.riscv64,
2424	2518	=> \|arch\| if (abi == .musl) initFmt("/lib/ld-musl-{s}{s}.so.1", .{
...	...	@@ -2432,6 +2526,7 @@ pub const DynamicLinker = struct {
2432	2526	}) else none,
2433	2527
2434	2528	.x86 => if (abi == .musl) init("/lib/ld-musl-i386.so.1") else none,
	2529
2435	2530	.x86_64 => initFmt("/lib/ld-musl-{s}.so.1", .{switch (abi) {
2436	2531	.musl => "x86_64",
2437	2532	.muslx32 => "x32",
...	...	@@ -2475,7 +2570,10 @@ pub const DynamicLinker = struct {
2475	2570	else => return none,
2476	2571	}}),
2477	2572
	2573	.hppa,
2478	2574	.m68k,
	2575	.microblaze,
	2576	.microblazeel,
2479	2577	.xtensa,
2480	2578	.xtensaeb,
2481	2579	=> if (abi == .gnu) init("/lib/ld.so.1") else none,
...	...	@@ -2531,10 +2629,22 @@ pub const DynamicLinker = struct {
2531	2629
2532	2630	.s390x => if (abi == .gnu) init("/lib/ld64.so.1") else none,
2533	2631
2534		.sparc => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
	2632	.sh,
	2633	.sheb,
	2634	=> switch (abi) {
	2635	.gnueabi,
	2636	.gnueabihf,
	2637	=> init("/lib/ld-linux.so.2"),
	2638	else => none,
	2639	},
	2640
	2641	.alpha,
	2642	.sparc,
	2643	.x86,
	2644	=> if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
	2645
2535	2646	.sparc64 => if (abi == .gnu) init("/lib64/ld-linux.so.2") else none,
2536	2647
2537		.x86 => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
2538	2648	.x86_64 => switch (abi) {
2539	2649	.gnu => init("/lib64/ld-linux-x86-64.so.2"),
2540	2650	.gnux32 => init("/libx32/ld-linux-x32.so.2"),
...	...	@@ -2712,10 +2822,13 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2712	2822	.armeb,
2713	2823	.csky,
2714	2824	.hexagon,
	2825	.hppa,
2715	2826	.kalimba,
2716	2827	.lanai,
2717	2828	.loongarch32,
2718	2829	.m68k,
	2830	.microblaze,
	2831	.microblazeel,
2719	2832	.mips,
2720	2833	.mipsel,
2721	2834	.nvptx,
...	...	@@ -2725,6 +2838,8 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2725	2838	.propeller,
2726	2839	.riscv32,
2727	2840	.riscv32be,
	2841	.sh,
	2842	.sheb,
2728	2843	.sparc,
2729	2844	.spirv32,
2730	2845	.thumb,
...	...	@@ -2738,9 +2853,11 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2738	2853
2739	2854	.aarch64,
2740	2855	.aarch64_be,
	2856	.alpha,
2741	2857	.amdgcn,
2742	2858	.bpfeb,
2743	2859	.bpfel,
	2860	.hppa64,
2744	2861	.loongarch64,
2745	2862	.mips64,
2746	2863	.mips64el,
...	...	@@ -2772,17 +2889,20 @@ pub fn stackAlignment(target: *const Target) u16 {
2772	2889	=> return 4,
2773	2890	.arm,
2774	2891	.armeb,
2775		.thumb,
2776		.thumbeb,
	2892	.hppa,
2777	2893	.lanai,
2778	2894	.mips,
2779	2895	.mipsel,
2780	2896	.sparc,
	2897	.thumb,
	2898	.thumbeb,
2781	2899	=> return 8,
2782	2900	.aarch64,
2783	2901	.aarch64_be,
	2902	.alpha,
2784	2903	.bpfeb,
2785	2904	.bpfel,
	2905	.hppa64,
2786	2906	.loongarch32,
2787	2907	.loongarch64,
2788	2908	.mips64,
...	...	@@ -2950,6 +3070,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
2950	3070	else => return 128,
2951	3071	},
2952	3072
	3073	.alpha,
2953	3074	.riscv32,
2954	3075	.riscv32be,
2955	3076	.riscv64,
...	...	@@ -3059,6 +3180,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
3059	3180	},
3060	3181	},
3061	3182
	3183	.alpha,
3062	3184	.riscv32,
3063	3185	.riscv32be,
3064	3186	.riscv64,
...	...	@@ -3251,8 +3373,12 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3251	3373	.arceb,
3252	3374	.csky,
3253	3375	.kalimba,
	3376	.microblaze,
	3377	.microblazeel,
3254	3378	.or1k,
3255	3379	.propeller,
	3380	.sh,
	3381	.sheb,
3256	3382	.x86,
3257	3383	.xcore,
3258	3384	.xtensa,
...	...	@@ -3265,6 +3391,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3265	3391	.bpfeb,
3266	3392	.bpfel,
3267	3393	.hexagon,
	3394	.hppa,
3268	3395	.lanai,
3269	3396	.m68k,
3270	3397	.mips,
...	...	@@ -3279,6 +3406,8 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3279	3406
3280	3407	.aarch64,
3281	3408	.aarch64_be,
	3409	.alpha,
	3410	.hppa64,
3282	3411	.loongarch32,
3283	3412	.loongarch64,
3284	3413	.mips64,
...	...	@@ -3351,8 +3480,12 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3351	3480	.arceb,
3352	3481	.csky,
3353	3482	.kalimba,
	3483	.microblaze,
	3484	.microblazeel,
3354	3485	.or1k,
3355	3486	.propeller,
	3487	.sh,
	3488	.sheb,
3356	3489	.xcore,
3357	3490	.xtensa,
3358	3491	.xtensaeb,
...	...	@@ -3364,6 +3497,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3364	3497	.bpfeb,
3365	3498	.bpfel,
3366	3499	.hexagon,
	3500	.hppa,
3367	3501	.lanai,
3368	3502	.m68k,
3369	3503	.mips,
...	...	@@ -3379,6 +3513,8 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3379	3513
3380	3514	.aarch64,
3381	3515	.aarch64_be,
	3516	.alpha,
	3517	.hppa64,
3382	3518	.loongarch32,
3383	3519	.loongarch64,
3384	3520	.mips64,
...	...	@@ -3416,14 +3552,19 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3416	3552	.arceb,
3417	3553	.csky,
3418	3554	.kalimba,
	3555	.microblaze,
	3556	.microblazeel,
3419	3557	.or1k,
3420	3558	.propeller,
	3559	.sh,
	3560	.sheb,
3421	3561	.xcore,
3422	3562	=> 4,
3423	3563
3424	3564	.arm,
3425	3565	.armeb,
3426	3566	.hexagon,
	3567	.hppa,
3427	3568	.lanai,
3428	3569	.loongarch32,
3429	3570	.m68k,
...	...	@@ -3444,9 +3585,11 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3444	3585
3445	3586	.aarch64,
3446	3587	.aarch64_be,
	3588	.alpha,
3447	3589	.amdgcn,
3448	3590	.bpfel,
3449	3591	.bpfeb,
	3592	.hppa64,
3450	3593	.loongarch64,
3451	3594	.mips64,
3452	3595	.mips64el,
...	...	@@ -3483,6 +3626,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3483	3626	.windows => .{ .aarch64_aapcs_win = .{} },
3484	3627	else => .{ .aarch64_aapcs = .{} },
3485	3628	},
	3629	.alpha => .{ .alpha_osf = .{} },
3486	3630	.arm, .armeb, .thumb, .thumbeb => switch (target.abi.float()) {
3487	3631	.soft => .{ .arm_aapcs = .{} },
3488	3632	.hard => .{ .arm_aapcs_vfp = .{} },
...	...	@@ -3511,6 +3655,8 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3511	3655	.bpfel, .bpfeb => .{ .bpf_std = .{} },
3512	3656	.csky => .{ .csky_sysv = .{} },
3513	3657	.hexagon => .{ .hexagon_sysv = .{} },
	3658	.hppa => .{ .hppa_elf = .{} },
	3659	.hppa64 => .{ .hppa64_elf = .{} },
3514	3660	.kalimba => null,
3515	3661	.lanai => .{ .lanai_sysv = .{} },
3516	3662	.loongarch64 => .{ .loongarch64_lp64 = .{} },
...	...	@@ -3519,10 +3665,12 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3519	3665	.{ .m68k_gnu = .{} }
3520	3666	else
3521	3667	.{ .m68k_sysv = .{} },
	3668	.microblaze, .microblazeel => .{ .microblaze_std = .{} },
3522	3669	.msp430 => .{ .msp430_eabi = .{} },
3523	3670	.or1k => .{ .or1k_sysv = .{} },
3524	3671	.propeller => .{ .propeller_sysv = .{} },
3525	3672	.s390x => .{ .s390x_sysv = .{} },
	3673	.sh, .sheb => .{ .sh_gnu = .{} },
3526	3674	.ve => .{ .ve_sysv = .{} },
3527	3675	.xcore => .{ .xcore_xs1 = .{} },
3528	3676	.xtensa, .xtensaeb => .{ .xtensa_windowed = .{} },

lib/std/builtin.zig+39

...	...	@@ -229,6 +229,9 @@ pub const CallingConvention = union(enum(u8)) {
229	229	aarch64_vfabi: CommonOptions,
230	230	aarch64_vfabi_sve: CommonOptions,
231	231
	232	/// The standard `alpha` calling convention.
	233	alpha_osf: CommonOptions,
	234
232	235	// Calling convetions for the `arm`, `armeb`, `thumb`, and `thumbeb` architectures.
233	236	/// ARM Architecture Procedure Call Standard
234	237	arm_aapcs: CommonOptions,
...	...	@@ -296,6 +299,12 @@ pub const CallingConvention = union(enum(u8)) {
296	299	hexagon_sysv: CommonOptions,
297	300	hexagon_sysv_hvx: CommonOptions,
298	301
	302	/// The standard `hppa` calling convention.
	303	hppa_elf: CommonOptions,
	304
	305	/// The standard `hppa64` calling convention.
	306	hppa64_elf: CommonOptions,
	307
299	308	/// The standard `lanai` calling convention.
300	309	lanai_sysv: CommonOptions,
301	310
...	...	@@ -311,6 +320,9 @@ pub const CallingConvention = union(enum(u8)) {
311	320	m68k_rtd: CommonOptions,
312	321	m68k_interrupt: CommonOptions,
313	322
	323	/// The standard `microblaze`/`microblazeel` calling convention.
	324	microblaze_std: CommonOptions,
	325
314	326	/// The standard `msp430` calling convention.
315	327	msp430_eabi: CommonOptions,
316	328
...	...	@@ -324,6 +336,10 @@ pub const CallingConvention = union(enum(u8)) {
324	336	s390x_sysv: CommonOptions,
325	337	s390x_sysv_vx: CommonOptions,
326	338
	339	// Calling conventions for the `sh`/`sheb` architecture.
	340	sh_gnu: CommonOptions,
	341	sh_renesas: CommonOptions,
	342
327	343	/// The standard `ve` calling convention.
328	344	ve_sysv: CommonOptions,
329	345
...	...	@@ -858,6 +874,13 @@ pub const VaListAarch64 = extern struct {
858	874	__vr_offs: c_int,
859	875	};
860	876
	877	/// This data structure is used by the Zig language code generation and
	878	/// therefore must be kept in sync with the compiler implementation.
	879	pub const VaListAlpha = extern struct {
	880	__base: *anyopaque,
	881	__offset: c_int,
	882	};
	883
861	884	/// This data structure is used by the Zig language code generation and
862	885	/// therefore must be kept in sync with the compiler implementation.
863	886	pub const VaListArm = extern struct {
...	...	@@ -891,6 +914,16 @@ pub const VaListS390x = extern struct {
891	914	__overflow_area_pointer: *anyopaque,
892	915	};
893	916
	917	/// This data structure is used by the Zig language code generation and
	918	/// therefore must be kept in sync with the compiler implementation.
	919	pub const VaListSh = extern struct {
	920	__va_next_o: *anyopaque,
	921	__va_next_o_limit: *anyopaque,
	922	__va_next_fp: *anyopaque,
	923	__va_next_fp_limit: *anyopaque,
	924	__va_next_stack: *anyopaque,
	925	};
	926
894	927	/// This data structure is used by the Zig language code generation and
895	928	/// therefore must be kept in sync with the compiler implementation.
896	929	pub const VaListX86_64 = extern struct {
...	...	@@ -925,10 +958,14 @@ pub const VaList = switch (builtin.cpu.arch) {
925	958	.bpfel,
926	959	.bpfeb,
927	960	.csky,
	961	.hppa,
	962	.hppa64,
928	963	.lanai,
929	964	.loongarch32,
930	965	.loongarch64,
931	966	.m68k,
	967	.microblaze,
	968	.microblazeel,
932	969	.mips,
933	970	.mipsel,
934	971	.mips64,
...	...	@@ -953,6 +990,7 @@ pub const VaList = switch (builtin.cpu.arch) {
953	990	.stage2_llvm => @compileError("disabled due to miscompilations"),
954	991	},
955	992	},
	993	.alpha => VaListAlpha,
956	994	.arm, .armeb, .thumb, .thumbeb => VaListArm,
957	995	.hexagon => if (builtin.target.abi.isMusl()) VaListHexagon else *u8,
958	996	.powerpc, .powerpcle => switch (builtin.os.tag) {
...	...	@@ -960,6 +998,7 @@ pub const VaList = switch (builtin.cpu.arch) {
960	998	else => VaListPowerPc,
961	999	},
962	1000	.s390x => VaListS390x,
	1001	.sh, .sheb => VaListSh, // This is wrong for `sh_renesas`: https://github.com/ziglang/zig/issues/24692#issuecomment-3150779829
963	1002	.x86_64 => switch (builtin.os.tag) {
964	1003	.uefi, .windows => switch (builtin.zig_backend) {
965	1004	else => *u8,

lib/std/builtin/assembly.zig+315

...	...	@@ -2197,6 +2197,321 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
2197	2197	msa_map: bool = false,
2198	2198	msa_unmap: bool = false,
2199	2199	},
	2200	.alpha => packed struct {
	2201	/// Whether the inline assembly code may perform stores to memory
	2202	/// addresses other than those derived from input pointer provenance.
	2203	memory: bool = false,
	2204
	2205	r0: bool = false,
	2206	r1: bool = false,
	2207	r2: bool = false,
	2208	r3: bool = false,
	2209	r4: bool = false,
	2210	r5: bool = false,
	2211	r6: bool = false,
	2212	r7: bool = false,
	2213	r8: bool = false,
	2214	r9: bool = false,
	2215	r10: bool = false,
	2216	r11: bool = false,
	2217	r12: bool = false,
	2218	r13: bool = false,
	2219	r14: bool = false,
	2220	r15: bool = false,
	2221	r16: bool = false,
	2222	r17: bool = false,
	2223	r18: bool = false,
	2224	r19: bool = false,
	2225	r20: bool = false,
	2226	r21: bool = false,
	2227	r22: bool = false,
	2228	r23: bool = false,
	2229	r24: bool = false,
	2230	r25: bool = false,
	2231	r26: bool = false,
	2232	r27: bool = false,
	2233	r28: bool = false,
	2234	r29: bool = false,
	2235	r30: bool = false,
	2236
	2237	f0: bool = false,
	2238	f1: bool = false,
	2239	f2: bool = false,
	2240	f3: bool = false,
	2241	f4: bool = false,
	2242	f5: bool = false,
	2243	f6: bool = false,
	2244	f7: bool = false,
	2245	f8: bool = false,
	2246	f9: bool = false,
	2247	f10: bool = false,
	2248	f11: bool = false,
	2249	f12: bool = false,
	2250	f13: bool = false,
	2251	f14: bool = false,
	2252	f15: bool = false,
	2253	f16: bool = false,
	2254	f17: bool = false,
	2255	f18: bool = false,
	2256	f19: bool = false,
	2257	f20: bool = false,
	2258	f21: bool = false,
	2259	f22: bool = false,
	2260	f23: bool = false,
	2261	f24: bool = false,
	2262	f25: bool = false,
	2263	f26: bool = false,
	2264	f27: bool = false,
	2265	f28: bool = false,
	2266	f29: bool = false,
	2267	f30: bool = false,
	2268	},
	2269	.hppa, .hppa64 => packed struct {
	2270	/// Whether the inline assembly code may perform stores to memory
	2271	/// addresses other than those derived from input pointer provenance.
	2272	memory: bool = false,
	2273
	2274	sar: bool = false,
	2275
	2276	r1: bool = false,
	2277	r2: bool = false,
	2278	r3: bool = false,
	2279	r4: bool = false,
	2280	r5: bool = false,
	2281	r6: bool = false,
	2282	r7: bool = false,
	2283	r8: bool = false,
	2284	r9: bool = false,
	2285	r10: bool = false,
	2286	r11: bool = false,
	2287	r12: bool = false,
	2288	r13: bool = false,
	2289	r14: bool = false,
	2290	r15: bool = false,
	2291	r16: bool = false,
	2292	r17: bool = false,
	2293	r18: bool = false,
	2294	r19: bool = false,
	2295	r20: bool = false,
	2296	r21: bool = false,
	2297	r22: bool = false,
	2298	r23: bool = false,
	2299	r24: bool = false,
	2300	r25: bool = false,
	2301	r26: bool = false,
	2302	r27: bool = false,
	2303	r28: bool = false,
	2304	r29: bool = false,
	2305	r30: bool = false,
	2306	r31: bool = false,
	2307
	2308	fr4: bool = false,
	2309	fr5: bool = false,
	2310	fr6: bool = false,
	2311	fr7: bool = false,
	2312	fr8: bool = false,
	2313	fr9: bool = false,
	2314	fr10: bool = false,
	2315	fr11: bool = false,
	2316	fr12: bool = false,
	2317	fr13: bool = false,
	2318	fr14: bool = false,
	2319	fr15: bool = false,
	2320	fr16: bool = false,
	2321	fr17: bool = false,
	2322	fr18: bool = false,
	2323	fr19: bool = false,
	2324	fr20: bool = false,
	2325	fr21: bool = false,
	2326	fr22: bool = false,
	2327	fr23: bool = false,
	2328	fr24: bool = false,
	2329	fr25: bool = false,
	2330	fr26: bool = false,
	2331	fr27: bool = false,
	2332	fr28: bool = false,
	2333	fr29: bool = false,
	2334	fr30: bool = false,
	2335	fr31: bool = false,
	2336
	2337	fr4r: bool = false,
	2338	fr5r: bool = false,
	2339	fr6r: bool = false,
	2340	fr7r: bool = false,
	2341	fr8r: bool = false,
	2342	fr9r: bool = false,
	2343	fr10r: bool = false,
	2344	fr11r: bool = false,
	2345	fr12r: bool = false,
	2346	fr13r: bool = false,
	2347	fr14r: bool = false,
	2348	fr15r: bool = false,
	2349	fr16r: bool = false,
	2350	fr17r: bool = false,
	2351	fr18r: bool = false,
	2352	fr19r: bool = false,
	2353	fr20r: bool = false,
	2354	fr21r: bool = false,
	2355	fr22r: bool = false,
	2356	fr23r: bool = false,
	2357	fr24r: bool = false,
	2358	fr25r: bool = false,
	2359	fr26r: bool = false,
	2360	fr27r: bool = false,
	2361	fr28r: bool = false,
	2362	fr29r: bool = false,
	2363	fr30r: bool = false,
	2364	fr31r: bool = false,
	2365	},
	2366	.microblaze, .microblazeel => packed struct {
	2367	/// Whether the inline assembly code may perform stores to memory
	2368	/// addresses other than those derived from input pointer provenance.
	2369	memory: bool = false,
	2370
	2371	rmsr: bool = false,
	2372
	2373	r1: bool = false,
	2374	r2: bool = false,
	2375	r3: bool = false,
	2376	r4: bool = false,
	2377	r5: bool = false,
	2378	r6: bool = false,
	2379	r7: bool = false,
	2380	r8: bool = false,
	2381	r9: bool = false,
	2382	r10: bool = false,
	2383	r11: bool = false,
	2384	r12: bool = false,
	2385	r13: bool = false,
	2386	r14: bool = false,
	2387	r15: bool = false,
	2388	r16: bool = false,
	2389	r17: bool = false,
	2390	r18: bool = false,
	2391	r19: bool = false,
	2392	r20: bool = false,
	2393	r21: bool = false,
	2394	r22: bool = false,
	2395	r23: bool = false,
	2396	r24: bool = false,
	2397	r25: bool = false,
	2398	r26: bool = false,
	2399	r27: bool = false,
	2400	r28: bool = false,
	2401	r29: bool = false,
	2402	r30: bool = false,
	2403	r31: bool = false,
	2404	},
	2405	.sh, .sheb => packed struct {
	2406	/// Whether the inline assembly code may perform stores to memory
	2407	/// addresses other than those derived from input pointer provenance.
	2408	memory: bool = false,
	2409
	2410	sr: bool = false,
	2411	gbr: bool = false,
	2412	pr: bool = false,
	2413
	2414	r0: bool = false,
	2415	r1: bool = false,
	2416	r2: bool = false,
	2417	r3: bool = false,
	2418	r4: bool = false,
	2419	r5: bool = false,
	2420	r6: bool = false,
	2421	r7: bool = false,
	2422	r8: bool = false,
	2423	r9: bool = false,
	2424	r10: bool = false,
	2425	r11: bool = false,
	2426	r12: bool = false,
	2427	r13: bool = false,
	2428	r14: bool = false,
	2429	r15: bool = false,
	2430
	2431	mach: bool = false,
	2432	macl: bool = false,
	2433
	2434	fr0: bool = false,
	2435	fr1: bool = false,
	2436	fr2: bool = false,
	2437	fr3: bool = false,
	2438	fr4: bool = false,
	2439	fr5: bool = false,
	2440	fr6: bool = false,
	2441	fr7: bool = false,
	2442	fr8: bool = false,
	2443	fr9: bool = false,
	2444	fr10: bool = false,
	2445	fr11: bool = false,
	2446	fr12: bool = false,
	2447	fr13: bool = false,
	2448	fr14: bool = false,
	2449	fr15: bool = false,
	2450
	2451	dr0: bool = false,
	2452	dr2: bool = false,
	2453	dr4: bool = false,
	2454	dr6: bool = false,
	2455	dr8: bool = false,
	2456	dr10: bool = false,
	2457	dr12: bool = false,
	2458	dr14: bool = false,
	2459
	2460	fv0: bool = false,
	2461	fv4: bool = false,
	2462	fv8: bool = false,
	2463	fv12: bool = false,
	2464
	2465	xf0: bool = false,
	2466	xf1: bool = false,
	2467	xf2: bool = false,
	2468	xf3: bool = false,
	2469	xf4: bool = false,
	2470	xf5: bool = false,
	2471	xf6: bool = false,
	2472	xf7: bool = false,
	2473	xf8: bool = false,
	2474	xf9: bool = false,
	2475	xf10: bool = false,
	2476	xf11: bool = false,
	2477	xf12: bool = false,
	2478	xf13: bool = false,
	2479	xf14: bool = false,
	2480	xf15: bool = false,
	2481
	2482	xd0: bool = false,
	2483	xd2: bool = false,
	2484	xd4: bool = false,
	2485	xd6: bool = false,
	2486	xd8: bool = false,
	2487	xd10: bool = false,
	2488	xd12: bool = false,
	2489	xd14: bool = false,
	2490
	2491	xmtrx: bool = false,
	2492
	2493	fpul: bool = false,
	2494	fpscr: bool = false,
	2495
	2496	ms: bool = false,
	2497	me: bool = false,
	2498
	2499	rs: bool = false,
	2500	re: bool = false,
	2501
	2502	a0: bool = false,
	2503	a0g: bool = false,
	2504	a1: bool = false,
	2505	a1g: bool = false,
	2506	m0: bool = false,
	2507	m1: bool = false,
	2508	x0: bool = false,
	2509	x1: bool = false,
	2510	y0: bool = false,
	2511	y1: bool = false,
	2512
	2513	dsr: bool = false,
	2514	},
2200	2515	else => packed struct {
2201	2516	/// Whether the inline assembly code may perform stores to memory
2202	2517	/// addresses other than those derived from input pointer provenance.

src/Sema.zig+6

...	...	@@ -9043,8 +9043,10 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9043	9043	.aarch64_aapcs_win,
9044	9044	.aarch64_vfabi,
9045	9045	.aarch64_vfabi_sve,
	9046	.alpha_osf,
9046	9047	.arm_aapcs,
9047	9048	.arm_aapcs_vfp,
	9049	.microblaze_std,
9048	9050	.mips64_n64,
9049	9051	.mips64_n32,
9050	9052	.mips_o32,
...	...	@@ -9068,6 +9070,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9068	9070	.csky_sysv,
9069	9071	.hexagon_sysv,
9070	9072	.hexagon_sysv_hvx,
	9073	.hppa_elf,
	9074	.hppa64_elf,
9071	9075	.lanai_sysv,
9072	9076	.loongarch64_lp64,
9073	9077	.loongarch32_ilp32,
...	...	@@ -9078,6 +9082,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9078	9082	.or1k_sysv,
9079	9083	.s390x_sysv,
9080	9084	.s390x_sysv_vx,
	9085	.sh_gnu,
	9086	.sh_renesas,
9081	9087	.ve_sysv,
9082	9088	.xcore_xs1,
9083	9089	.xcore_xs2,

src/codegen/c.zig+2

...	...	@@ -8106,6 +8106,8 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8106	8106	inline else => \|m\| "interrupt(\"" ++ @tagName(m) ++ "\")",
8107	8107	},
8108	8108
	8109	.sh_renesas => "renesas",
	8110
8109	8111	.m68k_rtd => "m68k_rtd",
8110	8112
8111	8113	.avr_interrupt,

src/codegen/llvm.zig+27

...	...	@@ -106,10 +106,17 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
106	106	.wasm64 => "wasm64",
107	107	.ve => "ve",
108	108
	109	.alpha,
109	110	.arceb,
	111	.hppa,
	112	.hppa64,
110	113	.kalimba,
	114	.microblaze,
	115	.microblazeel,
111	116	.or1k,
112	117	.propeller,
	118	.sh,
	119	.sheb,
113	120	.xtensaeb,
114	121	=> unreachable, // Gated by hasLlvmSupport().
115	122	};
...	...	@@ -475,10 +482,17 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
475	482	.loongarch64 => "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
476	483	.xtensa => "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32",
477	484
	485	.alpha,
478	486	.arceb,
	487	.hppa,
	488	.hppa64,
479	489	.kalimba,
	490	.microblaze,
	491	.microblazeel,
480	492	.or1k,
481	493	.propeller,
	494	.sh,
	495	.sheb,
482	496	.xtensaeb,
483	497	=> unreachable, // Gated by hasLlvmSupport().
484	498	};
...	...	@@ -11908,6 +11922,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11908	11922	.aarch64_aapcs,
11909	11923	.aarch64_aapcs_darwin,
11910	11924	.aarch64_aapcs_win,
	11925	.alpha_osf,
	11926	.microblaze_std,
11911	11927	.mips64_n64,
11912	11928	.mips64_n32,
11913	11929	.mips_o32,
...	...	@@ -11930,6 +11946,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11930	11946	.csky_sysv,
11931	11947	.hexagon_sysv,
11932	11948	.hexagon_sysv_hvx,
	11949	.hppa_elf,
	11950	.hppa64_elf,
11933	11951	.lanai_sysv,
11934	11952	.loongarch64_lp64,
11935	11953	.loongarch32_ilp32,
...	...	@@ -11940,6 +11958,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11940	11958	.propeller_sysv,
11941	11959	.s390x_sysv,
11942	11960	.s390x_sysv_vx,
	11961	.sh_gnu,
	11962	.sh_renesas,
11943	11963	.ve_sysv,
11944	11964	.xcore_xs1,
11945	11965	.xcore_xs2,
...	...	@@ -13111,10 +13131,17 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13111	13131	},
13112	13132
13113	13133	// LLVM does does not have a backend for these.
	13134	.alpha,
13114	13135	.arceb,
	13136	.hppa,
	13137	.hppa64,
13115	13138	.kalimba,
	13139	.microblaze,
	13140	.microblazeel,
13116	13141	.or1k,
13117	13142	.propeller,
	13143	.sh,
	13144	.sheb,
13118	13145	.xtensaeb,
13119	13146	=> unreachable,
13120	13147	}

src/link/Dwarf.zig+2

...	...	@@ -3905,6 +3905,8 @@ fn updateLazyType(
3905	3905
3906	3906	.m68k_rtd => .LLVM_M68kRTD,
3907	3907
	3908	.sh_renesas => .GNU_renesas_sh,
	3909
3908	3910	.amdgcn_kernel => .LLVM_OpenCLKernel,
3909	3911	.nvptx_kernel,
3910	3912	.spirv_kernel,

src/target.zig+17-3

...	...	@@ -216,10 +216,17 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
216	216	=> false,
217	217
218	218	// No LLVM backend exists.
	219	.alpha,
219	220	.arceb,
	221	.hppa,
	222	.hppa64,
220	223	.kalimba,
	224	.microblaze,
	225	.microblazeel,
221	226	.or1k,
222	227	.propeller,
	228	.sh,
	229	.sheb,
223	230	.xtensaeb,
224	231	=> false,
225	232	};
...	...	@@ -709,19 +716,26 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
709	716	.csky,
710	717	.m68k,
711	718	.msp430,
	719	.sh,
	720	.sheb,
712	721	.s390x,
713	722	.xcore,
714	723	=> .@"2",
	724	.aarch64,
	725	.aarch64_be,
	726	.alpha,
715	727	.arc,
716	728	.arceb,
717	729	.arm,
718	730	.armeb,
719		.aarch64,
720		.aarch64_be,
721	731	.hexagon,
	732	.hppa,
	733	.hppa64,
722	734	.lanai,
723	735	.loongarch32,
724	736	.loongarch64,
	737	.microblaze,
	738	.microblazeel,
725	739	.mips,
726	740	.mipsel,
727	741	.powerpc,
...	...	@@ -733,8 +747,8 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
733	747	.xtensa,
734	748	.xtensaeb,
735	749	=> .@"4",
736		.bpfel,
737	750	.bpfeb,
	751	.bpfel,
738	752	.mips64,
739	753	.mips64el,
740	754	=> .@"8",