Commit f12beb857ad7868396a4246b8f62f83f625c0978 | zig

author	Robin Voetter <robin@voetter.nl> 2023-04-08 14:17:34+02:00
committer	Robin Voetter <robin@voetter.nl> 2023-04-09 01:51:54+02:00
log	f12beb857ad7868396a4246b8f62f83f625c0978
tree	ee82e5c5b60c48db8122adaa6f74763ea756c2a4
parent	3f2025f59e4488bff9e046cabbbff047fa1db508
signature	Commit is signed but in an unrecognized format.

amdgpu,nvptx: unify kernel calling conventions

AmdgpuKernel and NvptxKernel are unified into a Kernel calling convention.
There is really no reason for these to be separate; no backend is allowed to
emit the calling convention of the other. This is in the same spirit as the
.Interrupt calling convention lowering to different LLVM calling conventions,
and opens the way for SPIR-V kernels to be exported using the Kernel calling
convention.

6 files changed, 27 insertions(+), 30 deletions(-)

lib
- std
  - builtin.zig
src
- Sema.zig
- codegen
  - llvm.zig
- link
  - NvPtx.zig
- type.zig
test
- nvptx.zig

lib/std/builtin.zig+1-2

...	@@ -160,8 +160,7 @@ pub const CallingConvention = enum {	...	@@ -160,8 +160,7 @@ pub const CallingConvention = enum {
160	AAPCSVFP,	160	AAPCSVFP,
161	SysV,	161	SysV,
162	Win64,	162	Win64,
163	PtxKernel,	163	Kernel,
164	AmdgpuKernel,
165	};	164	};
166		165
167	/// This data structure is used by the Zig language code generation and	166	/// This data structure is used by the Zig language code generation and

src/Sema.zig+15-17

 @@ -8883,7 +8883,7 @@ fn funcCommon(
             };
             return sema.failWithOwnedErrorMsg(msg);
         }
-        if (!ret_poison and !Type.fnCallingConventionAllowsZigTypes(cc_resolved) and !try sema.validateExternType(return_type, .ret_ty)) {
+        if (!ret_poison and !Type.fnCallingConventionAllowsZigTypes(target, cc_resolved) and !try sema.validateExternType(return_type, .ret_ty)) {
             const msg = msg: {
                 const msg = try sema.errMsg(block, ret_ty_src, "return type '{}' not allowed in function with calling convention '{s}'", .{
                     return_type.fmt(sema.mod), @tagName(cc_resolved),
 @@ -8961,13 +8961,9 @@ fn funcCommon(
                 .x86_64 => null,
                 else => @as([]const u8, "x86_64"),
             },
-            .PtxKernel => switch (arch) {
+            .Kernel => switch (arch) {
-                .nvptx, .nvptx64 => null,
+                .nvptx, .nvptx64, .amdgcn, .spirv32, .spirv64 => null,
-                else => @as([]const u8, "nvptx and nvptx64"),
+                else => @as([]const u8, "nvptx, amdgcn and SPIR-V"),
-            },
-            .AmdgpuKernel => switch (arch) {
-                .amdgcn => null,
-                else => @as([]const u8, "amdgcn"),
             },
         }) |allowed_platform| {
             return sema.fail(block, cc_src, "callconv '{s}' is only available on {s}, not {s}", .{
 @@ -9093,10 +9089,11 @@ fn analyzeParameter(
     comptime_params[i] = param.is_comptime or requires_comptime;
     const this_generic = param.ty.tag() == .generic_poison;
     is_generic.* = is_generic.* or this_generic;
-    if (param.is_comptime and !Type.fnCallingConventionAllowsZigTypes(cc)) {
+    const target = sema.mod.getTarget();
+    if (param.is_comptime and !Type.fnCallingConventionAllowsZigTypes(target, cc)) {
         return sema.fail(block, param_src, "comptime parameters not allowed in function with calling convention '{s}'", .{@tagName(cc)});
     }
-    if (this_generic and !sema.no_partial_func_ty and !Type.fnCallingConventionAllowsZigTypes(cc)) {
+    if (this_generic and !sema.no_partial_func_ty and !Type.fnCallingConventionAllowsZigTypes(target, cc)) {
         return sema.fail(block, param_src, "generic parameters not allowed in function with calling convention '{s}'", .{@tagName(cc)});
     }
     if (!param.ty.isValidParamType()) {
 @@ -9112,7 +9109,7 @@ fn analyzeParameter(
         };
         return sema.failWithOwnedErrorMsg(msg);
     }
-    if (!this_generic and !Type.fnCallingConventionAllowsZigTypes(cc) and !try sema.validateExternType(param.ty, .param_ty)) {
+    if (!this_generic and !Type.fnCallingConventionAllowsZigTypes(target, cc) and !try sema.validateExternType(param.ty, .param_ty)) {
         const msg = msg: {
             const msg = try sema.errMsg(block, param_src, "parameter of type '{}' not allowed in function with calling convention '{s}'", .{
                 param.ty.fmt(sema.mod), @tagName(cc),
 @@ -22786,12 +22783,13 @@ fn validateExternType(
         },
         .Fn => {
             if (position != .other) return false;
-            return switch (ty.fnCallingConvention()) {
+            const target = sema.mod.getTarget();
-                // For now we want to authorize PTX kernel to use zig objects, even if we end up exposing the ABI.
+            // For now we want to authorize PTX kernel to use zig objects, even if we end up exposing the ABI.
-                // The goal is to experiment with more integrated CPU/GPU code.
+            // The goal is to experiment with more integrated CPU/GPU code.
-                .PtxKernel => true,
+            if (ty.fnCallingConvention() == .Kernel and (target.cpu.arch == .nvptx or target.cpu.arch == .nvptx64)) {
-                else => !Type.fnCallingConventionAllowsZigTypes(ty.fnCallingConvention()),
+                return true;
-            };
+            }
+            return !Type.fnCallingConventionAllowsZigTypes(target, ty.fnCallingConvention());
         },
         .Enum => {
             var buf: Type.Payload.Bits = undefined;

src/codegen/llvm.zig+1-4

 @@ -10350,11 +10350,8 @@ fn toLlvmCallConv(cc: std.builtin.CallingConvention, target: std.Target) llvm.Ca
         .Signal => .AVR_SIGNAL,
         .SysV => .X86_64_SysV,
         .Win64 => .Win64,
-        .PtxKernel => return switch (target.cpu.arch) {
+        .Kernel => return switch (target.cpu.arch) {
             .nvptx, .nvptx64 => .PTX_Kernel,
-            else => unreachable,
-        },
-        .AmdgpuKernel => return switch (target.cpu.arch) {
             .amdgcn => .AMDGPU_KERNEL,
             else => unreachable,
         },

src/link/NvPtx.zig+1-1

...	@@ -1,7 +1,7 @@	...	@@ -1,7 +1,7 @@
1	//! NVidia PTX (Paralle Thread Execution)	1	//! NVidia PTX (Paralle Thread Execution)
2	//! https://docs.nvidia.com/cuda/parallel-thread-execution/index.html	2	//! https://docs.nvidia.com/cuda/parallel-thread-execution/index.html
3	//! For this we rely on the nvptx backend of LLVM	3	//! For this we rely on the nvptx backend of LLVM
4	//! Kernel functions need to be marked both as "export" and "callconv(.PtxKernel)"	4	//! Kernel functions need to be marked both as "export" and "callconv(.Kernel)"
5		5
6	const NvPtx = @This();	6	const NvPtx = @This();
7		7

src/type.zig+5-2

 @@ -4796,9 +4796,12 @@ pub const Type = extern union {
     }
     /// Asserts the type is a function.
-    pub fn fnCallingConventionAllowsZigTypes(cc: std.builtin.CallingConvention) bool {
+    pub fn fnCallingConventionAllowsZigTypes(target: Target, cc: std.builtin.CallingConvention) bool {
         return switch (cc) {
-            .Unspecified, .Async, .Inline, .PtxKernel => true,
+            .Unspecified, .Async, .Inline => true,
+            // For now we want to authorize PTX kernel to use zig objects, even if we end up exposing the ABI.
+            // The goal is to experiment with more integrated CPU/GPU code.
+            .Kernel => target.cpu.arch == .nvptx or target.cpu.arch == .nvptx64,
             else => false,
         };
     }

test/nvptx.zig+4-4

...	@@ -10,7 +10,7 @@ pub fn addCases(ctx: *Cases) !void {	...	@@ -10,7 +10,7 @@ pub fn addCases(ctx: *Cases) !void {
10	\\ return a + b;	10	\\ return a + b;
11	\\}	11	\\}
12	\\	12	\\
13	\\pub export fn add_and_substract(a: i32, out: *i32) callconv(.PtxKernel) void {	13	\\pub export fn add_and_substract(a: i32, out: *i32) callconv(.Kernel) void {
14	\\ const x = add(a, 7);	14	\\ const x = add(a, 7);
15	\\ var y = add(2, 0);	15	\\ var y = add(2, 0);
16	\\ y -= x;	16	\\ y -= x;
...	@@ -29,7 +29,7 @@ pub fn addCases(ctx: *Cases) !void {	...	@@ -29,7 +29,7 @@ pub fn addCases(ctx: *Cases) !void {
29	\\ );	29	\\ );
30	\\}	30	\\}
31	\\	31	\\
32	\\pub export fn special_reg(a: []const i32, out: []i32) callconv(.PtxKernel) void {	32	\\pub export fn special_reg(a: []const i32, out: []i32) callconv(.Kernel) void {
33	\\ const i = threadIdX();	33	\\ const i = threadIdX();
34	\\ out[i] = a[i] + 7;	34	\\ out[i] = a[i] + 7;
35	\\}	35	\\}
...	@@ -42,7 +42,7 @@ pub fn addCases(ctx: *Cases) !void {	...	@@ -42,7 +42,7 @@ pub fn addCases(ctx: *Cases) !void {
42	case.addCompile(	42	case.addCompile(
43	\\var x: i32 addrspace(.global) = 0;	43	\\var x: i32 addrspace(.global) = 0;
44	\\	44	\\
45	\\pub export fn increment(out: *i32) callconv(.PtxKernel) void {	45	\\pub export fn increment(out: *i32) callconv(.Kernel) void {
46	\\ x += 1;	46	\\ x += 1;
47	\\ out.* = x;	47	\\ out.* = x;
48	\\}	48	\\}
...	@@ -59,7 +59,7 @@ pub fn addCases(ctx: *Cases) !void {	...	@@ -59,7 +59,7 @@ pub fn addCases(ctx: *Cases) !void {
59	\\}	59	\\}
60	\\	60	\\
61	\\ var _sdata: [1024]f32 addrspace(.shared) = undefined;	61	\\ var _sdata: [1024]f32 addrspace(.shared) = undefined;
62	\\ pub export fn reduceSum(d_x: []const f32, out: *f32) callconv(.PtxKernel) void {	62	\\ pub export fn reduceSum(d_x: []const f32, out: *f32) callconv(.Kernel) void {
63	\\ var sdata = @addrSpaceCast(.generic, &_sdata);	63	\\ var sdata = @addrSpaceCast(.generic, &_sdata);
64	\\ const tid: u32 = threadIdX();	64	\\ const tid: u32 = threadIdX();
65	\\ var sum = d_x[tid];	65	\\ var sum = d_x[tid];