authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-03-05 18:47:00+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-03-11 20:05:49+01:00
logf14831ec73d7dd87a770f902fb53d1ede486e524
treed97ef54f7d11e3fb5bf96a8acfb627a76187436f
parent817fb263b533f0a24476cabe43a6ee5826113d8d

x86_64: truncate immediates

5 files changed, 114 insertions(+), 45 deletions(-)

src/arch/x86_64/CodeGen.zig+92-17
...@@ -385,6 +385,24 @@ pub fn addExtra(self: *Self, extra: anytype) Allocator.Error!u32 {...@@ -385,6 +385,24 @@ pub fn addExtra(self: *Self, extra: anytype) Allocator.Error!u32 {
385 return self.addExtraAssumeCapacity(extra);385 return self.addExtraAssumeCapacity(extra);
386}386}
387387
388fn extraData(self: *Self, comptime T: type, index: u32) struct { data: T, end: u32 } {
389 const fields = std.meta.fields(T);
390 var i: u32 = index;
391 var result: T = undefined;
392 inline for (fields) |field| {
393 @field(result, field.name) = switch (field.type) {
394 u32 => self.mir_extra.items[i],
395 i32 => @bitCast(i32, self.mir_extra.items[i]),
396 else => @compileError("bad field type"),
397 };
398 i += 1;
399 }
400 return .{
401 .data = result,
402 .end = i,
403 };
404}
405
388pub fn addExtraAssumeCapacity(self: *Self, extra: anytype) u32 {406pub fn addExtraAssumeCapacity(self: *Self, extra: anytype) u32 {
389 const fields = std.meta.fields(@TypeOf(extra));407 const fields = std.meta.fields(@TypeOf(extra));
390 const result = @intCast(u32, self.mir_extra.items.len);408 const result = @intCast(u32, self.mir_extra.items.len);
...@@ -2759,9 +2777,15 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type...@@ -2759,9 +2777,15 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
2759 1, 2, 4 => {2777 1, 2, 4 => {
2760 // TODO this is wasteful!2778 // TODO this is wasteful!
2761 // introduce new MIR tag specifically for mov [reg + 0], imm2779 // introduce new MIR tag specifically for mov [reg + 0], imm
2780 const operand = switch (abi_size) {
2781 1 => @truncate(u8, imm),
2782 2 => @truncate(u16, imm),
2783 4 => @truncate(u32, imm),
2784 else => unreachable,
2785 };
2762 const payload = try self.addExtra(Mir.ImmPair{2786 const payload = try self.addExtra(Mir.ImmPair{
2763 .dest_off = 0,2787 .dest_off = 0,
2764 .operand = @truncate(u32, imm),2788 .operand = operand,
2765 });2789 });
2766 _ = try self.addInst(.{2790 _ = try self.addInst(.{
2767 .tag = .mov_mem_imm,2791 .tag = .mov_mem_imm,
...@@ -2872,10 +2896,17 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type...@@ -2872,10 +2896,17 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
2872 return self.fail("TODO saving imm to memory for abi_size {}", .{abi_size});2896 return self.fail("TODO saving imm to memory for abi_size {}", .{abi_size});
2873 }2897 }
28742898
2899 const operand = switch (abi_size) {
2900 1 => @truncate(u8, imm),
2901 2 => @truncate(u16, imm),
2902 4 => @truncate(u32, imm),
2903 8 => @truncate(u32, imm),
2904 else => unreachable,
2905 };
2875 const payload = try self.addExtra(Mir.ImmPair{2906 const payload = try self.addExtra(Mir.ImmPair{
2876 .dest_off = 0,2907 .dest_off = 0,
2877 // TODO check if this logic is correct2908 // TODO check if this logic is correct
2878 .operand = @truncate(u32, imm),2909 .operand = operand,
2879 });2910 });
2880 const flags: u2 = switch (abi_size) {2911 const flags: u2 = switch (abi_size) {
2881 1 => 0b00,2912 1 => 0b00,
...@@ -3600,7 +3631,13 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu...@@ -3600,7 +3631,13 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
3600 _ = try self.addInst(.{3631 _ = try self.addInst(.{
3601 .tag = mir_tag,3632 .tag = mir_tag,
3602 .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(dst_reg, abi_size) }),3633 .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(dst_reg, abi_size) }),
3603 .data = .{ .imm = @truncate(u32, imm) },3634 .data = .{ .imm = switch (abi_size) {
3635 1 => @truncate(u8, imm),
3636 2 => @truncate(u16, imm),
3637 4 => @truncate(u32, imm),
3638 8 => @truncate(u32, imm),
3639 else => unreachable,
3640 } },
3604 });3641 });
3605 },3642 },
3606 .memory,3643 .memory,
...@@ -3671,9 +3708,16 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu...@@ -3671,9 +3708,16 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
3671 8 => 0b11,3708 8 => 0b11,
3672 else => unreachable,3709 else => unreachable,
3673 };3710 };
3711 const operand = switch (abi_size) {
3712 1 => @truncate(u8, imm),
3713 2 => @truncate(u16, imm),
3714 4 => @truncate(u32, imm),
3715 8 => @truncate(u32, imm),
3716 else => unreachable,
3717 };
3674 const payload = try self.addExtra(Mir.ImmPair{3718 const payload = try self.addExtra(Mir.ImmPair{
3675 .dest_off = -off,3719 .dest_off = -off,
3676 .operand = @truncate(u32, imm),3720 .operand = operand,
3677 });3721 });
3678 _ = try self.addInst(.{3722 _ = try self.addInst(.{
3679 .tag = tag,3723 .tag = tag,
...@@ -4855,7 +4899,13 @@ fn genCondSwitchMir(self: *Self, ty: Type, condition: MCValue, case: MCValue) !u...@@ -4855,7 +4899,13 @@ fn genCondSwitchMir(self: *Self, ty: Type, condition: MCValue, case: MCValue) !u
4855 _ = try self.addInst(.{4899 _ = try self.addInst(.{
4856 .tag = .xor,4900 .tag = .xor,
4857 .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(cond_reg, abi_size) }),4901 .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(cond_reg, abi_size) }),
4858 .data = .{ .imm = @intCast(u32, imm) },4902 .data = .{ .imm = switch (abi_size) {
4903 1 => @truncate(u8, imm),
4904 2 => @truncate(u16, imm),
4905 4 => @truncate(u32, imm),
4906 8 => @truncate(u32, imm),
4907 else => unreachable,
4908 } },
4859 });4909 });
4860 },4910 },
4861 .register => |reg| {4911 .register => |reg| {
...@@ -5366,20 +5416,27 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE...@@ -5366,20 +5416,27 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
5366 // We have a positive stack offset value but we want a twos complement negative5416 // We have a positive stack offset value but we want a twos complement negative
5367 // offset from rbp, which is at the top of the stack frame.5417 // offset from rbp, which is at the top of the stack frame.
5368 // mov [rbp+offset], immediate5418 // mov [rbp+offset], immediate
5419 const operand = switch (abi_size) {
5420 1 => @truncate(u8, imm),
5421 2 => @truncate(u16, imm),
5422 4 => @truncate(u32, imm),
5423 else => unreachable,
5424 };
5425 const flags: u2 = switch (abi_size) {
5426 1 => 0b00,
5427 2 => 0b01,
5428 4 => 0b10,
5429 else => unreachable,
5430 };
5369 const payload = try self.addExtra(Mir.ImmPair{5431 const payload = try self.addExtra(Mir.ImmPair{
5370 .dest_off = -stack_offset,5432 .dest_off = -stack_offset,
5371 .operand = @truncate(u32, imm),5433 .operand = operand,
5372 });5434 });
5373 _ = try self.addInst(.{5435 _ = try self.addInst(.{
5374 .tag = .mov_mem_imm,5436 .tag = .mov_mem_imm,
5375 .ops = Mir.Inst.Ops.encode(.{5437 .ops = Mir.Inst.Ops.encode(.{
5376 .reg1 = .rsp,5438 .reg1 = .rsp,
5377 .flags = switch (abi_size) {5439 .flags = flags,
5378 1 => 0b00,
5379 2 => 0b01,
5380 4 => 0b10,
5381 else => unreachable,
5382 },
5383 }),5440 }),
5384 .data = .{ .payload = payload },5441 .data = .{ .payload = payload },
5385 });5442 });
...@@ -5518,7 +5575,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl...@@ -5518,7 +5575,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
5518 assert(ty.isError());5575 assert(ty.isError());
5519 const payload = try self.addExtra(Mir.ImmPair{5576 const payload = try self.addExtra(Mir.ImmPair{
5520 .dest_off = -stack_offset,5577 .dest_off = -stack_offset,
5521 .operand = @truncate(u32, x_big),5578 .operand = @truncate(u8, x_big),
5522 });5579 });
5523 _ = try self.addInst(.{5580 _ = try self.addInst(.{
5524 .tag = .mov_mem_imm,5581 .tag = .mov_mem_imm,
...@@ -5530,9 +5587,15 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl...@@ -5530,9 +5587,15 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
5530 });5587 });
5531 },5588 },
5532 1, 2, 4 => {5589 1, 2, 4 => {
5590 const operand = switch (abi_size) {
5591 1 => @truncate(u8, x_big),
5592 2 => @truncate(u16, x_big),
5593 4 => @truncate(u32, x_big),
5594 else => unreachable,
5595 };
5533 const payload = try self.addExtra(Mir.ImmPair{5596 const payload = try self.addExtra(Mir.ImmPair{
5534 .dest_off = -stack_offset,5597 .dest_off = -stack_offset,
5535 .operand = @truncate(u32, x_big),5598 .operand = operand,
5536 });5599 });
5537 _ = try self.addInst(.{5600 _ = try self.addInst(.{
5538 .tag = .mov_mem_imm,5601 .tag = .mov_mem_imm,
...@@ -5932,7 +5995,7 @@ fn genInlineMemset(...@@ -5932,7 +5995,7 @@ fn genInlineMemset(
5932 const loop_start = try self.addInst(.{5995 const loop_start = try self.addInst(.{
5933 .tag = .cmp,5996 .tag = .cmp,
5934 .ops = Mir.Inst.Ops.encode(.{ .reg1 = index_reg }),5997 .ops = Mir.Inst.Ops.encode(.{ .reg1 = index_reg }),
5935 .data = .{ .imm = @bitCast(u32, @as(i32, -1)) },5998 .data = .{ .imm = @bitCast(u8, @as(i8, -1)) },
5936 });5999 });
59376000
5938 // je end6001 // je end
...@@ -6037,7 +6100,13 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -6037,7 +6100,13 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
6037 _ = try self.addInst(.{6100 _ = try self.addInst(.{
6038 .tag = .mov,6101 .tag = .mov,
6039 .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(reg, abi_size) }),6102 .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(reg, abi_size) }),
6040 .data = .{ .imm = @truncate(u32, x) },6103 .data = .{ .imm = switch (abi_size) {
6104 1 => @truncate(u8, x),
6105 2 => @truncate(u16, x),
6106 4 => @truncate(u32, x),
6107 8 => @truncate(u32, x),
6108 else => unreachable,
6109 } },
6041 });6110 });
6042 return;6111 return;
6043 }6112 }
...@@ -6204,7 +6273,13 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -6204,7 +6273,13 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
6204 .reg1 = registerAlias(reg, abi_size),6273 .reg1 = registerAlias(reg, abi_size),
6205 .flags = 0b01,6274 .flags = 0b01,
6206 }),6275 }),
6207 .data = .{ .imm = @truncate(u32, x) },6276 .data = .{ .imm = switch (abi_size) {
6277 1 => @truncate(u8, x),
6278 2 => @truncate(u16, x),
6279 4 => @truncate(u32, x),
6280 8 => @truncate(u32, x),
6281 else => unreachable,
6282 } },
6208 });6283 });
6209 } else {6284 } else {
6210 // If this is RAX, we can use a direct load.6285 // If this is RAX, we can use a direct load.
src/arch/x86_64/Emit.zig+8-8
...@@ -236,12 +236,12 @@ fn encode(emit: *Emit, mnemonic: Instruction.Mnemonic, ops: struct {...@@ -236,12 +236,12 @@ fn encode(emit: *Emit, mnemonic: Instruction.Mnemonic, ops: struct {
236 op3: Instruction.Operand = .none,236 op3: Instruction.Operand = .none,
237 op4: Instruction.Operand = .none,237 op4: Instruction.Operand = .none,
238}) InnerError!void {238}) InnerError!void {
239 const inst = try Instruction.new(mnemonic, .{239 const inst = Instruction.new(mnemonic, .{
240 .op1 = ops.op1,240 .op1 = ops.op1,
241 .op2 = ops.op2,241 .op2 = ops.op2,
242 .op3 = ops.op3,242 .op3 = ops.op3,
243 .op4 = ops.op4,243 .op4 = ops.op4,
244 });244 }) catch unreachable;
245 return inst.encode(emit.code.writer());245 return inst.encode(emit.code.writer());
246}246}
247247
...@@ -624,7 +624,7 @@ fn mirArithScaleSrc(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst....@@ -624,7 +624,7 @@ fn mirArithScaleSrc(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst.
624 const payload = emit.mir.instructions.items(.data)[inst].payload;624 const payload = emit.mir.instructions.items(.data)[inst].payload;
625 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();625 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();
626 const scale_index = Memory.ScaleIndex{626 const scale_index = Memory.ScaleIndex{
627 .scale = scale,627 .scale = @as(u4, 1) << scale,
628 .index = index_reg_disp.index,628 .index = index_reg_disp.index,
629 };629 };
630 return emit.encode(mnemonic, .{630 return emit.encode(mnemonic, .{
...@@ -643,7 +643,7 @@ fn mirArithScaleDst(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst....@@ -643,7 +643,7 @@ fn mirArithScaleDst(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst.
643 const payload = emit.mir.instructions.items(.data)[inst].payload;643 const payload = emit.mir.instructions.items(.data)[inst].payload;
644 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();644 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();
645 const scale_index = Memory.ScaleIndex{645 const scale_index = Memory.ScaleIndex{
646 .scale = scale,646 .scale = @as(u4, 1) << scale,
647 .index = index_reg_disp.index,647 .index = index_reg_disp.index,
648 };648 };
649 assert(ops.reg2 != .none);649 assert(ops.reg2 != .none);
...@@ -663,7 +663,7 @@ fn mirArithScaleImm(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst....@@ -663,7 +663,7 @@ fn mirArithScaleImm(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst.
663 const payload = emit.mir.instructions.items(.data)[inst].payload;663 const payload = emit.mir.instructions.items(.data)[inst].payload;
664 const index_reg_disp_imm = emit.mir.extraData(Mir.IndexRegisterDispImm, payload).data.decode();664 const index_reg_disp_imm = emit.mir.extraData(Mir.IndexRegisterDispImm, payload).data.decode();
665 const scale_index = Memory.ScaleIndex{665 const scale_index = Memory.ScaleIndex{
666 .scale = scale,666 .scale = @as(u4, 1) << scale,
667 .index = index_reg_disp_imm.index,667 .index = index_reg_disp_imm.index,
668 };668 };
669 return emit.encode(mnemonic, .{669 return emit.encode(mnemonic, .{
...@@ -688,7 +688,7 @@ fn mirArithMemIndexImm(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.In...@@ -688,7 +688,7 @@ fn mirArithMemIndexImm(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.In
688 0b11 => .qword,688 0b11 => .qword,
689 };689 };
690 const scale_index = Memory.ScaleIndex{690 const scale_index = Memory.ScaleIndex{
691 .scale = 0,691 .scale = 1,
692 .index = index_reg_disp_imm.index,692 .index = index_reg_disp_imm.index,
693 };693 };
694 return emit.encode(mnemonic, .{694 return emit.encode(mnemonic, .{
...@@ -777,7 +777,7 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {...@@ -777,7 +777,7 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
777 } else emit.mir.instructions.items(.data)[inst].imm;777 } else emit.mir.instructions.items(.data)[inst].imm;
778 return emit.encode(.mov, .{778 return emit.encode(.mov, .{
779 .op1 = .{ .reg = ops.reg1 },779 .op1 = .{ .reg = ops.reg1 },
780 .op2 = .{ .imm = @bitCast(i64, imm) },780 .op2 = .{ .imm = imm },
781 });781 });
782 },782 },
783 0b01 => {783 0b01 => {
...@@ -983,7 +983,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {...@@ -983,7 +983,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
983 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();983 const index_reg_disp = emit.mir.extraData(Mir.IndexRegisterDisp, payload).data.decode();
984 const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;984 const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;
985 const scale_index = Memory.ScaleIndex{985 const scale_index = Memory.ScaleIndex{
986 .scale = 0,986 .scale = 1,
987 .index = index_reg_disp.index,987 .index = index_reg_disp.index,
988 };988 };
989 return emit.encode(.lea, .{989 return emit.encode(.lea, .{
src/arch/x86_64/Encoding.zig+3-3
...@@ -390,9 +390,9 @@ pub const Op = enum {...@@ -390,9 +390,9 @@ pub const Op = enum {
390390
391 .imm => |imm| {391 .imm => |imm| {
392 if (imm == 1) return .unity;392 if (imm == 1) return .unity;
393 if (math.cast(i8, imm)) |_| return .imm8;393 if (math.cast(u8, imm)) |_| return .imm8;
394 if (math.cast(i16, imm)) |_| return .imm16;394 if (math.cast(u16, imm)) |_| return .imm16;
395 if (math.cast(i32, imm)) |_| return .imm32;395 if (math.cast(u32, imm)) |_| return .imm32;
396 return .imm64;396 return .imm64;
397 },397 },
398 }398 }
src/arch/x86_64/Mir.zig+2-2
...@@ -594,9 +594,9 @@ pub fn deinit(mir: *Mir, gpa: std.mem.Allocator) void {...@@ -594,9 +594,9 @@ pub fn deinit(mir: *Mir, gpa: std.mem.Allocator) void {
594 mir.* = undefined;594 mir.* = undefined;
595}595}
596596
597pub fn extraData(mir: Mir, comptime T: type, index: usize) struct { data: T, end: usize } {597pub fn extraData(mir: Mir, comptime T: type, index: u32) struct { data: T, end: u32 } {
598 const fields = std.meta.fields(T);598 const fields = std.meta.fields(T);
599 var i: usize = index;599 var i: u32 = index;
600 var result: T = undefined;600 var result: T = undefined;
601 inline for (fields) |field| {601 inline for (fields) |field| {
602 @field(result, field.name) = switch (field.type) {602 @field(result, field.name) = switch (field.type) {
src/arch/x86_64/encoder.zig+9-15
...@@ -22,7 +22,7 @@ pub const Instruction = struct {...@@ -22,7 +22,7 @@ pub const Instruction = struct {
22 none,22 none,
23 reg: Register,23 reg: Register,
24 mem: Memory,24 mem: Memory,
25 imm: i64,25 imm: u64,
2626
27 /// Returns the bitsize of the operand.27 /// Returns the bitsize of the operand.
28 /// Asserts the operand is either register or memory.28 /// Asserts the operand is either register or memory.
...@@ -47,6 +47,7 @@ pub const Instruction = struct {...@@ -47,6 +47,7 @@ pub const Instruction = struct {
47 }47 }
4848
49 pub fn fmtPrint(op: Operand, enc_op: Encoding.Op, writer: anytype) !void {49 pub fn fmtPrint(op: Operand, enc_op: Encoding.Op, writer: anytype) !void {
50 _ = enc_op;
50 switch (op) {51 switch (op) {
51 .none => {},52 .none => {},
52 .reg => |reg| try writer.writeAll(@tagName(reg)),53 .reg => |reg| try writer.writeAll(@tagName(reg)),
...@@ -92,14 +93,7 @@ pub const Instruction = struct {...@@ -92,14 +93,7 @@ pub const Instruction = struct {
92 .moffs => |moffs| try writer.print("{s}:0x{x}", .{ @tagName(moffs.seg), moffs.offset }),93 .moffs => |moffs| try writer.print("{s}:0x{x}", .{ @tagName(moffs.seg), moffs.offset }),
93 },94 },
94 .imm => |imm| {95 .imm => |imm| {
95 if (enc_op == .imm64) {96 try writer.print("0x{x}", .{imm});
96 return writer.print("0x{x}", .{@bitCast(u64, imm)});
97 }
98 const imm_abs = try std.math.absInt(imm);
99 if (sign(imm) < 0) {
100 try writer.writeByte('-');
101 }
102 try writer.print("0x{x}", .{imm_abs});
103 },97 },
104 }98 }
105 }99 }
...@@ -117,7 +111,7 @@ pub const Instruction = struct {...@@ -117,7 +111,7 @@ pub const Instruction = struct {
117 .op3 = args.op3,111 .op3 = args.op3,
118 .op4 = args.op4,112 .op4 = args.op4,
119 }) orelse return error.InvalidInstruction;113 }) orelse return error.InvalidInstruction;
120 std.log.debug("{}", .{encoding});114 std.log.warn("{}", .{encoding});
121 return .{115 return .{
122 .op1 = args.op1,116 .op1 = args.op1,
123 .op2 = args.op2,117 .op2 = args.op2,
...@@ -386,12 +380,12 @@ pub const Instruction = struct {...@@ -386,12 +380,12 @@ pub const Instruction = struct {
386 }380 }
387 }381 }
388382
389 fn encodeImm(imm: i64, kind: Encoding.Op, encoder: anytype) !void {383 fn encodeImm(imm: u64, kind: Encoding.Op, encoder: anytype) !void {
390 switch (kind) {384 switch (kind) {
391 .imm8, .rel8 => try encoder.imm8(@truncate(i8, imm)),385 .imm8, .rel8 => try encoder.imm8(@bitCast(i8, @truncate(u8, imm))),
392 .imm16, .rel16 => try encoder.imm16(@truncate(i16, imm)),386 .imm16, .rel16 => try encoder.imm16(@bitCast(i16, @truncate(u16, imm))),
393 .imm32, .rel32 => try encoder.imm32(@truncate(i32, imm)),387 .imm32, .rel32 => try encoder.imm32(@bitCast(i32, @truncate(u32, imm))),
394 .imm64 => try encoder.imm64(@bitCast(u64, imm)),388 .imm64 => try encoder.imm64(imm),
395 else => unreachable,389 else => unreachable,
396 }390 }
397 }391 }