Commit f42133aba77c81e02968e58d7bf75706eab0ec5b | zig

author	Alex Rønne Petersen <alex@alexrp.com> 2026-08-03 12:13:28+02:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2026-09-05 14:54:30+02:00
log	f42133aba77c81e02968e58d7bf75706eab0ec5b
tree	282c2f4b14156e51e315b20c1b51c7c10410deb5
parent	ef21dc825f0a5bb514a7d1294faff319c51e66db
signature	Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

zig cc: update intrinsic headers to LLVM 23

56 files changed, 7420 insertions(+), 4457 deletions(-)

lib/include/__clang_spirv_libdevice_declares.h created+170

...	...	@@ -0,0 +1,170 @@
	1	/*===-- __clang_spirv_libdevice_declares.h - decls for libdevice functions --===
	2	*
	3	* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	4	* See https://llvm.org/LICENSE.txt for license information.
	5	* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	6	*
	7	*===-----------------------------------------------------------------------===
	8	*/
	9
	10	#ifndef __CLANG_SPIRV_LIBDEVICE_DECLARES_H__
	11	#define __CLANG_SPIRV_LIBDEVICE_DECLARES_H__
	12
	13	#if defined(__cplusplus)
	14	extern "C" {
	15	#else
	16	_Pragma("push_macro(\"bool\")");
	17	#define bool _Bool
	18	#endif
	19
	20	#define _CLC_OVERLOAD [[clang::overloadable]]
	21	#define _CLC_CONSTFN [[gnu::const]]
	22	// TODO: Add vector versions of the API in case it is required.
	23	_CLC_OVERLOAD _CLC_CONSTFN unsigned int __spirv_ocl_s_abs(int);
	24	_CLC_OVERLOAD _CLC_CONSTFN unsigned long __spirv_ocl_s_abs(long);
	25	_CLC_OVERLOAD _CLC_CONSTFN unsigned long long __spirv_ocl_s_abs(long long);
	26	_CLC_OVERLOAD _CLC_CONSTFN int __spirv_ocl_s_max(int, int);
	27	_CLC_OVERLOAD _CLC_CONSTFN long __spirv_ocl_s_max(long, long);
	28	_CLC_OVERLOAD _CLC_CONSTFN long long __spirv_ocl_s_max(long long, long long);
	29	_CLC_OVERLOAD _CLC_CONSTFN int __spirv_ocl_s_min(int, int);
	30	_CLC_OVERLOAD _CLC_CONSTFN long __spirv_ocl_s_min(long, long);
	31	_CLC_OVERLOAD _CLC_CONSTFN long long __spirv_ocl_s_min(long long, long long);
	32	_CLC_OVERLOAD _CLC_CONSTFN unsigned int __spirv_ocl_u_max(unsigned int,
	33	unsigned int);
	34	_CLC_OVERLOAD _CLC_CONSTFN unsigned long __spirv_ocl_u_max(unsigned long,
	35	unsigned long);
	36	_CLC_OVERLOAD _CLC_CONSTFN unsigned long long
	37	__spirv_ocl_u_max(unsigned long long, unsigned long long);
	38	_CLC_OVERLOAD _CLC_CONSTFN unsigned int __spirv_ocl_u_min(unsigned int,
	39	unsigned int);
	40	_CLC_OVERLOAD _CLC_CONSTFN unsigned long __spirv_ocl_u_min(unsigned long,
	41	unsigned long);
	42	_CLC_OVERLOAD _CLC_CONSTFN unsigned long long
	43	__spirv_ocl_u_min(unsigned long long, unsigned long long);
	44	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_acos(float);
	45	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_acos(double);
	46	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_acosh(float);
	47	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_acosh(double);
	48	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_asin(float);
	49	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_asin(double);
	50	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_asinh(float);
	51	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_asinh(double);
	52	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_atan(float);
	53	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_atan(double);
	54	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_atan2(float, float);
	55	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_atan2(double, double);
	56	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_atanh(float);
	57	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_atanh(double);
	58	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_cbrt(float);
	59	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_cbrt(double);
	60	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_ceil(float);
	61	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_ceil(double);
	62	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_cos(float);
	63	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_cos(double);
	64	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_cosh(float);
	65	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_cosh(double);
	66	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_cospi(float);
	67	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_cospi(double);
	68	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_erf(float);
	69	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_erf(double);
	70	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_erfc(float);
	71	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_erfc(double);
	72	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_exp(float);
	73	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_exp(double);
	74	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_exp2(float);
	75	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_exp2(double);
	76	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_exp10(float);
	77	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_exp10(double);
	78	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_expm1(float);
	79	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_expm1(double);
	80	_CLC_OVERLOAD _CLC_CONSTFN bool __spirv_IsNan(float);
	81	_CLC_OVERLOAD _CLC_CONSTFN bool __spirv_IsNan(double);
	82	_CLC_OVERLOAD _CLC_CONSTFN bool __spirv_IsInf(float);
	83	_CLC_OVERLOAD _CLC_CONSTFN bool __spirv_IsInf(double);
	84	_CLC_OVERLOAD _CLC_CONSTFN bool __spirv_IsFinite(float);
	85	_CLC_OVERLOAD _CLC_CONSTFN bool __spirv_IsFinite(double);
	86	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_copysign(float, float);
	87	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_copysign(double, double);
	88	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_ldexp(float, int);
	89	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_ldexp(double, int);
	90	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fabs(float);
	91	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fabs(double);
	92	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_logb(float);
	93	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_logb(double);
	94	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fmax(float, float);
	95	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fmax(double, double);
	96	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fmin(float, float);
	97	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fmin(double, double);
	98	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fdim(float, float);
	99	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fdim(double, double);
	100	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_floor(float);
	101	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_floor(double);
	102	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fma(float, float, float);
	103	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fma(double, double, double);
	104	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fmod(float, float);
	105	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fmod(double, double);
	106	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_frexp(float, int *);
	107	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_frexp(double, int *);
	108	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_hypot(float, float);
	109	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_hypot(double, double);
	110	_CLC_OVERLOAD _CLC_CONSTFN int __spirv_ocl_ilogb(float);
	111	_CLC_OVERLOAD _CLC_CONSTFN int __spirv_ocl_ilogb(double);
	112	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_lgamma(float);
	113	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_lgamma(double);
	114	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_round(float);
	115	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_round(double);
	116	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_log(float);
	117	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_log(double);
	118	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_log10(float);
	119	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_log10(double);
	120	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_log1p(float);
	121	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_log1p(double);
	122	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_log2(float);
	123	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_log2(double);
	124	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_modf(float, float *);
	125	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_modf(double, double *);
	126	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_nan(int);
	127	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_nan(unsigned int);
	128	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_nan(long);
	129	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_nan(unsigned long);
	130	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_nextafter(float, float);
	131	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_nextafter(double, double);
	132	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_sqrt(float);
	133	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_sqrt(double);
	134	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_rsqrt(float);
	135	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_rsqrt(double);
	136	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_pow(float, float);
	137	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_pow(double, double);
	138	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_pown(float, int);
	139	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_pown(double, int);
	140	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_remainder(float, float);
	141	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_remainder(double, double);
	142	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_remquo(float, float, int *);
	143	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_remquo(double, double, int *);
	144	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_sin(float);
	145	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_sin(double);
	146	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_sincos(float, float *);
	147	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_sincos(double, double *);
	148	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_sinh(float);
	149	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_sinh(double);
	150	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_sinpi(float);
	151	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_sinpi(double);
	152	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_tan(float);
	153	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_tan(double);
	154	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_tanh(float);
	155	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_tanh(double);
	156	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_tgamma(float);
	157	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_tgamma(double);
	158	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_trunc(float);
	159	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_trunc(double);
	160	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_rint(float);
	161	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_rint(double);
	162	_CLC_OVERLOAD _CLC_CONSTFN float __spirv_ocl_fclamp(float, float, float);
	163	_CLC_OVERLOAD _CLC_CONSTFN double __spirv_ocl_fclamp(double, double, double);
	164
	165	#if defined(__cplusplus)
	166	} // extern "C"
	167	#else
	168	_Pragma("pop_macro(\"bool\")");
	169	#endif
	170	#endif // __CLANG_SPIRV_LIBDEVICE_DECLARES_H__

lib/include/__clang_spirv_math.h created+719

...	...	@@ -0,0 +1,719 @@
	1	/*===---- __clang_spirv_math.h - Device-side SPIRV math support ------------===
	2	*
	3	* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	4	* See https://llvm.org/LICENSE.txt for license information.
	5	* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	6	*
	7	*===-----------------------------------------------------------------------===
	8	*/
	9	#ifndef __CLANG_SPIRV_MATH_H__
	10	#define __CLANG_SPIRV_MATH_H__
	11
	12	#if !defined(__SPIRV__) && !defined(__OPENMP_SPIRV__)
	13	#error "This file is for SPIRV and OpenMP SPIRV device compilation only."
	14	#endif
	15
	16	// The __CLANG_GPU_DISABLE_MATH_WRAPPERS macro provides a way to let standard
	17	// libcalls reach the link step instead of being eagerly replaced.
	18	#ifndef __CLANG_GPU_DISABLE_MATH_WRAPPERS
	19
	20	// __DEVICE__ is a helper macro with common set of attributes for the wrappers
	21	// we implement in this file. We need static in order to avoid emitting unused
	22	// functions and __forceinline__ helps inlining these wrappers at -O1.
	23	#pragma push_macro("__DEVICE__")
	24	#ifdef __OPENMP_SPIRV__
	25	#if defined(__cplusplus)
	26	#define __DEVICE__ static constexpr __attribute__((always_inline, nothrow))
	27	#else
	28	#define __DEVICE__ static __attribute__((always_inline, nothrow))
	29	#endif
	30	#else
	31	#define __DEVICE__ static __device__ __forceinline__
	32	#endif
	33
	34	__DEVICE__
	35	float __cosf(float __x) { return __spirv_ocl_cos(__x); }
	36	__DEVICE__
	37	float __exp10f(float __x) { return __spirv_ocl_exp10(__x); }
	38	__DEVICE__
	39	float __expf(float __x) { return __spirv_ocl_exp(__x); }
	40
	41	__DEVICE__
	42	float __fadd_rd(float __x, float __y) {
	43	float sum = __x + __y;
	44	float rounded = __spirv_ocl_floor(sum);
	45	if (rounded > sum)
	46	rounded -= 1.0f;
	47	return rounded;
	48	}
	49
	50	__DEVICE__
	51	float __fadd_rn(float __x, float __y) { return __spirv_ocl_rint(__x + __y); }
	52	__DEVICE__
	53	float __fadd_ru(float __x, float __y) { return __spirv_ocl_ceil(__x + __y); }
	54	__DEVICE__
	55	float __fadd_rz(float __x, float __y) { return __spirv_ocl_trunc(__x + __y); }
	56
	57	__DEVICE__
	58	float __fdiv_rd(float __x, float __y) {
	59	float res = __x / __y;
	60	float rounded = __spirv_ocl_floor(res);
	61	if (rounded > res)
	62	rounded -= 1.0f;
	63	return rounded;
	64	}
	65	__DEVICE__
	66	float __fdiv_rn(float __x, float __y) { return __spirv_ocl_rint(__x / __y); }
	67	__DEVICE__
	68	float __fdiv_ru(float __x, float __y) { return __spirv_ocl_ceil(__x / __y); }
	69	__DEVICE__
	70	float __fdiv_rz(float __x, float __y) { return __spirv_ocl_trunc(__x / __y); }
	71	__DEVICE__
	72	float __fdividef(float __x, float __y) { return __x / __y; }
	73
	74	__DEVICE__
	75	float __fmaf_rd(float __x, float __y, float __z) {
	76	float res = __x * __y + __z;
	77	float rounded = __spirv_ocl_floor(res);
	78	if (rounded > res)
	79	rounded -= 1.0f;
	80	return rounded;
	81	}
	82	__DEVICE__
	83	float __fmaf_rn(float __x, float __y, float __z) {
	84	return __spirv_ocl_rint(__x * __y + __z);
	85	}
	86	__DEVICE__
	87	float __fmaf_ru(float __x, float __y, float __z) {
	88	return __spirv_ocl_ceil(__x * __y + __z);
	89	}
	90	__DEVICE__
	91	float __fmaf_rz(float __x, float __y, float __z) {
	92	return __spirv_ocl_trunc(__x * __y + __z);
	93	}
	94
	95	__DEVICE__
	96	float __fmul_rd(float __x, float __y) {
	97	float res = __x * __y;
	98	float rounded = __spirv_ocl_floor(res);
	99	if (rounded > res)
	100	rounded -= 1.0f;
	101	return rounded;
	102	}
	103	__DEVICE__
	104	float __fmul_rn(float __x, float __y) { return __spirv_ocl_rint(__x * __y); }
	105	__DEVICE__
	106	float __fmul_ru(float __x, float __y) { return __spirv_ocl_ceil(__x * __y); }
	107	__DEVICE__
	108	float __fmul_rz(float __x, float __y) { return __spirv_ocl_trunc(__x * __y); }
	109
	110	__DEVICE__
	111	float __frcp_rd(float __x) { return __fdiv_rd(1.0f, __x); }
	112	__DEVICE__
	113	float __frcp_rn(float __x) { return __fdiv_rn(1.0f, __x); }
	114	__DEVICE__
	115	float __frcp_ru(float __x) { return __fdiv_ru(1.0f, __x); }
	116	__DEVICE__
	117	float __frcp_rz(float __x) { return __fdiv_rz(1.0f, __x); }
	118	__DEVICE__
	119
	120	float __frsqrt_rn(float __x) {
	121	return __spirv_ocl_rint(__spirv_ocl_rsqrt(__x));
	122	}
	123
	124	__DEVICE__
	125	float __fsqrt_rd(float __x) {
	126	float res = __spirv_ocl_sqrt(__x);
	127	float rounded = __spirv_ocl_floor(res);
	128	if (rounded > res)
	129	rounded -= 1.0f;
	130	return rounded;
	131	}
	132	__DEVICE__
	133	float __fsqrt_rn(float __x) { return __spirv_ocl_rint(__spirv_ocl_sqrt(__x)); }
	134	__DEVICE__
	135	float __fsqrt_ru(float __x) { return __spirv_ocl_ceil(__spirv_ocl_sqrt(__x)); }
	136	__DEVICE__
	137	float __fsqrt_rz(float __x) { return __spirv_ocl_trunc(__spirv_ocl_sqrt(__x)); }
	138
	139	__DEVICE__
	140	float __fsub_rd(float __x, float __y) {
	141	float res = __x - __y;
	142	float rounded = __spirv_ocl_floor(res);
	143	if (rounded > res)
	144	rounded -= 1.0f;
	145	return rounded;
	146	}
	147	__DEVICE__
	148	float __fsub_rn(float __x, float __y) { return __spirv_ocl_rint(__x - __y); }
	149	__DEVICE__
	150	float __fsub_ru(float __x, float __y) { return __spirv_ocl_ceil(__x - __y); }
	151	__DEVICE__
	152	float __fsub_rz(float __x, float __y) { return __spirv_ocl_trunc(__x - __y); }
	153	__DEVICE__
	154	float __log10f(float __x) { return __spirv_ocl_log10(__x); }
	155	__DEVICE__
	156	float __log2f(float __x) { return __spirv_ocl_log2(__x); }
	157	__DEVICE__
	158	float __logf(float __x) { return __spirv_ocl_log(__x); }
	159	__DEVICE__
	160	float __powf(float __x, float __y) { return __spirv_ocl_pow(__x, __y); }
	161
	162	__DEVICE__
	163	float __saturatef(float __x) { return __spirv_ocl_fclamp(__x, 0.0f, 1.0f); }
	164
	165	__DEVICE__
	166	void __sincosf(float __x, float __sinptr, float __cosptr) {
	167	*__sinptr = __spirv_ocl_sincos(__x, __cosptr);
	168	}
	169
	170	__DEVICE__
	171	float __sinf(float __x) { return __spirv_ocl_sin(__x); }
	172
	173	__DEVICE__
	174	float __tanf(float __x) { return __spirv_ocl_tan(__x); }
	175
	176	__DEVICE__
	177	int __finitef(float __x) { return !__spirv_IsInf(__x) && !__spirv_IsNan(__x); }
	178	__DEVICE__
	179	int __isinff(float __x) { return __spirv_IsInf(__x); }
	180	__DEVICE__
	181	int __isnanf(float __x) { return __spirv_IsNan(__x); }
	182	__DEVICE__
	183	int __signbitf(float __x) { return __builtin_signbitf(__x); }
	184
	185	__DEVICE__
	186	int __finite(double __x) { return !__spirv_IsInf(__x) && !__spirv_IsNan(__x); }
	187
	188	__DEVICE__
	189	int __isinf(double __x) { return __spirv_IsInf(__x); }
	190
	191	__DEVICE__
	192	int __isnan(double __x) { return __spirv_IsNan(__x); }
	193	__DEVICE__
	194	int __signbit(double __x) { return __builtin_signbit(__x); }
	195
	196	__DEVICE__
	197	double __dadd_rd(double __x, double __y) {
	198	double sum = __x + __y;
	199	double rounded = __spirv_ocl_floor(sum);
	200	if (rounded > sum)
	201	rounded -= 1.0;
	202	return rounded;
	203	}
	204	__DEVICE__
	205	double __dadd_rn(double __x, double __y) { return __spirv_ocl_rint(__x + __y); }
	206	__DEVICE__
	207	double __dadd_ru(double __x, double __y) { return __spirv_ocl_ceil(__x + __y); }
	208	__DEVICE__
	209	double __dadd_rz(double __x, double __y) {
	210	return __spirv_ocl_trunc(__x + __y);
	211	}
	212	__DEVICE__
	213	double __ddiv_rd(double __x, double __y) {
	214	double res = __x / __y;
	215	double rounded = __spirv_ocl_floor(res);
	216	if (rounded > res)
	217	rounded -= 1.0;
	218	return rounded;
	219	}
	220	__DEVICE__
	221	double __ddiv_rn(double __x, double __y) { return __spirv_ocl_rint(__x / __y); }
	222	__DEVICE__
	223	double __ddiv_ru(double __x, double __y) { return __spirv_ocl_ceil(__x / __y); }
	224	__DEVICE__
	225	double __ddiv_rz(double __x, double __y) {
	226	return __spirv_ocl_trunc(__x / __y);
	227	}
	228
	229	__DEVICE__
	230	double __dmul_rd(double __x, double __y) {
	231	double res = __x * __y;
	232	double rounded = __spirv_ocl_floor(res);
	233	if (rounded > res)
	234	rounded -= 1.0;
	235	return rounded;
	236	}
	237	__DEVICE__
	238	double __dmul_rn(double __x, double __y) { return __spirv_ocl_rint(__x * __y); }
	239	__DEVICE__
	240	double __dmul_ru(double __x, double __y) { return __spirv_ocl_ceil(__x * __y); }
	241	__DEVICE__
	242	double __dmul_rz(double __x, double __y) {
	243	return __spirv_ocl_trunc(__x * __y);
	244	}
	245
	246	__DEVICE__
	247	double __drcp_rd(double __x) { return __ddiv_rd(1.0, __x); }
	248	__DEVICE__
	249	double __drcp_rn(double __x) { return __ddiv_rn(1.0, __x); }
	250	__DEVICE__
	251	double __drcp_ru(double __x) { return __ddiv_ru(1.0, __x); }
	252	__DEVICE__
	253	double __drcp_rz(double __x) { return __ddiv_rz(1.0, __x); }
	254
	255	__DEVICE__
	256	double __dsqrt_rd(double __x) {
	257	double res = __spirv_ocl_sqrt(__x);
	258	double rounded = __spirv_ocl_floor(res);
	259	if (rounded > res)
	260	rounded -= 1.0;
	261	return rounded;
	262	}
	263	__DEVICE__
	264	double __dsqrt_rn(double __x) {
	265	return __spirv_ocl_rint(__spirv_ocl_sqrt(__x));
	266	}
	267	__DEVICE__
	268	double __dsqrt_ru(double __x) {
	269	return __spirv_ocl_ceil(__spirv_ocl_sqrt(__x));
	270	}
	271	__DEVICE__
	272	double __dsqrt_rz(double __x) {
	273	return __spirv_ocl_trunc(__spirv_ocl_sqrt(__x));
	274	}
	275
	276	__DEVICE__
	277	double __dsub_rd(double __x, double __y) {
	278	double res = __x - __y;
	279	double rounded = __spirv_ocl_floor(res);
	280	if (rounded > res)
	281	rounded -= 1.0;
	282	return rounded;
	283	}
	284	__DEVICE__
	285	double __dsub_rn(double __x, double __y) { return __spirv_ocl_rint(__x - __y); }
	286	__DEVICE__
	287	double __dsub_ru(double __x, double __y) { return __spirv_ocl_ceil(__x - __y); }
	288	__DEVICE__
	289	double __dsub_rz(double __x, double __y) {
	290	return __spirv_ocl_trunc(__x - __y);
	291	}
	292
	293	__DEVICE__
	294	double __fma_rd(double __x, double __y, double __z) {
	295	double res = __x * __y + __z;
	296	double rounded = __spirv_ocl_floor(res);
	297	if (rounded > res)
	298	rounded -= 1.0;
	299	return rounded;
	300	}
	301	__DEVICE__
	302	double __fma_rn(double __x, double __y, double __z) {
	303	return __spirv_ocl_rint(__x * __y + __z);
	304	}
	305	__DEVICE__
	306	double __fma_ru(double __x, double __y, double __z) {
	307	return __spirv_ocl_ceil(__x * __y + __z);
	308	}
	309	__DEVICE__
	310	double __fma_rz(double __x, double __y, double __z) {
	311	return __spirv_ocl_trunc(__x * __y + __z);
	312	}
	313
	314	__DEVICE__ int abs(int __a) { return __spirv_ocl_s_abs(__a); }
	315	__DEVICE__ double fabs(double __a) { return __spirv_ocl_fabs(__a); }
	316	__DEVICE__ double acos(double __a) { return __spirv_ocl_acos(__a); }
	317	__DEVICE__ float acosf(float __a) { return __spirv_ocl_acos(__a); }
	318	__DEVICE__ double acosh(double __a) { return __spirv_ocl_acosh(__a); }
	319	__DEVICE__ float acoshf(float __a) { return __spirv_ocl_acosh(__a); }
	320	__DEVICE__ double asin(double __a) { return __spirv_ocl_asin(__a); }
	321	__DEVICE__ float asinf(float __a) { return __spirv_ocl_asin(__a); }
	322	__DEVICE__ double asinh(double __a) { return __spirv_ocl_asinh(__a); }
	323	__DEVICE__ float asinhf(float __a) { return __spirv_ocl_asinh(__a); }
	324	__DEVICE__ double atan(double __a) { return __spirv_ocl_atan(__a); }
	325	__DEVICE__ double atan2(double __a, double __b) {
	326	return __spirv_ocl_atan2(__a, __b);
	327	}
	328	__DEVICE__ float atan2f(float __a, float __b) {
	329	return __spirv_ocl_atan2(__a, __b);
	330	}
	331	__DEVICE__ float atanf(float __a) { return __spirv_ocl_atan(__a); }
	332	__DEVICE__ double atanh(double __a) { return __spirv_ocl_atanh(__a); }
	333	__DEVICE__ float atanhf(float __a) { return __spirv_ocl_atanh(__a); }
	334	__DEVICE__ double cbrt(double __a) { return __spirv_ocl_cbrt(__a); }
	335	__DEVICE__ float cbrtf(float __a) { return __spirv_ocl_cbrt(__a); }
	336	__DEVICE__ double ceil(double __a) { return __spirv_ocl_ceil(__a); }
	337	__DEVICE__ float ceilf(float __a) { return __spirv_ocl_ceil(__a); }
	338	__DEVICE__ double copysign(double __a, double __b) {
	339	return __spirv_ocl_copysign(__a, __b);
	340	}
	341	__DEVICE__ float copysignf(float __a, float __b) {
	342	return __spirv_ocl_copysign(__a, __b);
	343	}
	344	__DEVICE__ double cos(double __a) { return __spirv_ocl_cos(__a); }
	345	__DEVICE__ float cosf(float __a) { return __spirv_ocl_cos(__a); }
	346	__DEVICE__ double cosh(double __a) { return __spirv_ocl_cosh(__a); }
	347	__DEVICE__ float coshf(float __a) { return __spirv_ocl_cosh(__a); }
	348	__DEVICE__ double cospi(double __a) { return __spirv_ocl_cospi(__a); }
	349	__DEVICE__ float cospif(float __a) { return __spirv_ocl_cospi(__a); }
	350	__DEVICE__ double erf(double __a) { return __spirv_ocl_erf(__a); }
	351	__DEVICE__ double erfc(double __a) { return __spirv_ocl_erfc(__a); }
	352	__DEVICE__ float erfcf(float __a) { return __spirv_ocl_erfc(__a); }
	353	__DEVICE__ double erfcx(double __a) {
	354	return __spirv_ocl_exp(__a * __a) * __spirv_ocl_erfc(__a);
	355	}
	356	__DEVICE__ float erfcxf(float __a) {
	357	return __spirv_ocl_exp(__a * __a) * __spirv_ocl_erfc(__a);
	358	}
	359	__DEVICE__ float erff(float __a) { return __spirv_ocl_erf(__a); }
	360	__DEVICE__ double exp(double __a) { return __spirv_ocl_exp(__a); }
	361	__DEVICE__ double exp10(double __a) { return __spirv_ocl_exp10(__a); }
	362	__DEVICE__ float exp10f(float __a) { return __spirv_ocl_exp10(__a); }
	363	__DEVICE__ double exp2(double __a) { return __spirv_ocl_exp2(__a); }
	364	__DEVICE__ float exp2f(float __a) { return __spirv_ocl_exp2(__a); }
	365	__DEVICE__ float expf(float __a) { return __spirv_ocl_exp(__a); }
	366	__DEVICE__ double expm1(double __a) { return __spirv_ocl_expm1(__a); }
	367	__DEVICE__ float expm1f(float __a) { return __spirv_ocl_expm1(__a); }
	368	__DEVICE__ float fabsf(float __a) { return __spirv_ocl_fabs(__a); }
	369	__DEVICE__ double fdim(double __a, double __b) {
	370	return __spirv_ocl_fdim(__a, __b);
	371	}
	372	__DEVICE__ float fdimf(float __a, float __b) {
	373	return __spirv_ocl_fdim(__a, __b);
	374	}
	375	__DEVICE__ double fdivide(double __a, double __b) { return __a / __b; }
	376	__DEVICE__ float fdividef(float __a, float __b) { return __a / __b; }
	377	__DEVICE__ double floor(double __f) { return __spirv_ocl_floor(__f); }
	378	__DEVICE__ float floorf(float __f) { return __spirv_ocl_floor(__f); }
	379	__DEVICE__ double fma(double __a, double __b, double __c) {
	380	return __spirv_ocl_fma(__a, __b, __c);
	381	}
	382	__DEVICE__ float fmaf(float __a, float __b, float __c) {
	383	return __spirv_ocl_fma(__a, __b, __c);
	384	}
	385	__DEVICE__ double fmax(double __a, double __b) {
	386	return __spirv_ocl_fmax(__a, __b);
	387	}
	388	__DEVICE__ float fmaxf(float __a, float __b) {
	389	return __spirv_ocl_fmax(__a, __b);
	390	}
	391	__DEVICE__ double fmin(double __a, double __b) {
	392	return __spirv_ocl_fmin(__a, __b);
	393	}
	394	__DEVICE__ float fminf(float __a, float __b) {
	395	return __spirv_ocl_fmin(__a, __b);
	396	}
	397	__DEVICE__ double fmod(double __a, double __b) {
	398	return __spirv_ocl_fmod(__a, __b);
	399	}
	400	__DEVICE__ float fmodf(float __a, float __b) {
	401	return __spirv_ocl_fmod(__a, __b);
	402	}
	403	__DEVICE__ double frexp(double __a, int *__b) {
	404	return __spirv_ocl_frexp(__a, __b);
	405	}
	406	__DEVICE__ float frexpf(float __a, int *__b) {
	407	return __spirv_ocl_frexp(__a, __b);
	408	}
	409	__DEVICE__ double hypot(double __a, double __b) {
	410	return __spirv_ocl_hypot(__a, __b);
	411	}
	412	__DEVICE__ float hypotf(float __a, float __b) {
	413	return __spirv_ocl_hypot(__a, __b);
	414	}
	415	__DEVICE__ int ilogb(double __a) { return __spirv_ocl_ilogb(__a); }
	416	__DEVICE__ int ilogbf(float __a) { return __spirv_ocl_ilogb(__a); }
	417	__DEVICE__ long labs(long __a) { return __spirv_ocl_s_abs(__a); };
	418	__DEVICE__ double ldexp(double __a, int __b) {
	419	return __spirv_ocl_ldexp(__a, __b);
	420	}
	421	__DEVICE__ float ldexpf(float __a, int __b) {
	422	return __spirv_ocl_ldexp(__a, __b);
	423	}
	424	__DEVICE__ double lgamma(double __a) { return __spirv_ocl_lgamma(__a); }
	425	__DEVICE__ float lgammaf(float __a) { return __spirv_ocl_lgamma(__a); }
	426	__DEVICE__ long long llabs(long long __a) { return __spirv_ocl_s_abs(__a); }
	427	__DEVICE__ long long llmax(long long __a, long long __b) {
	428	return __spirv_ocl_s_max(__a, __b);
	429	}
	430	__DEVICE__ long long llmin(long long __a, long long __b) {
	431	return __spirv_ocl_s_min(__a, __b);
	432	}
	433	__DEVICE__ long long llrint(double __a) { return __builtin_rint(__a); }
	434	__DEVICE__ long long llrintf(float __a) { return __builtin_rintf(__a); }
	435	__DEVICE__ long long llround(double __a) { return __builtin_round(__a); }
	436	__DEVICE__ long long llroundf(float __a) { return __builtin_roundf(__a); }
	437	__DEVICE__ double round(double __a) { return __spirv_ocl_round(__a); }
	438	__DEVICE__ float roundf(float __a) { return __spirv_ocl_round(__a); }
	439	__DEVICE__ double log(double __a) { return __spirv_ocl_log(__a); }
	440	__DEVICE__ double log10(double __a) { return __spirv_ocl_log10(__a); }
	441	__DEVICE__ float log10f(float __a) { return __spirv_ocl_log10(__a); }
	442	__DEVICE__ double log1p(double __a) { return __spirv_ocl_log1p(__a); }
	443	__DEVICE__ float log1pf(float __a) { return __spirv_ocl_log1p(__a); }
	444	__DEVICE__ double log2(double __a) { return __spirv_ocl_log2(__a); }
	445	__DEVICE__ float log2f(float __a) { return __spirv_ocl_log2(__a); }
	446	__DEVICE__ double logb(double __a) { return __spirv_ocl_logb(__a); }
	447	__DEVICE__ float logbf(float __a) { return __spirv_ocl_logb(__a); }
	448	__DEVICE__ float logf(float __a) { return __spirv_ocl_log(__a); }
	449	__DEVICE__ long lrint(double __a) { return __builtin_rint(__a); }
	450	__DEVICE__ long lrintf(float __a) { return __builtin_rintf(__a); }
	451	__DEVICE__ long lround(double __a) { return __builtin_round(__a); }
	452	__DEVICE__ long lroundf(float __a) { return __builtin_roundf(__a); }
	453	__DEVICE__ int max(int __a, int __b) { return __spirv_ocl_s_max(__a, __b); }
	454	__DEVICE__ int min(int __a, int __b) { return __spirv_ocl_s_min(__a, __b); }
	455	__DEVICE__ double modf(double __a, double *__b) {
	456	return __spirv_ocl_modf(__a, __b);
	457	}
	458	__DEVICE__ float modff(float __a, float *__b) {
	459	return __spirv_ocl_modf(__a, __b);
	460	}
	461	__DEVICE__ double nearbyint(double __a) { return __spirv_ocl_rint(__a); }
	462	__DEVICE__ float nearbyintf(float __a) { return __spirv_ocl_rint(__a); }
	463	__DEVICE__ double nextafter(double __a, double __b) {
	464	return __spirv_ocl_nextafter(__a, __b);
	465	}
	466	__DEVICE__ float nextafterf(float __a, float __b) {
	467	return __spirv_ocl_nextafter(__a, __b);
	468	}
	469
	470	__DEVICE__ double norm(int __dim, const double *__a) {
	471	double __r = 0;
	472	while (__dim--) {
	473	__r += __a[0] * __a[0];
	474	++__a;
	475	}
	476
	477	return __spirv_ocl_sqrt(__r);
	478	}
	479	__DEVICE__ double norm3d(double __a, double __b, double __c) {
	480	return __spirv_ocl_sqrt(__a * __a + __b * __b + __c * __c);
	481	}
	482	__DEVICE__ float norm3df(float __a, float __b, float __c) {
	483	return __spirv_ocl_sqrt(__a * __a + __b * __b + __c * __c);
	484	}
	485	__DEVICE__ double norm4d(double __a, double __b, double __c, double __d) {
	486	return __spirv_ocl_sqrt(__a * __a + __b * __b + __c * __c + __d * __d);
	487	}
	488	__DEVICE__ float norm4df(float __a, float __b, float __c, float __d) {
	489	return __spirv_ocl_sqrt(__a * __a + __b * __b + __c * __c + __d * __d);
	490	}
	491	__DEVICE__ double normcdf(double __a) {
	492	return 0.5 * (1.0 + __spirv_ocl_erf(__a * __spirv_ocl_rsqrt(2.0)));
	493	}
	494	__DEVICE__ float normcdff(float __a) {
	495	return 0.5f * (1.0f + __spirv_ocl_erf(__a * __spirv_ocl_rsqrt(2.0f)));
	496	}
	497	__DEVICE__ float normf(int __dim, const float *__a) {
	498	float __r = 0;
	499	while (__dim--) {
	500	__r += __a[0] * __a[0];
	501	++__a;
	502	}
	503	return __spirv_ocl_sqrt(__r);
	504	}
	505	__DEVICE__ double pow(double __a, double __b) {
	506	return __spirv_ocl_pow(__a, __b);
	507	}
	508	__DEVICE__ float powf(float __a, float __b) {
	509	return __spirv_ocl_pow(__a, __b);
	510	}
	511	__DEVICE__ double powi(double __a, int __b) { return pow(__a, (double)__b); }
	512	__DEVICE__ float powif(float __a, int __b) { return pow(__a, (float)__b); }
	513	__DEVICE__ double rcbrt(double __a) { return 1.0 / __spirv_ocl_cbrt(__a); }
	514	__DEVICE__ float rcbrtf(float __a) { return 1.0f / __spirv_ocl_cbrt(__a); }
	515	__DEVICE__ double remainder(double __a, double __b) {
	516	return __spirv_ocl_remainder(__a, __b);
	517	}
	518	__DEVICE__ float remainderf(float __a, float __b) {
	519	return __spirv_ocl_remainder(__a, __b);
	520	}
	521	__DEVICE__ double remquo(double __a, double __b, int *__c) {
	522	return __spirv_ocl_remquo(__a, __b, __c);
	523	}
	524	__DEVICE__ float remquof(float __a, float __b, int *__c) {
	525	return __spirv_ocl_remquo(__a, __b, __c);
	526	}
	527	__DEVICE__ double rhypot(double __a, double __b) {
	528	return __spirv_ocl_hypot(__a, __b);
	529	}
	530	__DEVICE__ float rhypotf(float __a, float __b) {
	531	return __spirv_ocl_hypot(__a, __b);
	532	}
	533	__DEVICE__ double rint(double __a) { return __spirv_ocl_rint(__a); }
	534	__DEVICE__ float rintf(float __a) { return __spirv_ocl_rint(__a); }
	535	__DEVICE__ double rnorm(int __dim, const double *__a) {
	536	double __r = 0;
	537	while (__dim--) {
	538	__r += __a[0] * __a[0];
	539	++__a;
	540	}
	541
	542	return __spirv_ocl_rsqrt(__r);
	543	}
	544	__DEVICE__ double rnorm3d(double __a, double __b, double __c) {
	545	return __spirv_ocl_rsqrt(__a * __a + __b * __b + __c * __c);
	546	}
	547	__DEVICE__ float rnorm3df(float __a, float __b, float __c) {
	548	return __spirv_ocl_rsqrt(__a * __a + __b * __b + __c * __c);
	549	}
	550	__DEVICE__ double rnorm4d(double __a, double __b, double __c, double __d) {
	551	return __spirv_ocl_rsqrt(__a * __a + __b * __b + __c * __c + __d * __d);
	552	}
	553	__DEVICE__ float rnorm4df(float __a, float __b, float __c, float __d) {
	554	return __spirv_ocl_rsqrt(__a * __a + __b * __b + __c * __c + __d * __d);
	555	}
	556	__DEVICE__ float rnormf(int __dim, const float *__a) {
	557	float __r = 0;
	558	while (__dim--) {
	559	__r += __a[0] * __a[0];
	560	++__a;
	561	}
	562
	563	return __spirv_ocl_rsqrt(__r);
	564	}
	565	__DEVICE__ double rsqrt(double __a) { return __spirv_ocl_rsqrt(__a); }
	566	__DEVICE__ float rsqrtf(float __a) { return __spirv_ocl_rsqrt(__a); }
	567	__DEVICE__ double scalbn(double __a, int __b) {
	568	return __spirv_ocl_ldexp(__a, __b);
	569	}
	570	__DEVICE__ float scalbnf(float __a, int __b) {
	571	return __spirv_ocl_ldexp(__a, __b);
	572	}
	573	__DEVICE__ double scalbln(double __a, long __b) {
	574	if (__b > INT_MAX)
	575	return __a > 0 ? HUGE_VAL : -HUGE_VAL;
	576	if (__b < INT_MIN)
	577	return __a > 0 ? 0.0 : -0.0;
	578	return scalbn(__a, (int)__b);
	579	}
	580	__DEVICE__ float scalblnf(float __a, long __b) {
	581	if (__b > INT_MAX)
	582	return __a > 0 ? HUGE_VALF : -HUGE_VALF;
	583	if (__b < INT_MIN)
	584	return __a > 0 ? 0.f : -0.f;
	585	return scalbnf(__a, (int)__b);
	586	}
	587	__DEVICE__ double sin(double __a) { return __spirv_ocl_sin(__a); }
	588	__DEVICE__ void sincos(double __a, double __s, double __c) {
	589	*__s = __spirv_ocl_sincos(__a, __c);
	590	}
	591	__DEVICE__ void sincosf(float __a, float __s, float __c) {
	592	*__s = __spirv_ocl_sincos(__a, __c);
	593	}
	594	__DEVICE__ void sincospi(double __a, double __s, double __c) {
	595	*__s = __spirv_ocl_sinpi(__a);
	596	*__c = __spirv_ocl_cospi(__a);
	597	}
	598	__DEVICE__ void sincospif(float __a, float __s, float __c) {
	599	*__s = __spirv_ocl_sinpi(__a);
	600	*__c = __spirv_ocl_cospi(__a);
	601	}
	602	__DEVICE__ float sinf(float __a) { return __spirv_ocl_sin(__a); }
	603	__DEVICE__ double sinh(double __a) { return __spirv_ocl_sinh(__a); }
	604	__DEVICE__ float sinhf(float __a) { return __spirv_ocl_sinh(__a); }
	605	__DEVICE__ double sinpi(double __a) { return __spirv_ocl_sinpi(__a); }
	606	__DEVICE__ float sinpif(float __a) { return __spirv_ocl_sinpi(__a); }
	607	__DEVICE__ double sqrt(double __a) { return __spirv_ocl_sqrt(__a); }
	608	__DEVICE__ float sqrtf(float __a) { return __spirv_ocl_sqrt(__a); }
	609	__DEVICE__ double tan(double __a) { return __spirv_ocl_tan(__a); }
	610	__DEVICE__ float tanf(float __a) { return __spirv_ocl_tan(__a); }
	611	__DEVICE__ double tanh(double __a) { return __spirv_ocl_tanh(__a); }
	612	__DEVICE__ float tanhf(float __a) { return __spirv_ocl_tanh(__a); }
	613	__DEVICE__ double tgamma(double __a) { return __spirv_ocl_tgamma(__a); }
	614	__DEVICE__ float tgammaf(float __a) { return __spirv_ocl_tgamma(__a); }
	615	__DEVICE__ double trunc(double __a) { return __spirv_ocl_trunc(__a); }
	616	__DEVICE__ float truncf(float __a) { return __spirv_ocl_trunc(__a); }
	617	__DEVICE__ unsigned long long ullmax(unsigned long long __a,
	618	unsigned long long __b) {
	619	return __spirv_ocl_u_max(__a, __b);
	620	}
	621	__DEVICE__ unsigned long long ullmin(unsigned long long __a,
	622	unsigned long long __b) {
	623	return __spirv_ocl_u_min(__a, __b);
	624	}
	625	__DEVICE__ unsigned int umax(unsigned int __a, unsigned int __b) {
	626	return __spirv_ocl_u_max(__a, __b);
	627	}
	628	__DEVICE__ unsigned int umin(unsigned int __a, unsigned int __b) {
	629	return __spirv_ocl_u_min(__a, __b);
	630	}
	631
	632	#if !defined(__cplusplus) && __STDC_VERSION__ >= 201112L
	633	#define isfinite(__x) _Generic((__x), float: __finitef, double: __finite)(__x)
	634	#define isinf(__x) _Generic((__x), float: __isinff, double: __isinf)(__x)
	635	#define isnan(__x) _Generic((__x), float: __isnanf, double: __isnan)(__x)
	636	#define signbit(__x) _Generic((__x), float: __signbitf, double: __signbit)(__x)
	637	#endif // !defined(__cplusplus) && __STDC_VERSION__ >= 201112L
	638
	639	__DEVICE__
	640	unsigned long __make_mantissa_base8(const char *__tagp) {
	641	unsigned long __r = 0;
	642	while (*__tagp != '\0') {
	643	char __tmp = *__tagp;
	644
	645	if (__tmp >= '0' && __tmp <= '7')
	646	__r = (__r * 8u) + __tmp - '0';
	647	else
	648	return 0;
	649
	650	++__tagp;
	651	}
	652
	653	return __r;
	654	}
	655
	656	__DEVICE__
	657	unsigned long __make_mantissa_base10(const char *__tagp) {
	658	unsigned long __r = 0;
	659	while (*__tagp != '\0') {
	660	char __tmp = *__tagp;
	661
	662	if (__tmp >= '0' && __tmp <= '9')
	663	__r = (__r * 10u) + __tmp - '0';
	664	else
	665	return 0;
	666
	667	++__tagp;
	668	}
	669
	670	return __r;
	671	}
	672
	673	__DEVICE__
	674	unsigned long __make_mantissa_base16(const char *__tagp) {
	675	unsigned long __r = 0;
	676	while (*__tagp != '\0') {
	677	char __tmp = *__tagp;
	678
	679	if (__tmp >= '0' && __tmp <= '9')
	680	__r = (__r * 16u) + __tmp - '0';
	681	else if (__tmp >= 'a' && __tmp <= 'f')
	682	__r = (__r * 16u) + __tmp - 'a' + 10;
	683	else if (__tmp >= 'A' && __tmp <= 'F')
	684	__r = (__r * 16u) + __tmp - 'A' + 10;
	685	else
	686	return 0;
	687
	688	++__tagp;
	689	}
	690
	691	return __r;
	692	}
	693
	694	__DEVICE__
	695	unsigned long __make_mantissa(const char *__tagp) {
	696	if (!__tagp)
	697	return 0;
	698	if (*__tagp == '0') {
	699	++__tagp;
	700
	701	if (__tagp == 'x' \|\| __tagp == 'X')
	702	return __make_mantissa_base16(++__tagp);
	703	else
	704	return __make_mantissa_base8(__tagp);
	705	}
	706
	707	return __make_mantissa_base10(__tagp);
	708	}
	709
	710	float nanf(const char *__tagp) {
	711	return __spirv_ocl_nan((unsigned int)__make_mantissa(__tagp));
	712	}
	713	double nan(const char *__tagp) {
	714	return __spirv_ocl_nan(__make_mantissa(__tagp));
	715	}
	716
	717	#pragma pop_macro("__DEVICE__")
	718	#endif // __CLANG_GPU_DISABLE_MATH_WRAPPERS
	719	#endif // __CLANG_SPIRV_MATH_H__

lib/include/altivec.h+79-9

...	...	@@ -2117,7 +2117,7 @@ vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {
2117	2117	}
2118	2118	#endif
2119	2119
2120		#ifdef __VSX__
	2120	#ifdef __POWER8_VECTOR__
2121	2121	static __inline__ vector bool long long __ATTRS_o_ai
2122	2122	vec_cmpne(vector double __a, vector double __b) {
2123	2123	return (vector bool long long)
...	...	@@ -6404,6 +6404,18 @@ vec_mulh(vector unsigned long long __a, vector unsigned long long __b) {
6404	6404	}
6405	6405	#endif
6406	6406
	6407	#ifdef __FUTURE_VECTOR__
	6408	static __inline__ vector signed short
	6409	__ATTRS_o_ai vec_mulh(vector signed short __a, vector signed short __b) {
	6410	return __builtin_altivec_vmulhsh(__a, __b);
	6411	}
	6412
	6413	static __inline__ vector unsigned short __ATTRS_o_ai
	6414	vec_mulh(vector unsigned short __a, vector unsigned short __b) {
	6415	return __builtin_altivec_vmulhuh(__a, __b);
	6416	}
	6417	#endif
	6418
6407	6419	/* vec_mulo */
6408	6420
6409	6421	static __inline__ vector short __ATTRS_o_ai vec_mulo(vector signed char __a,
...	...	@@ -17809,6 +17821,7 @@ vec_xl(ptrdiff_t __offset, const unsigned __int128 *__ptr) {
17809	17821	/* vec_xl_be */
17810	17822
17811	17823	#ifdef __LITTLE_ENDIAN__
	17824	#ifdef __VSX__
17812	17825	static __inline__ vector signed char __ATTRS_o_ai
17813	17826	vec_xl_be(ptrdiff_t __offset, const signed char *__ptr) {
17814	17827	vector signed char __vec = (vector signed char)__builtin_vsx_lxvd2x_be(__offset, __ptr);
...	...	@@ -17850,7 +17863,6 @@ vec_xl_be(signed long long __offset, const float *__ptr) {
17850	17863	return (vector float)__builtin_vsx_lxvw4x_be(__offset, __ptr);
17851	17864	}
17852	17865
17853		#ifdef __VSX__
17854	17866	static __inline__ vector signed long long __ATTRS_o_ai
17855	17867	vec_xl_be(signed long long __offset, const signed long long *__ptr) {
17856	17868	return (vector signed long long)__builtin_vsx_lxvd2x_be(__offset, __ptr);
...	...	@@ -17865,7 +17877,6 @@ static __inline__ vector double __ATTRS_o_ai
17865	17877	vec_xl_be(signed long long __offset, const double *__ptr) {
17866	17878	return (vector double)__builtin_vsx_lxvd2x_be(__offset, __ptr);
17867	17879	}
17868		#endif
17869	17880
17870	17881	#if defined(__POWER8_VECTOR__) && defined(__powerpc64__) && \
17871	17882	defined(__SIZEOF_INT128__)
...	...	@@ -17879,8 +17890,9 @@ vec_xl_be(signed long long __offset, const unsigned __int128 *__ptr) {
17879	17890	return vec_xl(__offset, __ptr);
17880	17891	}
17881	17892	#endif
17882		#else
17883		#define vec_xl_be vec_xl
	17893	#endif // __VSX__
	17894	#else // ! __LITTLE_ENDIAN__
	17895	#define vec_xl_be vec_xl
17884	17896	#endif
17885	17897
17886	17898	#if defined(__POWER10_VECTOR__) && defined(__VSX__) && \
...	...	@@ -18130,6 +18142,7 @@ vec_xst_trunc(vector unsigned __int128 __vec, ptrdiff_t __offset,
18130	18142	/* vec_xst_be */
18131	18143
18132	18144	#ifdef __LITTLE_ENDIAN__
	18145	#ifdef __VSX__
18133	18146	static __inline__ void __ATTRS_o_ai vec_xst_be(vector signed char __vec,
18134	18147	signed long long __offset,
18135	18148	signed char *__ptr) {
...	...	@@ -18186,7 +18199,6 @@ static __inline__ void __ATTRS_o_ai vec_xst_be(vector float __vec,
18186	18199	__builtin_vsx_stxvw4x_be((vector int)__vec, __offset, __ptr);
18187	18200	}
18188	18201
18189		#ifdef __VSX__
18190	18202	static __inline__ void __ATTRS_o_ai vec_xst_be(vector signed long long __vec,
18191	18203	signed long long __offset,
18192	18204	signed long long *__ptr) {
...	...	@@ -18204,7 +18216,6 @@ static __inline__ void __ATTRS_o_ai vec_xst_be(vector double __vec,
18204	18216	double *__ptr) {
18205	18217	__builtin_vsx_stxvd2x_be((vector double)__vec, __offset, __ptr);
18206	18218	}
18207		#endif
18208	18219
18209	18220	#if defined(__POWER8_VECTOR__) && defined(__powerpc64__) && \
18210	18221	defined(__SIZEOF_INT128__)
...	...	@@ -18220,8 +18231,9 @@ static __inline__ void __ATTRS_o_ai vec_xst_be(vector unsigned __int128 __vec,
18220	18231	vec_xst(__vec, __offset, __ptr);
18221	18232	}
18222	18233	#endif
18223		#else
18224		#define vec_xst_be vec_xst
	18234	#endif // VSX
	18235	#else // ! __LITTLE_ENDIAN__
	18236	#define vec_xst_be vec_xst
18225	18237	#endif
18226	18238
18227	18239	#ifdef __POWER9_VECTOR__
...	...	@@ -19314,6 +19326,64 @@ vec_sra(vector signed __int128 __a, vector unsigned __int128 __b) {
19314	19326	#endif /* __SIZEOF_INT128__ */
19315	19327	#endif /* __POWER10_VECTOR__ */
19316	19328
	19329	#ifdef __FUTURE_VECTOR__
	19330
	19331	/* vec_uncompress* - Deeply Compressed Weights builtins */
	19332
	19333	static __inline__ vector unsigned char __ATTRS_o_ai
	19334	vec_uncompresshn(vector unsigned char __a, vector unsigned char __b) {
	19335	return __builtin_altivec_vucmprhn(__a, __b);
	19336	}
	19337
	19338	static __inline__ vector unsigned char __ATTRS_o_ai
	19339	vec_uncompressln(vector unsigned char __a, vector unsigned char __b) {
	19340	return __builtin_altivec_vucmprln(__a, __b);
	19341	}
	19342
	19343	static __inline__ vector unsigned char __ATTRS_o_ai
	19344	vec_uncompresshb(vector unsigned char __a, vector unsigned char __b) {
	19345	return __builtin_altivec_vucmprhb(__a, __b);
	19346	}
	19347
	19348	static __inline__ vector unsigned char __ATTRS_o_ai
	19349	vec_uncompresslb(vector unsigned char __a, vector unsigned char __b) {
	19350	return __builtin_altivec_vucmprlb(__a, __b);
	19351	}
	19352
	19353	static __inline__ vector unsigned char __ATTRS_o_ai
	19354	vec_uncompresshh(vector unsigned char __a, vector unsigned char __b) {
	19355	return __builtin_altivec_vucmprhh(__a, __b);
	19356	}
	19357
	19358	static __inline__ vector unsigned char __ATTRS_o_ai
	19359	vec_uncompresslh(vector unsigned char __a, vector unsigned char __b) {
	19360	return __builtin_altivec_vucmprlh(__a, __b);
	19361	}
	19362
	19363	static __inline__ vector unsigned char __ATTRS_o_ai
	19364	vec_unpack_hsn_to_byte(vector unsigned char __a) {
	19365	return __builtin_altivec_vupkhsntob(__a);
	19366	}
	19367
	19368	static __inline__ vector unsigned char __ATTRS_o_ai
	19369	vec_unpack_lsn_to_byte(vector unsigned char __a) {
	19370	return __builtin_altivec_vupklsntob(__a);
	19371	}
	19372
	19373	#define vec_unpack_int4_to_bf16(__a, __imm) \
	19374	__builtin_altivec_vupkint4tobf16((__a), (__imm))
	19375
	19376	#define vec_unpack_int8_to_bf16(__a, __imm) \
	19377	__builtin_altivec_vupkint8tobf16((__a), (__imm))
	19378
	19379	#define vec_unpack_int4_to_fp32(__a, __imm) \
	19380	__builtin_altivec_vupkint4tofp32((__a), (__imm))
	19381
	19382	#define vec_unpack_int8_to_fp32(__a, __imm) \
	19383	__builtin_altivec_vupkint8tofp32((__a), (__imm))
	19384
	19385	#endif /* __FUTURE_VECTOR__ */
	19386
19317	19387	#ifdef __POWER8_VECTOR__
19318	19388	#define __bcdadd(__a, __b, __ps) __builtin_ppc_bcdadd((__a), (__b), (__ps))
19319	19389	#define __bcdsub(__a, __b, __ps) __builtin_ppc_bcdsub((__a), (__b), (__ps))

lib/include/amdhsa_abi.h created+83

...	...	@@ -0,0 +1,83 @@
	1	//===-- amdhsa_abi.h - AMDHSA ABI definition utilities --------------------===//
	2	//
	3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	4	// See https://llvm.org/LICENSE.txt for license information.
	5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	6	//
	7	//===----------------------------------------------------------------------===//
	8
	9	#ifndef __AMDHSA_ABI_H
	10	#define __AMDHSA_ABI_H
	11
	12	#include <stddef.h>
	13	#include <stdint.h>
	14
	15	typedef struct __attribute__((aligned(8))) amdhsa_implicit_kernarg_v5 {
	16	uint32_t block_count[3];
	17	uint16_t group_size[3];
	18	uint16_t remainder[3];
	19	char reserved0[16];
	20	uint64_t global_offset[3];
	21	uint16_t grid_dims;
	22	char reserved1[6];
	23	__attribute__((opencl_global)) void *printf_buffer;
	24	__attribute__((opencl_global)) void *hostcall_buffer;
	25	__attribute__((opencl_global)) void *multigrid_sync_arg;
	26	__attribute__((opencl_global)) void *heap_v1;
	27	__attribute__((opencl_global)) void *default_queue;
	28	__attribute__((opencl_global)) void *completion_action;
	29	char reserved2[72];
	30	uint32_t private_base; // Unused on gfx9+
	31	uint32_t shared_base; // Unused on gfx9+
	32	__attribute__((opencl_global)) void *queue_ptr;
	33	char reserved3[48];
	34	} amdhsa_implicit_kernarg_v5;
	35
	36	_Static_assert(sizeof(amdhsa_implicit_kernarg_v5) == 256, "wrong struct size");
	37
	38	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, block_count[0]) == 0,
	39	"wrong offset");
	40	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, block_count[1]) == 4,
	41	"wrong offset");
	42	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, block_count[2]) == 8,
	43	"wrong offset");
	44	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, group_size[0]) == 12,
	45	"wrong offset");
	46	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, group_size[1]) == 14,
	47	"wrong offset");
	48	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, group_size[2]) == 16,
	49	"wrong offset");
	50	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, remainder[0]) == 18,
	51	"wrong offset");
	52	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, remainder[1]) == 20,
	53	"wrong offset");
	54	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, remainder[2]) == 22,
	55	"wrong offset");
	56	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, global_offset[0]) == 40,
	57	"wrong offset");
	58	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, global_offset[1]) == 48,
	59	"wrong offset");
	60	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, global_offset[2]) == 56,
	61	"wrong offset");
	62	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, grid_dims) == 64,
	63	"wrong offset");
	64	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, printf_buffer) == 72,
	65	"wrong offset");
	66	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, hostcall_buffer) == 80,
	67	"wrong offset");
	68	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, multigrid_sync_arg) == 88,
	69	"wrong offset");
	70	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, heap_v1) == 96,
	71	"wrong offset");
	72	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, default_queue) == 104,
	73	"wrong offset");
	74	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, completion_action) == 112,
	75	"wrong offset");
	76	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, private_base) == 192,
	77	"wrong offset");
	78	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, shared_base) == 196,
	79	"wrong offset");
	80	_Static_assert(offsetof(amdhsa_implicit_kernarg_v5, queue_ptr) == 200,
	81	"wrong offset");
	82
	83	#endif // __AMDHSA_ABI_H

lib/include/amo.h+89

...	...	@@ -124,6 +124,95 @@ static inline int64_t amo_ldat_sswap(int64_t *ptr, int64_t val) {
124	124	return __builtin_amo_ldat_s(ptr, val, _AMO_LD_SWAP);
125	125	}
126	126
	127	/* AMO Store Operation Codes (FC values) */
	128	enum _AMO_ST {
	129	_AMO_ST_ADD = 0x00, /* Store Add */
	130	_AMO_ST_XOR = 0x01, /* Store Xor */
	131	_AMO_ST_IOR = 0x02, /* Store Ior */
	132	_AMO_ST_AND = 0x03, /* Store And */
	133	_AMO_ST_UMAX = 0x04, /* Store Unsigned Maximum */
	134	_AMO_ST_SMAX = 0x05, /* Store Signed Maximum */
	135	_AMO_ST_UMIN = 0x06, /* Store Unsigned Minimum */
	136	_AMO_ST_SMIN = 0x07, /* Store Signed Minimum */
	137	_AMO_ST_TWIN = 0x18 /* Store Twin */
	138	};
	139
	140	/* 32-bit unsigned AMO store operations */
	141	static inline void amo_stwat_add(uint32_t *ptr, uint32_t val) {
	142	__builtin_amo_stwat(ptr, val, _AMO_ST_ADD);
	143	}
	144
	145	static inline void amo_stwat_xor(uint32_t *ptr, uint32_t val) {
	146	__builtin_amo_stwat(ptr, val, _AMO_ST_XOR);
	147	}
	148
	149	static inline void amo_stwat_ior(uint32_t *ptr, uint32_t val) {
	150	__builtin_amo_stwat(ptr, val, _AMO_ST_IOR);
	151	}
	152
	153	static inline void amo_stwat_and(uint32_t *ptr, uint32_t val) {
	154	__builtin_amo_stwat(ptr, val, _AMO_ST_AND);
	155	}
	156
	157	static inline void amo_stwat_umax(uint32_t *ptr, uint32_t val) {
	158	__builtin_amo_stwat(ptr, val, _AMO_ST_UMAX);
	159	}
	160
	161	static inline void amo_stwat_umin(uint32_t *ptr, uint32_t val) {
	162	__builtin_amo_stwat(ptr, val, _AMO_ST_UMIN);
	163	}
	164
	165	/* 32-bit signed AMO store operations */
	166	static inline void amo_stwat_sadd(int32_t *ptr, int32_t val) {
	167	__builtin_amo_stwat_s(ptr, val, _AMO_ST_ADD);
	168	}
	169
	170	static inline void amo_stwat_smax(int32_t *ptr, int32_t val) {
	171	__builtin_amo_stwat_s(ptr, val, _AMO_ST_SMAX);
	172	}
	173
	174	static inline void amo_stwat_smin(int32_t *ptr, int32_t val) {
	175	__builtin_amo_stwat_s(ptr, val, _AMO_ST_SMIN);
	176	}
	177
	178	/* 64-bit unsigned AMO store operations */
	179	static inline void amo_stdat_add(uint64_t *ptr, uint64_t val) {
	180	__builtin_amo_stdat(ptr, val, _AMO_ST_ADD);
	181	}
	182
	183	static inline void amo_stdat_xor(uint64_t *ptr, uint64_t val) {
	184	__builtin_amo_stdat(ptr, val, _AMO_ST_XOR);
	185	}
	186
	187	static inline void amo_stdat_ior(uint64_t *ptr, uint64_t val) {
	188	__builtin_amo_stdat(ptr, val, _AMO_ST_IOR);
	189	}
	190
	191	static inline void amo_stdat_and(uint64_t *ptr, uint64_t val) {
	192	__builtin_amo_stdat(ptr, val, _AMO_ST_AND);
	193	}
	194
	195	static inline void amo_stdat_umax(uint64_t *ptr, uint64_t val) {
	196	__builtin_amo_stdat(ptr, val, _AMO_ST_UMAX);
	197	}
	198
	199	static inline void amo_stdat_umin(uint64_t *ptr, uint64_t val) {
	200	__builtin_amo_stdat(ptr, val, _AMO_ST_UMIN);
	201	}
	202
	203	/* 64-bit signed AMO store operations */
	204	static inline void amo_stdat_sadd(int64_t *ptr, int64_t val) {
	205	__builtin_amo_stdat_s(ptr, val, _AMO_ST_ADD);
	206	}
	207
	208	static inline void amo_stdat_smax(int64_t *ptr, int64_t val) {
	209	__builtin_amo_stdat_s(ptr, val, _AMO_ST_SMAX);
	210	}
	211
	212	static inline void amo_stdat_smin(int64_t *ptr, int64_t val) {
	213	__builtin_amo_stdat_s(ptr, val, _AMO_ST_SMIN);
	214	}
	215
127	216	#ifdef __cplusplus
128	217	}
129	218	#endif

lib/include/amxtf32intrin.h deleted-108

...	...	@@ -1,108 +0,0 @@
1		/===------------- amxtf32intrin.h - AMX_TF32 intrinsics -- C++ -*---------===
2		*
3		* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4		* See https://llvm.org/LICENSE.txt for license information.
5		* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6		*
7		*===------------------------------------------------------------------------===
8		*/
9
10		#ifndef __IMMINTRIN_H
11		#error "Never use <amxtf32intrin.h> directly; include <immintrin.h> instead."
12		#endif // __IMMINTRIN_H
13
14		#ifndef __AMX_TF32INTRIN_H
15		#define __AMX_TF32INTRIN_H
16		#ifdef __x86_64__
17
18		#define __DEFAULT_FN_ATTRS_TF32 \
19		__attribute__((__always_inline__, __nodebug__, __target__("amx-tf32")))
20
21		/// Do Matrix Multiplication of \a a and \a b, and then do Matrix Plus
22		/// with \a srcdst.
23		/// All the calculation is base on float32 but with the lower 13-bit set to 0.
24		///
25		/// \headerfile <immintrin.h>
26		///
27		/// \code
28		/// void _tile_mmultf32ps(constexpr int srcdst, constexpr int a, \
29		/// constexpr int b);
30		/// \endcode
31		///
32		/// This intrinsic corresponds to the <c> TMMULTF32PS </c> instruction.
33		///
34		/// \param srcdst
35		/// The destination tile. Max size is 1024 Bytes.
36		/// \param a
37		/// The 1st source tile. Max size is 1024 Bytes.
38		/// \param b
39		/// The 2nd source tile. Max size is 1024 Bytes.
40		///
41		/// \code{.operation}
42		/// DEFINE zero_lower_mantissa_bits_fp32(x[31:0]) {
43		/// dword[12:0] := 0
44		/// dword[31:13] := x[31:13]
45		/// return dword
46		/// }
47		///
48		/// DEFINE silence_snan_fp32(x[31:0]) {
49		/// IF (x.exponent == 255 and x.fraction != 0 and x.fraction[22] == 0)
50		/// x.fraction[22] := 1
51		/// return x
52		/// }
53		///
54		/// elements_a := a.colsb / 4
55		/// elements_dest := srcdst.colsb / 4
56		///
57		/// FOR m = 0 TO (srcdst.rows-1)
58		/// tmp[511:0] := 0
59		/// FOR k = 0 TO (elements_a-1)
60		/// FOR n = 0 TO (elements_dest-1)
61		/// af := silence_snan_fp32(a.row[m].fp32[k])
62		/// bf := silence_snan_fp32(b.row[k].fp32[n])
63		/// tmp.fp32[n] += zero_lower_mantissa_bits_fp32(af)
64		/// * zero_lower_mantissa_bits_fp32(bf)
65		/// ENDFOR
66		/// ENDFOR
67		///
68		/// FOR n = 0 TO (elements_dest-1)
69		/// tmp.fp32[n] += srcdst.row[m].fp32[n]
70		/// ENDFOR
71		/// write_row_and_zero(srcdst, m, tmp, srcdst.colsb)
72		///
73		/// ENDFOR
74		///
75		/// zero_upper_rows(srcdst, srcdst.rows)
76		/// zero_tileconfig_start()
77		/// \endcode
78		#define _tile_mmultf32ps(srcdst, a, b) \
79		__builtin_ia32_tmmultf32ps((srcdst), (a), (b))
80
81		static __inline__ _tile1024i __DEFAULT_FN_ATTRS_TF32
82		_tile_mmultf32ps_internal(unsigned short m, unsigned short n, unsigned short k,
83		_tile1024i dst, _tile1024i src1, _tile1024i src2) {
84		return __builtin_ia32_tmmultf32ps_internal(m, n, k, dst, src1, src2);
85		}
86
87		/// Do Matrix Multiplication of src0 and src1, and then do Matrix Plus with dst.
88		/// All the calculation is base on float32 but with the lower 13-bit set to 0.
89		///
90		/// \headerfile <immintrin.h>
91		///
92		/// This intrinsic corresponds to the <c> TMMULTF32PS </c> instruction.
93		///
94		/// \param dst
95		/// The destination tile. Max size is 1024 Bytes.
96		/// \param src0
97		/// The 1st source tile. Max size is 1024 Bytes.
98		/// \param src1
99		/// The 2nd source tile. Max size is 1024 Bytes.
100		__DEFAULT_FN_ATTRS_TF32
101		static void __tile_mmultf32ps(__tile1024i *dst, __tile1024i src0,
102		__tile1024i src1) {
103		dst->tile = _tile_mmultf32ps_internal(src0.row, src1.col, src0.col, dst->tile,
104		src0.tile, src1.tile);
105		}
106
107		#endif // __x86_64__
108		#endif // __AMX_TF32INTRIN_H

lib/include/andes_vector.h+5

...	...	@@ -13,4 +13,9 @@
13	13
14	14	#pragma clang riscv intrinsic andes_vector
15	15
	16	#define __riscv_intrinsic_xandesvbfhcvt 1
	17	#define __riscv_intrinsic_xandesvdot 1
	18	#define __riscv_intrinsic_xandesvpackfph 1
	19	#define __riscv_intrinsic_xandesvsintload 1
	20
16	21	#endif //_ANDES_VECTOR_H_

lib/include/arm64_neon.h created+21

...	...	@@ -0,0 +1,21 @@
	1	/*===---- arm64_neon.h - ARM64 NEON intrinsics -----------------------------===
	2	*
	3	* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	4	* See https://llvm.org/LICENSE.txt for license information.
	5	* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	6	*
	7	*===-----------------------------------------------------------------------===
	8	*/
	9
	10	/* Only include this if we're compiling for the windows platform. */
	11	#ifndef _MSC_VER
	12	#include_next <arm64_neon.h>
	13	#else
	14
	15	#ifndef __ARM64_NEON_H
	16	#define __ARM64_NEON_H
	17
	18	#include <arm_neon.h>
	19
	20	#endif /* __ARM64_NEON_H */
	21	#endif /* _MSC_VER */

lib/include/arm64intr.h+10

...	...	@@ -15,6 +15,16 @@
15	15	#ifndef __ARM64INTR_H
16	16	#define __ARM64INTR_H
17	17
	18	/* Encode an AArch64 system register for use with
	19	_ReadStatusReg/_WriteStatusReg. op0 must be 2 or 3; only the low bit is
	20	stored. */
	21	#define ARM64_SYSREG(op0, op1, CRn, CRm, op2) \
	22	((((op0) & 0x1) << 14) \| (((op1) & 0x7) << 11) \| (((CRn) & 0xF) << 7) \| \
	23	(((CRm) & 0xF) << 3) \| ((op2) & 0x7))
	24
	25	#define ARM64_FPCR ARM64_SYSREG(3, 3, 4, 4, 0)
	26	#define ARM64_FPSR ARM64_SYSREG(3, 3, 4, 4, 1)
	27
18	28	typedef enum
19	29	{
20	30	_ARM64_BARRIER_SY = 0xF,

lib/include/arm_acle.h+1

...	...	@@ -115,6 +115,7 @@ __swp(uint32_t __x, volatile uint32_t *__p) {
115	115	#else
116	116	#define __plix(cache_level, retention_policy, addr) \
117	117	__builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0)
	118	#define __pldir(addr) __builtin_arm_prefetch_ir(addr)
118	119	#endif
119	120
120	121	/* 7.7 NOP */

lib/include/arm_neon.h+3922-3754

...	...	@@ -145,1431 +145,125 @@ typedef struct poly64x2x4_t {
145	145	#endif
146	146	#endif
147	147	#ifdef __LITTLE_ENDIAN__
148		#define splatq_lane_bf16(__p0, __p1) __extension__ ({ \
149		bfloat16x8_t __ret; \
150		bfloat16x4_t __s0 = __p0; \
151		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_lane_bf16(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
152		__ret; \
153		})
154		#else
155		#define splatq_lane_bf16(__p0, __p1) __extension__ ({ \
156		bfloat16x8_t __ret; \
157		bfloat16x4_t __s0 = __p0; \
158		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
159		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_lane_bf16(__builtin_bit_cast(int8x8_t, __rev0), __p1, 11)); \
160		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
161		__ret; \
162		})
163		#define __noswap_splatq_lane_bf16(__p0, __p1) __extension__ ({ \
164		bfloat16x8_t __ret; \
165		bfloat16x4_t __s0 = __p0; \
166		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_lane_bf16(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
167		__ret; \
168		})
169		#endif
170
171		#ifdef __LITTLE_ENDIAN__
172		#define splat_lane_bf16(__p0, __p1) __extension__ ({ \
173		bfloat16x4_t __ret; \
174		bfloat16x4_t __s0 = __p0; \
175		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_lane_bf16(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
176		__ret; \
177		})
178		#else
179		#define splat_lane_bf16(__p0, __p1) __extension__ ({ \
180		bfloat16x4_t __ret; \
181		bfloat16x4_t __s0 = __p0; \
182		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
183		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_lane_bf16(__builtin_bit_cast(int8x8_t, __rev0), __p1, 11)); \
184		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
185		__ret; \
186		})
187		#define __noswap_splat_lane_bf16(__p0, __p1) __extension__ ({ \
188		bfloat16x4_t __ret; \
189		bfloat16x4_t __s0 = __p0; \
190		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_lane_bf16(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
191		__ret; \
192		})
193		#endif
194
195		#ifdef __LITTLE_ENDIAN__
196		#define splatq_laneq_bf16(__p0, __p1) __extension__ ({ \
197		bfloat16x8_t __ret; \
198		bfloat16x8_t __s0 = __p0; \
199		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_laneq_bf16(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
200		__ret; \
201		})
202		#else
203		#define splatq_laneq_bf16(__p0, __p1) __extension__ ({ \
204		bfloat16x8_t __ret; \
205		bfloat16x8_t __s0 = __p0; \
206		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
207		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_laneq_bf16(__builtin_bit_cast(int8x16_t, __rev0), __p1, 43)); \
208		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
209		__ret; \
210		})
211		#define __noswap_splatq_laneq_bf16(__p0, __p1) __extension__ ({ \
212		bfloat16x8_t __ret; \
213		bfloat16x8_t __s0 = __p0; \
214		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_laneq_bf16(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
215		__ret; \
216		})
217		#endif
218
219		#ifdef __LITTLE_ENDIAN__
220		#define splat_laneq_bf16(__p0, __p1) __extension__ ({ \
221		bfloat16x4_t __ret; \
222		bfloat16x8_t __s0 = __p0; \
223		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_laneq_bf16(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
224		__ret; \
225		})
226		#else
227		#define splat_laneq_bf16(__p0, __p1) __extension__ ({ \
228		bfloat16x4_t __ret; \
229		bfloat16x8_t __s0 = __p0; \
230		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
231		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_laneq_bf16(__builtin_bit_cast(int8x16_t, __rev0), __p1, 43)); \
232		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
233		__ret; \
234		})
235		#define __noswap_splat_laneq_bf16(__p0, __p1) __extension__ ({ \
236		bfloat16x4_t __ret; \
237		bfloat16x8_t __s0 = __p0; \
238		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_laneq_bf16(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
239		__ret; \
240		})
241		#endif
242
243		#ifdef __LITTLE_ENDIAN__
244		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfdotq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
245		float32x4_t __ret;
246		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfdotq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
247		return __ret;
248		}
249		#else
250		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfdotq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
251		float32x4_t __ret;
252		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
253		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
254		bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
255		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfdotq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
256		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
257		return __ret;
258		}
259		__ai __attribute__((target("bf16,neon"))) float32x4_t __noswap_vbfdotq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
260		float32x4_t __ret;
261		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfdotq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
262		return __ret;
263		}
264		#endif
265
266		#ifdef __LITTLE_ENDIAN__
267		__ai __attribute__((target("bf16,neon"))) float32x2_t vbfdot_f32(float32x2_t __p0, bfloat16x4_t __p1, bfloat16x4_t __p2) {
268		float32x2_t __ret;
269		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vbfdot_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), __builtin_bit_cast(int8x8_t, __p2), 9));
270		return __ret;
271		}
272		#else
273		__ai __attribute__((target("bf16,neon"))) float32x2_t vbfdot_f32(float32x2_t __p0, bfloat16x4_t __p1, bfloat16x4_t __p2) {
274		float32x2_t __ret;
275		float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
276		bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
277		bfloat16x4_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_64_16);
278		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vbfdot_f32(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __builtin_bit_cast(int8x8_t, __rev2), 9));
279		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
280		return __ret;
281		}
282		__ai __attribute__((target("bf16,neon"))) float32x2_t __noswap_vbfdot_f32(float32x2_t __p0, bfloat16x4_t __p1, bfloat16x4_t __p2) {
283		float32x2_t __ret;
284		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vbfdot_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), __builtin_bit_cast(int8x8_t, __p2), 9));
285		return __ret;
286		}
287		#endif
288
289		#ifdef __LITTLE_ENDIAN__
290		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlalbq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
291		float32x4_t __ret;
292		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlalbq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
293		return __ret;
294		}
295		#else
296		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlalbq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
297		float32x4_t __ret;
298		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
299		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
300		bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
301		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlalbq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
302		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
303		return __ret;
304		}
305		__ai __attribute__((target("bf16,neon"))) float32x4_t __noswap_vbfmlalbq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
306		float32x4_t __ret;
307		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlalbq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
308		return __ret;
309		}
310		#endif
311
312		#ifdef __LITTLE_ENDIAN__
313		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlaltq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
314		float32x4_t __ret;
315		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlaltq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
316		return __ret;
317		}
318		#else
319		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlaltq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
320		float32x4_t __ret;
321		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
322		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
323		bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
324		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlaltq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
325		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
326		return __ret;
327		}
328		__ai __attribute__((target("bf16,neon"))) float32x4_t __noswap_vbfmlaltq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
329		float32x4_t __ret;
330		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlaltq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
331		return __ret;
332		}
333		#endif
334
335		#ifdef __LITTLE_ENDIAN__
336		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmmlaq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
337		float32x4_t __ret;
338		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmmlaq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
339		return __ret;
340		}
341		#else
342		__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmmlaq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
343		float32x4_t __ret;
344		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
345		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
346		bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
347		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmmlaq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
348		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
349		return __ret;
350		}
351		#endif
352
353		#ifdef __LITTLE_ENDIAN__
354		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcombine_bf16(bfloat16x4_t __p0, bfloat16x4_t __p1) {
355		bfloat16x8_t __ret;
356		__ret = __builtin_shufflevector(__p0, __p1, 0, 1, 2, 3, 4, 5, 6, 7);
357		return __ret;
358		}
359		#else
360		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcombine_bf16(bfloat16x4_t __p0, bfloat16x4_t __p1) {
361		bfloat16x8_t __ret;
362		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
363		bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
364		__ret = __builtin_shufflevector(__rev0, __rev1, 0, 1, 2, 3, 4, 5, 6, 7);
365		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
366		return __ret;
367		}
368		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t __noswap_vcombine_bf16(bfloat16x4_t __p0, bfloat16x4_t __p1) {
369		bfloat16x8_t __ret;
370		__ret = __builtin_shufflevector(__p0, __p1, 0, 1, 2, 3, 4, 5, 6, 7);
371		return __ret;
372		}
373		#endif
374
375		#define vcreate_bf16(__p0) __extension__ ({ \
376		bfloat16x4_t __ret; \
377		uint64_t __promote = __p0; \
378		__ret = __builtin_bit_cast(bfloat16x4_t, __promote); \
379		__ret; \
380		})
381		__ai __attribute__((target("bf16,neon"))) float32_t vcvtah_f32_bf16(bfloat16_t __p0) {
382		float32_t __ret;
383		__ret = __builtin_bit_cast(float32_t, (uint32_t)(__builtin_bit_cast(uint16_t, __p0)) << 16);
384		return __ret;
385		}
386		__ai __attribute__((target("bf16,neon"))) bfloat16_t vcvth_bf16_f32(float32_t __p0) {
387		bfloat16_t __ret;
388		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vcvth_bf16_f32(__p0));
389		return __ret;
390		}
391		#ifdef __LITTLE_ENDIAN__
392		#define vduph_lane_bf16(__p0, __p1) __extension__ ({ \
393		bfloat16_t __ret; \
394		bfloat16x4_t __s0 = __p0; \
395		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_lane_bf16(__s0, __p1)); \
396		__ret; \
397		})
398		#else
399		#define vduph_lane_bf16(__p0, __p1) __extension__ ({ \
400		bfloat16_t __ret; \
401		bfloat16x4_t __s0 = __p0; \
402		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
403		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_lane_bf16(__rev0, __p1)); \
404		__ret; \
405		})
406		#endif
407
408		#ifdef __LITTLE_ENDIAN__
409		#define vdupq_lane_bf16(__p0_0, __p1_0) __extension__ ({ \
410		bfloat16x8_t __ret_0; \
411		bfloat16x4_t __s0_0 = __p0_0; \
412		__ret_0 = splatq_lane_bf16(__s0_0, __p1_0); \
413		__ret_0; \
414		})
415		#else
416		#define vdupq_lane_bf16(__p0_1, __p1_1) __extension__ ({ \
417		bfloat16x8_t __ret_1; \
418		bfloat16x4_t __s0_1 = __p0_1; \
419		bfloat16x4_t __rev0_1; __rev0_1 = __builtin_shufflevector(__s0_1, __s0_1, __lane_reverse_64_16); \
420		__ret_1 = __noswap_splatq_lane_bf16(__rev0_1, __p1_1); \
421		__ret_1 = __builtin_shufflevector(__ret_1, __ret_1, __lane_reverse_128_16); \
422		__ret_1; \
423		})
424		#endif
425
426		#ifdef __LITTLE_ENDIAN__
427		#define vdup_lane_bf16(__p0_2, __p1_2) __extension__ ({ \
428		bfloat16x4_t __ret_2; \
429		bfloat16x4_t __s0_2 = __p0_2; \
430		__ret_2 = splat_lane_bf16(__s0_2, __p1_2); \
431		__ret_2; \
432		})
433		#else
434		#define vdup_lane_bf16(__p0_3, __p1_3) __extension__ ({ \
435		bfloat16x4_t __ret_3; \
436		bfloat16x4_t __s0_3 = __p0_3; \
437		bfloat16x4_t __rev0_3; __rev0_3 = __builtin_shufflevector(__s0_3, __s0_3, __lane_reverse_64_16); \
438		__ret_3 = __noswap_splat_lane_bf16(__rev0_3, __p1_3); \
439		__ret_3 = __builtin_shufflevector(__ret_3, __ret_3, __lane_reverse_64_16); \
440		__ret_3; \
441		})
442		#endif
443
444		#ifdef __LITTLE_ENDIAN__
445		#define vduph_laneq_bf16(__p0, __p1) __extension__ ({ \
446		bfloat16_t __ret; \
447		bfloat16x8_t __s0 = __p0; \
448		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_laneq_bf16(__s0, __p1)); \
449		__ret; \
450		})
451		#else
452		#define vduph_laneq_bf16(__p0, __p1) __extension__ ({ \
453		bfloat16_t __ret; \
454		bfloat16x8_t __s0 = __p0; \
455		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
456		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_laneq_bf16(__rev0, __p1)); \
457		__ret; \
458		})
459		#endif
460
461		#ifdef __LITTLE_ENDIAN__
462		#define vdupq_laneq_bf16(__p0_4, __p1_4) __extension__ ({ \
463		bfloat16x8_t __ret_4; \
464		bfloat16x8_t __s0_4 = __p0_4; \
465		__ret_4 = splatq_laneq_bf16(__s0_4, __p1_4); \
466		__ret_4; \
467		})
468		#else
469		#define vdupq_laneq_bf16(__p0_5, __p1_5) __extension__ ({ \
470		bfloat16x8_t __ret_5; \
471		bfloat16x8_t __s0_5 = __p0_5; \
472		bfloat16x8_t __rev0_5; __rev0_5 = __builtin_shufflevector(__s0_5, __s0_5, __lane_reverse_128_16); \
473		__ret_5 = __noswap_splatq_laneq_bf16(__rev0_5, __p1_5); \
474		__ret_5 = __builtin_shufflevector(__ret_5, __ret_5, __lane_reverse_128_16); \
475		__ret_5; \
476		})
477		#endif
478
479		#ifdef __LITTLE_ENDIAN__
480		#define vdup_laneq_bf16(__p0_6, __p1_6) __extension__ ({ \
481		bfloat16x4_t __ret_6; \
482		bfloat16x8_t __s0_6 = __p0_6; \
483		__ret_6 = splat_laneq_bf16(__s0_6, __p1_6); \
484		__ret_6; \
485		})
486		#else
487		#define vdup_laneq_bf16(__p0_7, __p1_7) __extension__ ({ \
488		bfloat16x4_t __ret_7; \
489		bfloat16x8_t __s0_7 = __p0_7; \
490		bfloat16x8_t __rev0_7; __rev0_7 = __builtin_shufflevector(__s0_7, __s0_7, __lane_reverse_128_16); \
491		__ret_7 = __noswap_splat_laneq_bf16(__rev0_7, __p1_7); \
492		__ret_7 = __builtin_shufflevector(__ret_7, __ret_7, __lane_reverse_64_16); \
493		__ret_7; \
494		})
495		#endif
496
497		#ifdef __LITTLE_ENDIAN__
498		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vdupq_n_bf16(bfloat16_t __p0) {
499		bfloat16x8_t __ret;
500		__ret = (bfloat16x8_t) {__p0, __p0, __p0, __p0, __p0, __p0, __p0, __p0};
501		return __ret;
502		}
503		#else
504		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vdupq_n_bf16(bfloat16_t __p0) {
505		bfloat16x8_t __ret;
506		__ret = (bfloat16x8_t) {__p0, __p0, __p0, __p0, __p0, __p0, __p0, __p0};
507		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
508		return __ret;
509		}
510		#endif
511
512		#ifdef __LITTLE_ENDIAN__
513		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vdup_n_bf16(bfloat16_t __p0) {
514		bfloat16x4_t __ret;
515		__ret = (bfloat16x4_t) {__p0, __p0, __p0, __p0};
516		return __ret;
517		}
518		#else
519		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vdup_n_bf16(bfloat16_t __p0) {
520		bfloat16x4_t __ret;
521		__ret = (bfloat16x4_t) {__p0, __p0, __p0, __p0};
522		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
523		return __ret;
524		}
525		#endif
526
527		#ifdef __LITTLE_ENDIAN__
528		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vget_high_bf16(bfloat16x8_t __p0) {
529		bfloat16x4_t __ret;
530		__ret = __builtin_shufflevector(__p0, __p0, 4, 5, 6, 7);
531		return __ret;
532		}
533		#else
534		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vget_high_bf16(bfloat16x8_t __p0) {
535		bfloat16x4_t __ret;
536		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
537		__ret = __builtin_shufflevector(__rev0, __rev0, 4, 5, 6, 7);
538		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
539		return __ret;
540		}
541		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t __noswap_vget_high_bf16(bfloat16x8_t __p0) {
542		bfloat16x4_t __ret;
543		__ret = __builtin_shufflevector(__p0, __p0, 4, 5, 6, 7);
544		return __ret;
545		}
546		#endif
547
548		#ifdef __LITTLE_ENDIAN__
549		#define vgetq_lane_bf16(__p0, __p1) __extension__ ({ \
550		bfloat16_t __ret; \
551		bfloat16x8_t __s0 = __p0; \
552		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vgetq_lane_bf16(__s0, __p1)); \
553		__ret; \
554		})
555		#else
556		#define vgetq_lane_bf16(__p0, __p1) __extension__ ({ \
557		bfloat16_t __ret; \
558		bfloat16x8_t __s0 = __p0; \
559		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
560		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vgetq_lane_bf16(__rev0, __p1)); \
561		__ret; \
562		})
563		#define __noswap_vgetq_lane_bf16(__p0, __p1) __extension__ ({ \
564		bfloat16_t __ret; \
565		bfloat16x8_t __s0 = __p0; \
566		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vgetq_lane_bf16(__s0, __p1)); \
567		__ret; \
568		})
569		#endif
570
571		#ifdef __LITTLE_ENDIAN__
572		#define vget_lane_bf16(__p0, __p1) __extension__ ({ \
573		bfloat16_t __ret; \
574		bfloat16x4_t __s0 = __p0; \
575		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vget_lane_bf16(__s0, __p1)); \
576		__ret; \
577		})
578		#else
579		#define vget_lane_bf16(__p0, __p1) __extension__ ({ \
580		bfloat16_t __ret; \
581		bfloat16x4_t __s0 = __p0; \
582		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
583		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vget_lane_bf16(__rev0, __p1)); \
584		__ret; \
585		})
586		#define __noswap_vget_lane_bf16(__p0, __p1) __extension__ ({ \
587		bfloat16_t __ret; \
588		bfloat16x4_t __s0 = __p0; \
589		__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vget_lane_bf16(__s0, __p1)); \
590		__ret; \
591		})
592		#endif
593
594		#ifdef __LITTLE_ENDIAN__
595		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vget_low_bf16(bfloat16x8_t __p0) {
596		bfloat16x4_t __ret;
597		__ret = __builtin_shufflevector(__p0, __p0, 0, 1, 2, 3);
598		return __ret;
599		}
600		#else
601		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vget_low_bf16(bfloat16x8_t __p0) {
602		bfloat16x4_t __ret;
603		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
604		__ret = __builtin_shufflevector(__rev0, __rev0, 0, 1, 2, 3);
605		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
606		return __ret;
607		}
608		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t __noswap_vget_low_bf16(bfloat16x8_t __p0) {
609		bfloat16x4_t __ret;
610		__ret = __builtin_shufflevector(__p0, __p0, 0, 1, 2, 3);
611		return __ret;
612		}
613		#endif
614
615		#ifdef __LITTLE_ENDIAN__
616		#define vld1q_bf16(__p0) __extension__ ({ \
617		bfloat16x8_t __ret; \
618		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_bf16(__p0, 43)); \
619		__ret; \
620		})
621		#else
622		#define vld1q_bf16(__p0) __extension__ ({ \
623		bfloat16x8_t __ret; \
624		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_bf16(__p0, 43)); \
625		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
626		__ret; \
627		})
628		#endif
629
630		#ifdef __LITTLE_ENDIAN__
631		#define vld1_bf16(__p0) __extension__ ({ \
632		bfloat16x4_t __ret; \
633		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_bf16(__p0, 11)); \
634		__ret; \
635		})
636		#else
637		#define vld1_bf16(__p0) __extension__ ({ \
638		bfloat16x4_t __ret; \
639		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_bf16(__p0, 11)); \
640		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
641		__ret; \
642		})
643		#endif
644
645		#ifdef __LITTLE_ENDIAN__
646		#define vld1q_dup_bf16(__p0) __extension__ ({ \
647		bfloat16x8_t __ret; \
648		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_dup_bf16(__p0, 43)); \
649		__ret; \
650		})
651		#else
652		#define vld1q_dup_bf16(__p0) __extension__ ({ \
653		bfloat16x8_t __ret; \
654		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_dup_bf16(__p0, 43)); \
655		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
656		__ret; \
657		})
658		#endif
659
660		#ifdef __LITTLE_ENDIAN__
661		#define vld1_dup_bf16(__p0) __extension__ ({ \
662		bfloat16x4_t __ret; \
663		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_dup_bf16(__p0, 11)); \
664		__ret; \
665		})
666		#else
667		#define vld1_dup_bf16(__p0) __extension__ ({ \
668		bfloat16x4_t __ret; \
669		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_dup_bf16(__p0, 11)); \
670		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
671		__ret; \
672		})
673		#endif
674
675		#ifdef __LITTLE_ENDIAN__
676		#define vld1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
677		bfloat16x8_t __ret; \
678		bfloat16x8_t __s1 = __p1; \
679		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
680		__ret; \
681		})
682		#else
683		#define vld1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
684		bfloat16x8_t __ret; \
685		bfloat16x8_t __s1 = __p1; \
686		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
687		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
688		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
689		__ret; \
690		})
691		#endif
692
693		#ifdef __LITTLE_ENDIAN__
694		#define vld1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
695		bfloat16x4_t __ret; \
696		bfloat16x4_t __s1 = __p1; \
697		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1), __p2, 11)); \
698		__ret; \
699		})
700		#else
701		#define vld1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
702		bfloat16x4_t __ret; \
703		bfloat16x4_t __s1 = __p1; \
704		bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
705		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1), __p2, 11)); \
706		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
707		__ret; \
708		})
709		#endif
710
711		#ifdef __LITTLE_ENDIAN__
712		#define vld1q_bf16_x2(__p0) __extension__ ({ \
713		bfloat16x8x2_t __ret; \
714		__builtin_neon_vld1q_bf16_x2(&__ret, __p0, 43); \
715		__ret; \
716		})
717		#else
718		#define vld1q_bf16_x2(__p0) __extension__ ({ \
719		bfloat16x8x2_t __ret; \
720		__builtin_neon_vld1q_bf16_x2(&__ret, __p0, 43); \
721		\
722		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
723		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
724		__ret; \
725		})
726		#endif
727
728		#ifdef __LITTLE_ENDIAN__
729		#define vld1_bf16_x2(__p0) __extension__ ({ \
730		bfloat16x4x2_t __ret; \
731		__builtin_neon_vld1_bf16_x2(&__ret, __p0, 11); \
732		__ret; \
733		})
734		#else
735		#define vld1_bf16_x2(__p0) __extension__ ({ \
736		bfloat16x4x2_t __ret; \
737		__builtin_neon_vld1_bf16_x2(&__ret, __p0, 11); \
738		\
739		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
740		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
741		__ret; \
742		})
743		#endif
744
745		#ifdef __LITTLE_ENDIAN__
746		#define vld1q_bf16_x3(__p0) __extension__ ({ \
747		bfloat16x8x3_t __ret; \
748		__builtin_neon_vld1q_bf16_x3(&__ret, __p0, 43); \
749		__ret; \
750		})
751		#else
752		#define vld1q_bf16_x3(__p0) __extension__ ({ \
753		bfloat16x8x3_t __ret; \
754		__builtin_neon_vld1q_bf16_x3(&__ret, __p0, 43); \
755		\
756		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
757		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
758		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
759		__ret; \
760		})
761		#endif
762
763		#ifdef __LITTLE_ENDIAN__
764		#define vld1_bf16_x3(__p0) __extension__ ({ \
765		bfloat16x4x3_t __ret; \
766		__builtin_neon_vld1_bf16_x3(&__ret, __p0, 11); \
767		__ret; \
768		})
769		#else
770		#define vld1_bf16_x3(__p0) __extension__ ({ \
771		bfloat16x4x3_t __ret; \
772		__builtin_neon_vld1_bf16_x3(&__ret, __p0, 11); \
773		\
774		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
775		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
776		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
777		__ret; \
778		})
779		#endif
780
781		#ifdef __LITTLE_ENDIAN__
782		#define vld1q_bf16_x4(__p0) __extension__ ({ \
783		bfloat16x8x4_t __ret; \
784		__builtin_neon_vld1q_bf16_x4(&__ret, __p0, 43); \
785		__ret; \
786		})
787		#else
788		#define vld1q_bf16_x4(__p0) __extension__ ({ \
789		bfloat16x8x4_t __ret; \
790		__builtin_neon_vld1q_bf16_x4(&__ret, __p0, 43); \
791		\
792		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
793		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
794		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
795		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
796		__ret; \
797		})
798		#endif
799
800		#ifdef __LITTLE_ENDIAN__
801		#define vld1_bf16_x4(__p0) __extension__ ({ \
802		bfloat16x4x4_t __ret; \
803		__builtin_neon_vld1_bf16_x4(&__ret, __p0, 11); \
804		__ret; \
805		})
806		#else
807		#define vld1_bf16_x4(__p0) __extension__ ({ \
808		bfloat16x4x4_t __ret; \
809		__builtin_neon_vld1_bf16_x4(&__ret, __p0, 11); \
810		\
811		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
812		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
813		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
814		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
815		__ret; \
816		})
817		#endif
818
819		#ifdef __LITTLE_ENDIAN__
820		#define vld2q_bf16(__p0) __extension__ ({ \
821		bfloat16x8x2_t __ret; \
822		__builtin_neon_vld2q_bf16(&__ret, __p0, 43); \
823		__ret; \
824		})
825		#else
826		#define vld2q_bf16(__p0) __extension__ ({ \
827		bfloat16x8x2_t __ret; \
828		__builtin_neon_vld2q_bf16(&__ret, __p0, 43); \
829		\
830		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
831		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
832		__ret; \
833		})
834		#endif
835
836		#ifdef __LITTLE_ENDIAN__
837		#define vld2_bf16(__p0) __extension__ ({ \
838		bfloat16x4x2_t __ret; \
839		__builtin_neon_vld2_bf16(&__ret, __p0, 11); \
840		__ret; \
841		})
842		#else
843		#define vld2_bf16(__p0) __extension__ ({ \
844		bfloat16x4x2_t __ret; \
845		__builtin_neon_vld2_bf16(&__ret, __p0, 11); \
846		\
847		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
848		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
849		__ret; \
850		})
851		#endif
852
853		#ifdef __LITTLE_ENDIAN__
854		#define vld2q_dup_bf16(__p0) __extension__ ({ \
855		bfloat16x8x2_t __ret; \
856		__builtin_neon_vld2q_dup_bf16(&__ret, __p0, 43); \
857		__ret; \
858		})
859		#else
860		#define vld2q_dup_bf16(__p0) __extension__ ({ \
861		bfloat16x8x2_t __ret; \
862		__builtin_neon_vld2q_dup_bf16(&__ret, __p0, 43); \
863		\
864		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
865		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
866		__ret; \
867		})
868		#endif
869
870		#ifdef __LITTLE_ENDIAN__
871		#define vld2_dup_bf16(__p0) __extension__ ({ \
872		bfloat16x4x2_t __ret; \
873		__builtin_neon_vld2_dup_bf16(&__ret, __p0, 11); \
874		__ret; \
875		})
876		#else
877		#define vld2_dup_bf16(__p0) __extension__ ({ \
878		bfloat16x4x2_t __ret; \
879		__builtin_neon_vld2_dup_bf16(&__ret, __p0, 11); \
880		\
881		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
882		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
883		__ret; \
884		})
885		#endif
886
887		#ifdef __LITTLE_ENDIAN__
888		#define vld2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
889		bfloat16x8x2_t __ret; \
890		bfloat16x8x2_t __s1 = __p1; \
891		__builtin_neon_vld2q_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __p2, 43); \
892		__ret; \
893		})
894		#else
895		#define vld2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
896		bfloat16x8x2_t __ret; \
897		bfloat16x8x2_t __s1 = __p1; \
898		bfloat16x8x2_t __rev1; \
899		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
900		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
901		__builtin_neon_vld2q_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __p2, 43); \
902		\
903		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
904		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
905		__ret; \
906		})
907		#endif
908
909		#ifdef __LITTLE_ENDIAN__
910		#define vld2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
911		bfloat16x4x2_t __ret; \
912		bfloat16x4x2_t __s1 = __p1; \
913		__builtin_neon_vld2_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __p2, 11); \
914		__ret; \
915		})
916		#else
917		#define vld2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
918		bfloat16x4x2_t __ret; \
919		bfloat16x4x2_t __s1 = __p1; \
920		bfloat16x4x2_t __rev1; \
921		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
922		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
923		__builtin_neon_vld2_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __p2, 11); \
924		\
925		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
926		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
927		__ret; \
928		})
929		#endif
930
931		#ifdef __LITTLE_ENDIAN__
932		#define vld3q_bf16(__p0) __extension__ ({ \
933		bfloat16x8x3_t __ret; \
934		__builtin_neon_vld3q_bf16(&__ret, __p0, 43); \
935		__ret; \
936		})
937		#else
938		#define vld3q_bf16(__p0) __extension__ ({ \
939		bfloat16x8x3_t __ret; \
940		__builtin_neon_vld3q_bf16(&__ret, __p0, 43); \
941		\
942		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
943		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
944		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
945		__ret; \
946		})
947		#endif
948
949		#ifdef __LITTLE_ENDIAN__
950		#define vld3_bf16(__p0) __extension__ ({ \
951		bfloat16x4x3_t __ret; \
952		__builtin_neon_vld3_bf16(&__ret, __p0, 11); \
953		__ret; \
954		})
955		#else
956		#define vld3_bf16(__p0) __extension__ ({ \
957		bfloat16x4x3_t __ret; \
958		__builtin_neon_vld3_bf16(&__ret, __p0, 11); \
959		\
960		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
961		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
962		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
963		__ret; \
964		})
965		#endif
966
967		#ifdef __LITTLE_ENDIAN__
968		#define vld3q_dup_bf16(__p0) __extension__ ({ \
969		bfloat16x8x3_t __ret; \
970		__builtin_neon_vld3q_dup_bf16(&__ret, __p0, 43); \
971		__ret; \
972		})
973		#else
974		#define vld3q_dup_bf16(__p0) __extension__ ({ \
975		bfloat16x8x3_t __ret; \
976		__builtin_neon_vld3q_dup_bf16(&__ret, __p0, 43); \
977		\
978		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
979		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
980		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
981		__ret; \
982		})
983		#endif
984
985		#ifdef __LITTLE_ENDIAN__
986		#define vld3_dup_bf16(__p0) __extension__ ({ \
987		bfloat16x4x3_t __ret; \
988		__builtin_neon_vld3_dup_bf16(&__ret, __p0, 11); \
989		__ret; \
990		})
991		#else
992		#define vld3_dup_bf16(__p0) __extension__ ({ \
993		bfloat16x4x3_t __ret; \
994		__builtin_neon_vld3_dup_bf16(&__ret, __p0, 11); \
995		\
996		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
997		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
998		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
999		__ret; \
1000		})
1001		#endif
1002
1003		#ifdef __LITTLE_ENDIAN__
1004		#define vld3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1005		bfloat16x8x3_t __ret; \
1006		bfloat16x8x3_t __s1 = __p1; \
1007		__builtin_neon_vld3q_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __p2, 43); \
1008		__ret; \
1009		})
1010		#else
1011		#define vld3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1012		bfloat16x8x3_t __ret; \
1013		bfloat16x8x3_t __s1 = __p1; \
1014		bfloat16x8x3_t __rev1; \
1015		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1016		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1017		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1018		__builtin_neon_vld3q_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __p2, 43); \
1019		\
1020		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
1021		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
1022		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
1023		__ret; \
1024		})
1025		#endif
1026
1027		#ifdef __LITTLE_ENDIAN__
1028		#define vld3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1029		bfloat16x4x3_t __ret; \
1030		bfloat16x4x3_t __s1 = __p1; \
1031		__builtin_neon_vld3_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __p2, 11); \
1032		__ret; \
1033		})
1034		#else
1035		#define vld3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1036		bfloat16x4x3_t __ret; \
1037		bfloat16x4x3_t __s1 = __p1; \
1038		bfloat16x4x3_t __rev1; \
1039		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1040		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1041		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1042		__builtin_neon_vld3_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __p2, 11); \
1043		\
1044		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
1045		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
1046		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
1047		__ret; \
1048		})
1049		#endif
1050
1051		#ifdef __LITTLE_ENDIAN__
1052		#define vld4q_bf16(__p0) __extension__ ({ \
1053		bfloat16x8x4_t __ret; \
1054		__builtin_neon_vld4q_bf16(&__ret, __p0, 43); \
1055		__ret; \
1056		})
1057		#else
1058		#define vld4q_bf16(__p0) __extension__ ({ \
1059		bfloat16x8x4_t __ret; \
1060		__builtin_neon_vld4q_bf16(&__ret, __p0, 43); \
1061		\
1062		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
1063		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
1064		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
1065		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
1066		__ret; \
1067		})
1068		#endif
1069
1070		#ifdef __LITTLE_ENDIAN__
1071		#define vld4_bf16(__p0) __extension__ ({ \
1072		bfloat16x4x4_t __ret; \
1073		__builtin_neon_vld4_bf16(&__ret, __p0, 11); \
1074		__ret; \
1075		})
1076		#else
1077		#define vld4_bf16(__p0) __extension__ ({ \
1078		bfloat16x4x4_t __ret; \
1079		__builtin_neon_vld4_bf16(&__ret, __p0, 11); \
1080		\
1081		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
1082		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
1083		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
1084		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
1085		__ret; \
1086		})
1087		#endif
1088
1089		#ifdef __LITTLE_ENDIAN__
1090		#define vld4q_dup_bf16(__p0) __extension__ ({ \
1091		bfloat16x8x4_t __ret; \
1092		__builtin_neon_vld4q_dup_bf16(&__ret, __p0, 43); \
1093		__ret; \
1094		})
1095		#else
1096		#define vld4q_dup_bf16(__p0) __extension__ ({ \
1097		bfloat16x8x4_t __ret; \
1098		__builtin_neon_vld4q_dup_bf16(&__ret, __p0, 43); \
1099		\
1100		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
1101		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
1102		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
1103		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
1104		__ret; \
1105		})
1106		#endif
1107
1108		#ifdef __LITTLE_ENDIAN__
1109		#define vld4_dup_bf16(__p0) __extension__ ({ \
1110		bfloat16x4x4_t __ret; \
1111		__builtin_neon_vld4_dup_bf16(&__ret, __p0, 11); \
1112		__ret; \
1113		})
1114		#else
1115		#define vld4_dup_bf16(__p0) __extension__ ({ \
1116		bfloat16x4x4_t __ret; \
1117		__builtin_neon_vld4_dup_bf16(&__ret, __p0, 11); \
1118		\
1119		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
1120		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
1121		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
1122		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
1123		__ret; \
1124		})
1125		#endif
1126
1127		#ifdef __LITTLE_ENDIAN__
1128		#define vld4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1129		bfloat16x8x4_t __ret; \
1130		bfloat16x8x4_t __s1 = __p1; \
1131		__builtin_neon_vld4q_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), __p2, 43); \
1132		__ret; \
1133		})
1134		#else
1135		#define vld4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1136		bfloat16x8x4_t __ret; \
1137		bfloat16x8x4_t __s1 = __p1; \
1138		bfloat16x8x4_t __rev1; \
1139		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1140		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1141		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1142		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
1143		__builtin_neon_vld4q_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), __p2, 43); \
1144		\
1145		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
1146		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
1147		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
1148		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
1149		__ret; \
1150		})
1151		#endif
1152
1153		#ifdef __LITTLE_ENDIAN__
1154		#define vld4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1155		bfloat16x4x4_t __ret; \
1156		bfloat16x4x4_t __s1 = __p1; \
1157		__builtin_neon_vld4_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), __p2, 11); \
1158		__ret; \
1159		})
1160		#else
1161		#define vld4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1162		bfloat16x4x4_t __ret; \
1163		bfloat16x4x4_t __s1 = __p1; \
1164		bfloat16x4x4_t __rev1; \
1165		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1166		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1167		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1168		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
1169		__builtin_neon_vld4_lane_bf16(&__ret, __p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), __p2, 11); \
1170		\
1171		__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
1172		__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
1173		__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
1174		__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
1175		__ret; \
1176		})
1177		#endif
1178
1179		#ifdef __LITTLE_ENDIAN__
1180		#define vsetq_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1181		bfloat16x8_t __ret; \
1182		bfloat16_t __s0 = __p0; \
1183		bfloat16x8_t __s1 = __p1; \
1184		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vsetq_lane_bf16(__s0, __s1, __p2)); \
1185		__ret; \
1186		})
1187		#else
1188		#define vsetq_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1189		bfloat16x8_t __ret; \
1190		bfloat16_t __s0 = __p0; \
1191		bfloat16x8_t __s1 = __p1; \
1192		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
1193		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vsetq_lane_bf16(__s0, __rev1, __p2)); \
1194		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
1195		__ret; \
1196		})
1197		#define __noswap_vsetq_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1198		bfloat16x8_t __ret; \
1199		bfloat16_t __s0 = __p0; \
1200		bfloat16x8_t __s1 = __p1; \
1201		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vsetq_lane_bf16(__s0, __s1, __p2)); \
1202		__ret; \
1203		})
1204		#endif
1205
1206		#ifdef __LITTLE_ENDIAN__
1207		#define vset_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1208		bfloat16x4_t __ret; \
1209		bfloat16_t __s0 = __p0; \
1210		bfloat16x4_t __s1 = __p1; \
1211		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vset_lane_bf16(__s0, __s1, __p2)); \
1212		__ret; \
1213		})
1214		#else
1215		#define vset_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1216		bfloat16x4_t __ret; \
1217		bfloat16_t __s0 = __p0; \
1218		bfloat16x4_t __s1 = __p1; \
1219		bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
1220		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vset_lane_bf16(__s0, __rev1, __p2)); \
1221		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
1222		__ret; \
1223		})
1224		#define __noswap_vset_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1225		bfloat16x4_t __ret; \
1226		bfloat16_t __s0 = __p0; \
1227		bfloat16x4_t __s1 = __p1; \
1228		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vset_lane_bf16(__s0, __s1, __p2)); \
1229		__ret; \
1230		})
1231		#endif
1232
1233		#ifdef __LITTLE_ENDIAN__
1234		#define vst1q_bf16(__p0, __p1) __extension__ ({ \
1235		bfloat16x8_t __s1 = __p1; \
1236		__builtin_neon_vst1q_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1), 43); \
1237		})
1238		#else
1239		#define vst1q_bf16(__p0, __p1) __extension__ ({ \
1240		bfloat16x8_t __s1 = __p1; \
1241		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
1242		__builtin_neon_vst1q_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1), 43); \
1243		})
1244		#endif
1245
1246		#ifdef __LITTLE_ENDIAN__
1247		#define vst1_bf16(__p0, __p1) __extension__ ({ \
1248		bfloat16x4_t __s1 = __p1; \
1249		__builtin_neon_vst1_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1), 11); \
1250		})
1251		#else
1252		#define vst1_bf16(__p0, __p1) __extension__ ({ \
1253		bfloat16x4_t __s1 = __p1; \
1254		bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
1255		__builtin_neon_vst1_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1), 11); \
1256		})
1257		#endif
1258
1259		#ifdef __LITTLE_ENDIAN__
1260		#define vst1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1261		bfloat16x8_t __s1 = __p1; \
1262		__builtin_neon_vst1q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1), __p2, 43); \
1263		})
1264		#else
1265		#define vst1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1266		bfloat16x8_t __s1 = __p1; \
1267		bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
1268		__builtin_neon_vst1q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1), __p2, 43); \
1269		})
1270		#endif
1271
1272		#ifdef __LITTLE_ENDIAN__
1273		#define vst1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1274		bfloat16x4_t __s1 = __p1; \
1275		__builtin_neon_vst1_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1), __p2, 11); \
1276		})
1277		#else
1278		#define vst1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1279		bfloat16x4_t __s1 = __p1; \
1280		bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
1281		__builtin_neon_vst1_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1), __p2, 11); \
1282		})
1283		#endif
1284
1285		#ifdef __LITTLE_ENDIAN__
1286		#define vst1q_bf16_x2(__p0, __p1) __extension__ ({ \
1287		bfloat16x8x2_t __s1 = __p1; \
1288		__builtin_neon_vst1q_bf16_x2(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), 43); \
1289		})
1290		#else
1291		#define vst1q_bf16_x2(__p0, __p1) __extension__ ({ \
1292		bfloat16x8x2_t __s1 = __p1; \
1293		bfloat16x8x2_t __rev1; \
1294		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1295		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1296		__builtin_neon_vst1q_bf16_x2(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), 43); \
1297		})
1298		#endif
1299
1300		#ifdef __LITTLE_ENDIAN__
1301		#define vst1_bf16_x2(__p0, __p1) __extension__ ({ \
1302		bfloat16x4x2_t __s1 = __p1; \
1303		__builtin_neon_vst1_bf16_x2(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), 11); \
1304		})
1305		#else
1306		#define vst1_bf16_x2(__p0, __p1) __extension__ ({ \
1307		bfloat16x4x2_t __s1 = __p1; \
1308		bfloat16x4x2_t __rev1; \
1309		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1310		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1311		__builtin_neon_vst1_bf16_x2(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), 11); \
1312		})
1313		#endif
1314
1315		#ifdef __LITTLE_ENDIAN__
1316		#define vst1q_bf16_x3(__p0, __p1) __extension__ ({ \
1317		bfloat16x8x3_t __s1 = __p1; \
1318		__builtin_neon_vst1q_bf16_x3(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), 43); \
1319		})
1320		#else
1321		#define vst1q_bf16_x3(__p0, __p1) __extension__ ({ \
1322		bfloat16x8x3_t __s1 = __p1; \
1323		bfloat16x8x3_t __rev1; \
1324		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1325		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1326		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1327		__builtin_neon_vst1q_bf16_x3(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), 43); \
1328		})
1329		#endif
1330
1331		#ifdef __LITTLE_ENDIAN__
1332		#define vst1_bf16_x3(__p0, __p1) __extension__ ({ \
1333		bfloat16x4x3_t __s1 = __p1; \
1334		__builtin_neon_vst1_bf16_x3(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), 11); \
1335		})
1336		#else
1337		#define vst1_bf16_x3(__p0, __p1) __extension__ ({ \
1338		bfloat16x4x3_t __s1 = __p1; \
1339		bfloat16x4x3_t __rev1; \
1340		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1341		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1342		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1343		__builtin_neon_vst1_bf16_x3(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), 11); \
1344		})
1345		#endif
1346
1347		#ifdef __LITTLE_ENDIAN__
1348		#define vst1q_bf16_x4(__p0, __p1) __extension__ ({ \
1349		bfloat16x8x4_t __s1 = __p1; \
1350		__builtin_neon_vst1q_bf16_x4(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), 43); \
1351		})
1352		#else
1353		#define vst1q_bf16_x4(__p0, __p1) __extension__ ({ \
1354		bfloat16x8x4_t __s1 = __p1; \
1355		bfloat16x8x4_t __rev1; \
1356		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1357		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1358		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1359		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
1360		__builtin_neon_vst1q_bf16_x4(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), 43); \
1361		})
1362		#endif
1363
1364		#ifdef __LITTLE_ENDIAN__
1365		#define vst1_bf16_x4(__p0, __p1) __extension__ ({ \
1366		bfloat16x4x4_t __s1 = __p1; \
1367		__builtin_neon_vst1_bf16_x4(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), 11); \
1368		})
1369		#else
1370		#define vst1_bf16_x4(__p0, __p1) __extension__ ({ \
1371		bfloat16x4x4_t __s1 = __p1; \
1372		bfloat16x4x4_t __rev1; \
1373		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1374		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1375		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1376		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
1377		__builtin_neon_vst1_bf16_x4(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), 11); \
1378		})
1379		#endif
1380
1381		#ifdef __LITTLE_ENDIAN__
1382		#define vst2q_bf16(__p0, __p1) __extension__ ({ \
1383		bfloat16x8x2_t __s1 = __p1; \
1384		__builtin_neon_vst2q_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), 43); \
1385		})
1386		#else
1387		#define vst2q_bf16(__p0, __p1) __extension__ ({ \
1388		bfloat16x8x2_t __s1 = __p1; \
1389		bfloat16x8x2_t __rev1; \
1390		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1391		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1392		__builtin_neon_vst2q_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), 43); \
1393		})
1394		#endif
1395
1396		#ifdef __LITTLE_ENDIAN__
1397		#define vst2_bf16(__p0, __p1) __extension__ ({ \
1398		bfloat16x4x2_t __s1 = __p1; \
1399		__builtin_neon_vst2_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), 11); \
1400		})
1401		#else
1402		#define vst2_bf16(__p0, __p1) __extension__ ({ \
1403		bfloat16x4x2_t __s1 = __p1; \
1404		bfloat16x4x2_t __rev1; \
1405		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1406		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1407		__builtin_neon_vst2_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), 11); \
1408		})
1409		#endif
1410
1411		#ifdef __LITTLE_ENDIAN__
1412		#define vst2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1413		bfloat16x8x2_t __s1 = __p1; \
1414		__builtin_neon_vst2q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __p2, 43); \
1415		})
1416		#else
1417		#define vst2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1418		bfloat16x8x2_t __s1 = __p1; \
1419		bfloat16x8x2_t __rev1; \
1420		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1421		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1422		__builtin_neon_vst2q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __p2, 43); \
1423		})
1424		#endif
1425
1426		#ifdef __LITTLE_ENDIAN__
1427		#define vst2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1428		bfloat16x4x2_t __s1 = __p1; \
1429		__builtin_neon_vst2_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __p2, 11); \
1430		})
1431		#else
1432		#define vst2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1433		bfloat16x4x2_t __s1 = __p1; \
1434		bfloat16x4x2_t __rev1; \
1435		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1436		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1437		__builtin_neon_vst2_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __p2, 11); \
1438		})
1439		#endif
1440
1441		#ifdef __LITTLE_ENDIAN__
1442		#define vst3q_bf16(__p0, __p1) __extension__ ({ \
1443		bfloat16x8x3_t __s1 = __p1; \
1444		__builtin_neon_vst3q_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), 43); \
1445		})
1446		#else
1447		#define vst3q_bf16(__p0, __p1) __extension__ ({ \
1448		bfloat16x8x3_t __s1 = __p1; \
1449		bfloat16x8x3_t __rev1; \
1450		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1451		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1452		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1453		__builtin_neon_vst3q_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), 43); \
1454		})
1455		#endif
1456
1457		#ifdef __LITTLE_ENDIAN__
1458		#define vst3_bf16(__p0, __p1) __extension__ ({ \
1459		bfloat16x4x3_t __s1 = __p1; \
1460		__builtin_neon_vst3_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), 11); \
1461		})
1462		#else
1463		#define vst3_bf16(__p0, __p1) __extension__ ({ \
1464		bfloat16x4x3_t __s1 = __p1; \
1465		bfloat16x4x3_t __rev1; \
1466		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1467		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1468		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1469		__builtin_neon_vst3_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), 11); \
1470		})
1471		#endif
1472
1473		#ifdef __LITTLE_ENDIAN__
1474		#define vst3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1475		bfloat16x8x3_t __s1 = __p1; \
1476		__builtin_neon_vst3q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __p2, 43); \
1477		})
1478		#else
1479		#define vst3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1480		bfloat16x8x3_t __s1 = __p1; \
1481		bfloat16x8x3_t __rev1; \
1482		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1483		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1484		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1485		__builtin_neon_vst3q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __p2, 43); \
1486		})
1487		#endif
1488
1489		#ifdef __LITTLE_ENDIAN__
1490		#define vst3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1491		bfloat16x4x3_t __s1 = __p1; \
1492		__builtin_neon_vst3_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __p2, 11); \
1493		})
	148	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfdotq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	149	float32x4_t __ret;
	150	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfdotq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	151	return __ret;
	152	}
1494	153	#else
1495		#define vst3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1496		bfloat16x4x3_t __s1 = __p1; \
1497		bfloat16x4x3_t __rev1; \
1498		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1499		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1500		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1501		__builtin_neon_vst3_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __p2, 11); \
1502		})
	154	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfdotq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	155	float32x4_t __ret;
	156	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	157	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	158	bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	159	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfdotq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
	160	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
	161	return __ret;
	162	}
	163	__ai __attribute__((target("bf16,neon"))) float32x4_t __noswap_vbfdotq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	164	float32x4_t __ret;
	165	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfdotq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	166	return __ret;
	167	}
1503	168	#endif
1504	169
1505	170	#ifdef __LITTLE_ENDIAN__
1506		#define vst4q_bf16(__p0, __p1) __extension__ ({ \
1507		bfloat16x8x4_t __s1 = __p1; \
1508		__builtin_neon_vst4q_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), 43); \
1509		})
	171	__ai __attribute__((target("bf16,neon"))) float32x2_t vbfdot_f32(float32x2_t __p0, bfloat16x4_t __p1, bfloat16x4_t __p2) {
	172	float32x2_t __ret;
	173	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vbfdot_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), __builtin_bit_cast(int8x8_t, __p2), 9));
	174	return __ret;
	175	}
1510	176	#else
1511		#define vst4q_bf16(__p0, __p1) __extension__ ({ \
1512		bfloat16x8x4_t __s1 = __p1; \
1513		bfloat16x8x4_t __rev1; \
1514		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1515		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1516		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1517		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
1518		__builtin_neon_vst4q_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), 43); \
1519		})
	177	__ai __attribute__((target("bf16,neon"))) float32x2_t vbfdot_f32(float32x2_t __p0, bfloat16x4_t __p1, bfloat16x4_t __p2) {
	178	float32x2_t __ret;
	179	float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
	180	bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
	181	bfloat16x4_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_64_16);
	182	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vbfdot_f32(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __builtin_bit_cast(int8x8_t, __rev2), 9));
	183	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
	184	return __ret;
	185	}
	186	__ai __attribute__((target("bf16,neon"))) float32x2_t __noswap_vbfdot_f32(float32x2_t __p0, bfloat16x4_t __p1, bfloat16x4_t __p2) {
	187	float32x2_t __ret;
	188	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vbfdot_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), __builtin_bit_cast(int8x8_t, __p2), 9));
	189	return __ret;
	190	}
1520	191	#endif
1521	192
1522	193	#ifdef __LITTLE_ENDIAN__
1523		#define vst4_bf16(__p0, __p1) __extension__ ({ \
1524		bfloat16x4x4_t __s1 = __p1; \
1525		__builtin_neon_vst4_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), 11); \
1526		})
	194	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlalbq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	195	float32x4_t __ret;
	196	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlalbq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	197	return __ret;
	198	}
1527	199	#else
1528		#define vst4_bf16(__p0, __p1) __extension__ ({ \
1529		bfloat16x4x4_t __s1 = __p1; \
1530		bfloat16x4x4_t __rev1; \
1531		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1532		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1533		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1534		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
1535		__builtin_neon_vst4_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), 11); \
1536		})
	200	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlalbq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	201	float32x4_t __ret;
	202	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	203	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	204	bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	205	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlalbq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
	206	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
	207	return __ret;
	208	}
	209	__ai __attribute__((target("bf16,neon"))) float32x4_t __noswap_vbfmlalbq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	210	float32x4_t __ret;
	211	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlalbq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	212	return __ret;
	213	}
1537	214	#endif
1538	215
1539	216	#ifdef __LITTLE_ENDIAN__
1540		#define vst4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1541		bfloat16x8x4_t __s1 = __p1; \
1542		__builtin_neon_vst4q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), __p2, 43); \
1543		})
	217	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlaltq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	218	float32x4_t __ret;
	219	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlaltq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	220	return __ret;
	221	}
1544	222	#else
1545		#define vst4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1546		bfloat16x8x4_t __s1 = __p1; \
1547		bfloat16x8x4_t __rev1; \
1548		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
1549		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
1550		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
1551		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
1552		__builtin_neon_vst4q_lane_bf16(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), __p2, 43); \
1553		})
	223	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmlaltq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	224	float32x4_t __ret;
	225	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	226	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	227	bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	228	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlaltq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
	229	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
	230	return __ret;
	231	}
	232	__ai __attribute__((target("bf16,neon"))) float32x4_t __noswap_vbfmlaltq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	233	float32x4_t __ret;
	234	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmlaltq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	235	return __ret;
	236	}
1554	237	#endif
1555	238
1556	239	#ifdef __LITTLE_ENDIAN__
1557		#define vst4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1558		bfloat16x4x4_t __s1 = __p1; \
1559		__builtin_neon_vst4_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), __p2, 11); \
1560		})
	240	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmmlaq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	241	float32x4_t __ret;
	242	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmmlaq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	243	return __ret;
	244	}
1561	245	#else
1562		#define vst4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
1563		bfloat16x4x4_t __s1 = __p1; \
1564		bfloat16x4x4_t __rev1; \
1565		__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
1566		__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
1567		__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
1568		__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
1569		__builtin_neon_vst4_lane_bf16(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), __p2, 11); \
1570		})
	246	__ai __attribute__((target("bf16,neon"))) float32x4_t vbfmmlaq_f32(float32x4_t __p0, bfloat16x8_t __p1, bfloat16x8_t __p2) {
	247	float32x4_t __ret;
	248	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	249	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	250	bfloat16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	251	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vbfmmlaq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
	252	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
	253	return __ret;
	254	}
1571	255	#endif
1572	256
	257	__ai __attribute__((target("bf16,neon"))) float32_t vcvtah_f32_bf16(bfloat16_t __p0) {
	258	float32_t __ret;
	259	__ret = __builtin_bit_cast(float32_t, (uint32_t)(__builtin_bit_cast(uint16_t, __p0)) << 16);
	260	return __ret;
	261	}
	262	__ai __attribute__((target("bf16,neon"))) bfloat16_t vcvth_bf16_f32(float32_t __p0) {
	263	bfloat16_t __ret;
	264	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vcvth_bf16_f32(__p0));
	265	return __ret;
	266	}
1573	267	#ifdef __LITTLE_ENDIAN__
1574	268	__ai __attribute__((target("dotprod,neon"))) uint32x4_t vdotq_u32(uint32x4_t __p0, uint8x16_t __p1, uint8x16_t __p2) {
1575	269	uint32x4_t __ret;
...	...	@@ -3925,6 +2619,54 @@ __ai __attribute__((target("i8mm,neon"))) int32x4_t vusmmlaq_s32(int32x4_t __p0,
3925	2619	})
3926	2620	#endif
3927	2621
	2622	#ifdef __LITTLE_ENDIAN__
	2623	#define splatq_lane_bf16(__p0, __p1) __extension__ ({ \
	2624	bfloat16x8_t __ret; \
	2625	bfloat16x4_t __s0 = __p0; \
	2626	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_lane_v(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
	2627	__ret; \
	2628	})
	2629	#else
	2630	#define splatq_lane_bf16(__p0, __p1) __extension__ ({ \
	2631	bfloat16x8_t __ret; \
	2632	bfloat16x4_t __s0 = __p0; \
	2633	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	2634	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_lane_v(__builtin_bit_cast(int8x8_t, __rev0), __p1, 11)); \
	2635	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	2636	__ret; \
	2637	})
	2638	#define __noswap_splatq_lane_bf16(__p0, __p1) __extension__ ({ \
	2639	bfloat16x8_t __ret; \
	2640	bfloat16x4_t __s0 = __p0; \
	2641	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_lane_v(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
	2642	__ret; \
	2643	})
	2644	#endif
	2645
	2646	#ifdef __LITTLE_ENDIAN__
	2647	#define splat_lane_bf16(__p0, __p1) __extension__ ({ \
	2648	bfloat16x4_t __ret; \
	2649	bfloat16x4_t __s0 = __p0; \
	2650	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_lane_v(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
	2651	__ret; \
	2652	})
	2653	#else
	2654	#define splat_lane_bf16(__p0, __p1) __extension__ ({ \
	2655	bfloat16x4_t __ret; \
	2656	bfloat16x4_t __s0 = __p0; \
	2657	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	2658	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_lane_v(__builtin_bit_cast(int8x8_t, __rev0), __p1, 11)); \
	2659	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	2660	__ret; \
	2661	})
	2662	#define __noswap_splat_lane_bf16(__p0, __p1) __extension__ ({ \
	2663	bfloat16x4_t __ret; \
	2664	bfloat16x4_t __s0 = __p0; \
	2665	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_lane_v(__builtin_bit_cast(int8x8_t, __s0), __p1, 11)); \
	2666	__ret; \
	2667	})
	2668	#endif
	2669
3928	2670	#ifdef __LITTLE_ENDIAN__
3929	2671	#define splat_laneq_p8(__p0, __p1) __extension__ ({ \
3930	2672	poly8x8_t __ret; \
...	...	@@ -4593,6 +3335,54 @@ __ai __attribute__((target("i8mm,neon"))) int32x4_t vusmmlaq_s32(int32x4_t __p0,
4593	3335	})
4594	3336	#endif
4595	3337
	3338	#ifdef __LITTLE_ENDIAN__
	3339	#define splatq_laneq_bf16(__p0, __p1) __extension__ ({ \
	3340	bfloat16x8_t __ret; \
	3341	bfloat16x8_t __s0 = __p0; \
	3342	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_laneq_v(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
	3343	__ret; \
	3344	})
	3345	#else
	3346	#define splatq_laneq_bf16(__p0, __p1) __extension__ ({ \
	3347	bfloat16x8_t __ret; \
	3348	bfloat16x8_t __s0 = __p0; \
	3349	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	3350	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_laneq_v(__builtin_bit_cast(int8x16_t, __rev0), __p1, 43)); \
	3351	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	3352	__ret; \
	3353	})
	3354	#define __noswap_splatq_laneq_bf16(__p0, __p1) __extension__ ({ \
	3355	bfloat16x8_t __ret; \
	3356	bfloat16x8_t __s0 = __p0; \
	3357	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_splatq_laneq_v(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
	3358	__ret; \
	3359	})
	3360	#endif
	3361
	3362	#ifdef __LITTLE_ENDIAN__
	3363	#define splat_laneq_bf16(__p0, __p1) __extension__ ({ \
	3364	bfloat16x4_t __ret; \
	3365	bfloat16x8_t __s0 = __p0; \
	3366	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_laneq_v(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
	3367	__ret; \
	3368	})
	3369	#else
	3370	#define splat_laneq_bf16(__p0, __p1) __extension__ ({ \
	3371	bfloat16x4_t __ret; \
	3372	bfloat16x8_t __s0 = __p0; \
	3373	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	3374	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_laneq_v(__builtin_bit_cast(int8x16_t, __rev0), __p1, 43)); \
	3375	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	3376	__ret; \
	3377	})
	3378	#define __noswap_splat_laneq_bf16(__p0, __p1) __extension__ ({ \
	3379	bfloat16x4_t __ret; \
	3380	bfloat16x8_t __s0 = __p0; \
	3381	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_splat_laneq_v(__builtin_bit_cast(int8x16_t, __s0), __p1, 43)); \
	3382	__ret; \
	3383	})
	3384	#endif
	3385
4596	3386	#ifdef __LITTLE_ENDIAN__
4597	3387	__ai __attribute__((target("neon"))) uint8x16_t vabdq_u8(uint8x16_t __p0, uint8x16_t __p1) {
4598	3388	uint8x16_t __ret;
...	...	@@ -8505,6 +7295,28 @@ __ai __attribute__((target("neon"))) int16x8_t __noswap_vcombine_s16(int16x4_t _
8505	7295	}
8506	7296	#endif
8507	7297
	7298	#ifdef __LITTLE_ENDIAN__
	7299	__ai __attribute__((target("neon"))) bfloat16x8_t vcombine_bf16(bfloat16x4_t __p0, bfloat16x4_t __p1) {
	7300	bfloat16x8_t __ret;
	7301	__ret = __builtin_shufflevector(__p0, __p1, 0, 1, 2, 3, 4, 5, 6, 7);
	7302	return __ret;
	7303	}
	7304	#else
	7305	__ai __attribute__((target("neon"))) bfloat16x8_t vcombine_bf16(bfloat16x4_t __p0, bfloat16x4_t __p1) {
	7306	bfloat16x8_t __ret;
	7307	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
	7308	bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
	7309	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 1, 2, 3, 4, 5, 6, 7);
	7310	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
	7311	return __ret;
	7312	}
	7313	__ai __attribute__((target("neon"))) bfloat16x8_t __noswap_vcombine_bf16(bfloat16x4_t __p0, bfloat16x4_t __p1) {
	7314	bfloat16x8_t __ret;
	7315	__ret = __builtin_shufflevector(__p0, __p1, 0, 1, 2, 3, 4, 5, 6, 7);
	7316	return __ret;
	7317	}
	7318	#endif
	7319
8508	7320	#define vcreate_p8(__p0) __extension__ ({ \
8509	7321	poly8x8_t __ret; \
8510	7322	uint64_t __promote = __p0; \
...	...	@@ -8577,6 +7389,12 @@ __ai __attribute__((target("neon"))) int16x8_t __noswap_vcombine_s16(int16x4_t _
8577	7389	__ret = __builtin_bit_cast(int16x4_t, __promote); \
8578	7390	__ret; \
8579	7391	})
	7392	#define vcreate_bf16(__p0) __extension__ ({ \
	7393	bfloat16x4_t __ret; \
	7394	uint64_t __promote = __p0; \
	7395	__ret = __builtin_bit_cast(bfloat16x4_t, __promote); \
	7396	__ret; \
	7397	})
8580	7398	#ifdef __LITTLE_ENDIAN__
8581	7399	__ai __attribute__((target("neon"))) float32x4_t vcvtq_f32_u32(uint32x4_t __p0) {
8582	7400	float32x4_t __ret;
...	...	@@ -8850,406 +7668,512 @@ __ai __attribute__((target("neon"))) uint32x2_t vcvt_u32_f32(float32x2_t __p0) {
8850	7668	#endif
8851	7669
8852	7670	#ifdef __LITTLE_ENDIAN__
8853		#define vdup_lane_p8(__p0_8, __p1_8) __extension__ ({ \
8854		poly8x8_t __ret_8; \
8855		poly8x8_t __s0_8 = __p0_8; \
8856		__ret_8 = splat_lane_p8(__s0_8, __p1_8); \
	7671	#define vduph_lane_bf16(__p0, __p1) __extension__ ({ \
	7672	bfloat16_t __ret; \
	7673	bfloat16x4_t __s0 = __p0; \
	7674	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_lane_bf16(__s0, __p1)); \
	7675	__ret; \
	7676	})
	7677	#else
	7678	#define vduph_lane_bf16(__p0, __p1) __extension__ ({ \
	7679	bfloat16_t __ret; \
	7680	bfloat16x4_t __s0 = __p0; \
	7681	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	7682	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_lane_bf16(__rev0, __p1)); \
	7683	__ret; \
	7684	})
	7685	#endif
	7686
	7687	#ifdef __LITTLE_ENDIAN__
	7688	#define vdup_lane_p8(__p0_0, __p1_0) __extension__ ({ \
	7689	poly8x8_t __ret_0; \
	7690	poly8x8_t __s0_0 = __p0_0; \
	7691	__ret_0 = splat_lane_p8(__s0_0, __p1_0); \
	7692	__ret_0; \
	7693	})
	7694	#else
	7695	#define vdup_lane_p8(__p0_1, __p1_1) __extension__ ({ \
	7696	poly8x8_t __ret_1; \
	7697	poly8x8_t __s0_1 = __p0_1; \
	7698	poly8x8_t __rev0_1; __rev0_1 = __builtin_shufflevector(__s0_1, __s0_1, __lane_reverse_64_8); \
	7699	__ret_1 = __noswap_splat_lane_p8(__rev0_1, __p1_1); \
	7700	__ret_1 = __builtin_shufflevector(__ret_1, __ret_1, __lane_reverse_64_8); \
	7701	__ret_1; \
	7702	})
	7703	#endif
	7704
	7705	#ifdef __LITTLE_ENDIAN__
	7706	#define vdup_lane_p16(__p0_2, __p1_2) __extension__ ({ \
	7707	poly16x4_t __ret_2; \
	7708	poly16x4_t __s0_2 = __p0_2; \
	7709	__ret_2 = splat_lane_p16(__s0_2, __p1_2); \
	7710	__ret_2; \
	7711	})
	7712	#else
	7713	#define vdup_lane_p16(__p0_3, __p1_3) __extension__ ({ \
	7714	poly16x4_t __ret_3; \
	7715	poly16x4_t __s0_3 = __p0_3; \
	7716	poly16x4_t __rev0_3; __rev0_3 = __builtin_shufflevector(__s0_3, __s0_3, __lane_reverse_64_16); \
	7717	__ret_3 = __noswap_splat_lane_p16(__rev0_3, __p1_3); \
	7718	__ret_3 = __builtin_shufflevector(__ret_3, __ret_3, __lane_reverse_64_16); \
	7719	__ret_3; \
	7720	})
	7721	#endif
	7722
	7723	#ifdef __LITTLE_ENDIAN__
	7724	#define vdupq_lane_p8(__p0_4, __p1_4) __extension__ ({ \
	7725	poly8x16_t __ret_4; \
	7726	poly8x8_t __s0_4 = __p0_4; \
	7727	__ret_4 = splatq_lane_p8(__s0_4, __p1_4); \
	7728	__ret_4; \
	7729	})
	7730	#else
	7731	#define vdupq_lane_p8(__p0_5, __p1_5) __extension__ ({ \
	7732	poly8x16_t __ret_5; \
	7733	poly8x8_t __s0_5 = __p0_5; \
	7734	poly8x8_t __rev0_5; __rev0_5 = __builtin_shufflevector(__s0_5, __s0_5, __lane_reverse_64_8); \
	7735	__ret_5 = __noswap_splatq_lane_p8(__rev0_5, __p1_5); \
	7736	__ret_5 = __builtin_shufflevector(__ret_5, __ret_5, __lane_reverse_128_8); \
	7737	__ret_5; \
	7738	})
	7739	#endif
	7740
	7741	#ifdef __LITTLE_ENDIAN__
	7742	#define vdupq_lane_p16(__p0_6, __p1_6) __extension__ ({ \
	7743	poly16x8_t __ret_6; \
	7744	poly16x4_t __s0_6 = __p0_6; \
	7745	__ret_6 = splatq_lane_p16(__s0_6, __p1_6); \
	7746	__ret_6; \
	7747	})
	7748	#else
	7749	#define vdupq_lane_p16(__p0_7, __p1_7) __extension__ ({ \
	7750	poly16x8_t __ret_7; \
	7751	poly16x4_t __s0_7 = __p0_7; \
	7752	poly16x4_t __rev0_7; __rev0_7 = __builtin_shufflevector(__s0_7, __s0_7, __lane_reverse_64_16); \
	7753	__ret_7 = __noswap_splatq_lane_p16(__rev0_7, __p1_7); \
	7754	__ret_7 = __builtin_shufflevector(__ret_7, __ret_7, __lane_reverse_128_16); \
	7755	__ret_7; \
	7756	})
	7757	#endif
	7758
	7759	#ifdef __LITTLE_ENDIAN__
	7760	#define vdupq_lane_u8(__p0_8, __p1_8) __extension__ ({ \
	7761	uint8x16_t __ret_8; \
	7762	uint8x8_t __s0_8 = __p0_8; \
	7763	__ret_8 = splatq_lane_u8(__s0_8, __p1_8); \
8857	7764	__ret_8; \
8858	7765	})
8859	7766	#else
8860		#define vdup_lane_p8(__p0_9, __p1_9) __extension__ ({ \
8861		poly8x8_t __ret_9; \
8862		poly8x8_t __s0_9 = __p0_9; \
8863		poly8x8_t __rev0_9; __rev0_9 = __builtin_shufflevector(__s0_9, __s0_9, __lane_reverse_64_8); \
8864		__ret_9 = __noswap_splat_lane_p8(__rev0_9, __p1_9); \
8865		__ret_9 = __builtin_shufflevector(__ret_9, __ret_9, __lane_reverse_64_8); \
	7767	#define vdupq_lane_u8(__p0_9, __p1_9) __extension__ ({ \
	7768	uint8x16_t __ret_9; \
	7769	uint8x8_t __s0_9 = __p0_9; \
	7770	uint8x8_t __rev0_9; __rev0_9 = __builtin_shufflevector(__s0_9, __s0_9, __lane_reverse_64_8); \
	7771	__ret_9 = __noswap_splatq_lane_u8(__rev0_9, __p1_9); \
	7772	__ret_9 = __builtin_shufflevector(__ret_9, __ret_9, __lane_reverse_128_8); \
8866	7773	__ret_9; \
8867	7774	})
8868	7775	#endif
8869	7776
8870	7777	#ifdef __LITTLE_ENDIAN__
8871		#define vdup_lane_p16(__p0_10, __p1_10) __extension__ ({ \
8872		poly16x4_t __ret_10; \
8873		poly16x4_t __s0_10 = __p0_10; \
8874		__ret_10 = splat_lane_p16(__s0_10, __p1_10); \
	7778	#define vdupq_lane_u32(__p0_10, __p1_10) __extension__ ({ \
	7779	uint32x4_t __ret_10; \
	7780	uint32x2_t __s0_10 = __p0_10; \
	7781	__ret_10 = splatq_lane_u32(__s0_10, __p1_10); \
8875	7782	__ret_10; \
8876	7783	})
8877	7784	#else
8878		#define vdup_lane_p16(__p0_11, __p1_11) __extension__ ({ \
8879		poly16x4_t __ret_11; \
8880		poly16x4_t __s0_11 = __p0_11; \
8881		poly16x4_t __rev0_11; __rev0_11 = __builtin_shufflevector(__s0_11, __s0_11, __lane_reverse_64_16); \
8882		__ret_11 = __noswap_splat_lane_p16(__rev0_11, __p1_11); \
8883		__ret_11 = __builtin_shufflevector(__ret_11, __ret_11, __lane_reverse_64_16); \
	7785	#define vdupq_lane_u32(__p0_11, __p1_11) __extension__ ({ \
	7786	uint32x4_t __ret_11; \
	7787	uint32x2_t __s0_11 = __p0_11; \
	7788	uint32x2_t __rev0_11; __rev0_11 = __builtin_shufflevector(__s0_11, __s0_11, __lane_reverse_64_32); \
	7789	__ret_11 = __noswap_splatq_lane_u32(__rev0_11, __p1_11); \
	7790	__ret_11 = __builtin_shufflevector(__ret_11, __ret_11, __lane_reverse_128_32); \
8884	7791	__ret_11; \
8885	7792	})
8886	7793	#endif
8887	7794
8888	7795	#ifdef __LITTLE_ENDIAN__
8889		#define vdupq_lane_p8(__p0_12, __p1_12) __extension__ ({ \
8890		poly8x16_t __ret_12; \
8891		poly8x8_t __s0_12 = __p0_12; \
8892		__ret_12 = splatq_lane_p8(__s0_12, __p1_12); \
	7796	#define vdupq_lane_u64(__p0_12, __p1_12) __extension__ ({ \
	7797	uint64x2_t __ret_12; \
	7798	uint64x1_t __s0_12 = __p0_12; \
	7799	__ret_12 = splatq_lane_u64(__s0_12, __p1_12); \
8893	7800	__ret_12; \
8894	7801	})
8895	7802	#else
8896		#define vdupq_lane_p8(__p0_13, __p1_13) __extension__ ({ \
8897		poly8x16_t __ret_13; \
8898		poly8x8_t __s0_13 = __p0_13; \
8899		poly8x8_t __rev0_13; __rev0_13 = __builtin_shufflevector(__s0_13, __s0_13, __lane_reverse_64_8); \
8900		__ret_13 = __noswap_splatq_lane_p8(__rev0_13, __p1_13); \
8901		__ret_13 = __builtin_shufflevector(__ret_13, __ret_13, __lane_reverse_128_8); \
	7803	#define vdupq_lane_u64(__p0_13, __p1_13) __extension__ ({ \
	7804	uint64x2_t __ret_13; \
	7805	uint64x1_t __s0_13 = __p0_13; \
	7806	__ret_13 = __noswap_splatq_lane_u64(__s0_13, __p1_13); \
	7807	__ret_13 = __builtin_shufflevector(__ret_13, __ret_13, __lane_reverse_128_64); \
8902	7808	__ret_13; \
8903	7809	})
8904	7810	#endif
8905	7811
8906	7812	#ifdef __LITTLE_ENDIAN__
8907		#define vdupq_lane_p16(__p0_14, __p1_14) __extension__ ({ \
8908		poly16x8_t __ret_14; \
8909		poly16x4_t __s0_14 = __p0_14; \
8910		__ret_14 = splatq_lane_p16(__s0_14, __p1_14); \
	7813	#define vdupq_lane_u16(__p0_14, __p1_14) __extension__ ({ \
	7814	uint16x8_t __ret_14; \
	7815	uint16x4_t __s0_14 = __p0_14; \
	7816	__ret_14 = splatq_lane_u16(__s0_14, __p1_14); \
8911	7817	__ret_14; \
8912	7818	})
8913	7819	#else
8914		#define vdupq_lane_p16(__p0_15, __p1_15) __extension__ ({ \
8915		poly16x8_t __ret_15; \
8916		poly16x4_t __s0_15 = __p0_15; \
8917		poly16x4_t __rev0_15; __rev0_15 = __builtin_shufflevector(__s0_15, __s0_15, __lane_reverse_64_16); \
8918		__ret_15 = __noswap_splatq_lane_p16(__rev0_15, __p1_15); \
	7820	#define vdupq_lane_u16(__p0_15, __p1_15) __extension__ ({ \
	7821	uint16x8_t __ret_15; \
	7822	uint16x4_t __s0_15 = __p0_15; \
	7823	uint16x4_t __rev0_15; __rev0_15 = __builtin_shufflevector(__s0_15, __s0_15, __lane_reverse_64_16); \
	7824	__ret_15 = __noswap_splatq_lane_u16(__rev0_15, __p1_15); \
8919	7825	__ret_15 = __builtin_shufflevector(__ret_15, __ret_15, __lane_reverse_128_16); \
8920	7826	__ret_15; \
8921	7827	})
8922	7828	#endif
8923	7829
8924	7830	#ifdef __LITTLE_ENDIAN__
8925		#define vdupq_lane_u8(__p0_16, __p1_16) __extension__ ({ \
8926		uint8x16_t __ret_16; \
8927		uint8x8_t __s0_16 = __p0_16; \
8928		__ret_16 = splatq_lane_u8(__s0_16, __p1_16); \
	7831	#define vdupq_lane_s8(__p0_16, __p1_16) __extension__ ({ \
	7832	int8x16_t __ret_16; \
	7833	int8x8_t __s0_16 = __p0_16; \
	7834	__ret_16 = splatq_lane_s8(__s0_16, __p1_16); \
8929	7835	__ret_16; \
8930	7836	})
8931	7837	#else
8932		#define vdupq_lane_u8(__p0_17, __p1_17) __extension__ ({ \
8933		uint8x16_t __ret_17; \
8934		uint8x8_t __s0_17 = __p0_17; \
8935		uint8x8_t __rev0_17; __rev0_17 = __builtin_shufflevector(__s0_17, __s0_17, __lane_reverse_64_8); \
8936		__ret_17 = __noswap_splatq_lane_u8(__rev0_17, __p1_17); \
	7838	#define vdupq_lane_s8(__p0_17, __p1_17) __extension__ ({ \
	7839	int8x16_t __ret_17; \
	7840	int8x8_t __s0_17 = __p0_17; \
	7841	int8x8_t __rev0_17; __rev0_17 = __builtin_shufflevector(__s0_17, __s0_17, __lane_reverse_64_8); \
	7842	__ret_17 = __noswap_splatq_lane_s8(__rev0_17, __p1_17); \
8937	7843	__ret_17 = __builtin_shufflevector(__ret_17, __ret_17, __lane_reverse_128_8); \
8938	7844	__ret_17; \
8939	7845	})
8940	7846	#endif
8941	7847
8942	7848	#ifdef __LITTLE_ENDIAN__
8943		#define vdupq_lane_u32(__p0_18, __p1_18) __extension__ ({ \
8944		uint32x4_t __ret_18; \
8945		uint32x2_t __s0_18 = __p0_18; \
8946		__ret_18 = splatq_lane_u32(__s0_18, __p1_18); \
	7849	#define vdupq_lane_f32(__p0_18, __p1_18) __extension__ ({ \
	7850	float32x4_t __ret_18; \
	7851	float32x2_t __s0_18 = __p0_18; \
	7852	__ret_18 = splatq_lane_f32(__s0_18, __p1_18); \
8947	7853	__ret_18; \
8948	7854	})
8949	7855	#else
8950		#define vdupq_lane_u32(__p0_19, __p1_19) __extension__ ({ \
8951		uint32x4_t __ret_19; \
8952		uint32x2_t __s0_19 = __p0_19; \
8953		uint32x2_t __rev0_19; __rev0_19 = __builtin_shufflevector(__s0_19, __s0_19, __lane_reverse_64_32); \
8954		__ret_19 = __noswap_splatq_lane_u32(__rev0_19, __p1_19); \
	7856	#define vdupq_lane_f32(__p0_19, __p1_19) __extension__ ({ \
	7857	float32x4_t __ret_19; \
	7858	float32x2_t __s0_19 = __p0_19; \
	7859	float32x2_t __rev0_19; __rev0_19 = __builtin_shufflevector(__s0_19, __s0_19, __lane_reverse_64_32); \
	7860	__ret_19 = __noswap_splatq_lane_f32(__rev0_19, __p1_19); \
8955	7861	__ret_19 = __builtin_shufflevector(__ret_19, __ret_19, __lane_reverse_128_32); \
8956	7862	__ret_19; \
8957	7863	})
8958	7864	#endif
8959	7865
8960	7866	#ifdef __LITTLE_ENDIAN__
8961		#define vdupq_lane_u64(__p0_20, __p1_20) __extension__ ({ \
8962		uint64x2_t __ret_20; \
8963		uint64x1_t __s0_20 = __p0_20; \
8964		__ret_20 = splatq_lane_u64(__s0_20, __p1_20); \
	7867	#define vdupq_lane_f16(__p0_20, __p1_20) __extension__ ({ \
	7868	float16x8_t __ret_20; \
	7869	float16x4_t __s0_20 = __p0_20; \
	7870	__ret_20 = splatq_lane_f16(__s0_20, __p1_20); \
8965	7871	__ret_20; \
8966	7872	})
8967	7873	#else
8968		#define vdupq_lane_u64(__p0_21, __p1_21) __extension__ ({ \
8969		uint64x2_t __ret_21; \
8970		uint64x1_t __s0_21 = __p0_21; \
8971		__ret_21 = __noswap_splatq_lane_u64(__s0_21, __p1_21); \
8972		__ret_21 = __builtin_shufflevector(__ret_21, __ret_21, __lane_reverse_128_64); \
	7874	#define vdupq_lane_f16(__p0_21, __p1_21) __extension__ ({ \
	7875	float16x8_t __ret_21; \
	7876	float16x4_t __s0_21 = __p0_21; \
	7877	float16x4_t __rev0_21; __rev0_21 = __builtin_shufflevector(__s0_21, __s0_21, __lane_reverse_64_16); \
	7878	__ret_21 = __noswap_splatq_lane_f16(__rev0_21, __p1_21); \
	7879	__ret_21 = __builtin_shufflevector(__ret_21, __ret_21, __lane_reverse_128_16); \
8973	7880	__ret_21; \
8974	7881	})
8975	7882	#endif
8976	7883
8977	7884	#ifdef __LITTLE_ENDIAN__
8978		#define vdupq_lane_u16(__p0_22, __p1_22) __extension__ ({ \
8979		uint16x8_t __ret_22; \
8980		uint16x4_t __s0_22 = __p0_22; \
8981		__ret_22 = splatq_lane_u16(__s0_22, __p1_22); \
	7885	#define vdupq_lane_s32(__p0_22, __p1_22) __extension__ ({ \
	7886	int32x4_t __ret_22; \
	7887	int32x2_t __s0_22 = __p0_22; \
	7888	__ret_22 = splatq_lane_s32(__s0_22, __p1_22); \
8982	7889	__ret_22; \
8983	7890	})
8984	7891	#else
8985		#define vdupq_lane_u16(__p0_23, __p1_23) __extension__ ({ \
8986		uint16x8_t __ret_23; \
8987		uint16x4_t __s0_23 = __p0_23; \
8988		uint16x4_t __rev0_23; __rev0_23 = __builtin_shufflevector(__s0_23, __s0_23, __lane_reverse_64_16); \
8989		__ret_23 = __noswap_splatq_lane_u16(__rev0_23, __p1_23); \
8990		__ret_23 = __builtin_shufflevector(__ret_23, __ret_23, __lane_reverse_128_16); \
	7892	#define vdupq_lane_s32(__p0_23, __p1_23) __extension__ ({ \
	7893	int32x4_t __ret_23; \
	7894	int32x2_t __s0_23 = __p0_23; \
	7895	int32x2_t __rev0_23; __rev0_23 = __builtin_shufflevector(__s0_23, __s0_23, __lane_reverse_64_32); \
	7896	__ret_23 = __noswap_splatq_lane_s32(__rev0_23, __p1_23); \
	7897	__ret_23 = __builtin_shufflevector(__ret_23, __ret_23, __lane_reverse_128_32); \
8991	7898	__ret_23; \
8992	7899	})
8993	7900	#endif
8994	7901
8995	7902	#ifdef __LITTLE_ENDIAN__
8996		#define vdupq_lane_s8(__p0_24, __p1_24) __extension__ ({ \
8997		int8x16_t __ret_24; \
8998		int8x8_t __s0_24 = __p0_24; \
8999		__ret_24 = splatq_lane_s8(__s0_24, __p1_24); \
	7903	#define vdupq_lane_s64(__p0_24, __p1_24) __extension__ ({ \
	7904	int64x2_t __ret_24; \
	7905	int64x1_t __s0_24 = __p0_24; \
	7906	__ret_24 = splatq_lane_s64(__s0_24, __p1_24); \
9000	7907	__ret_24; \
9001	7908	})
9002	7909	#else
9003		#define vdupq_lane_s8(__p0_25, __p1_25) __extension__ ({ \
9004		int8x16_t __ret_25; \
9005		int8x8_t __s0_25 = __p0_25; \
9006		int8x8_t __rev0_25; __rev0_25 = __builtin_shufflevector(__s0_25, __s0_25, __lane_reverse_64_8); \
9007		__ret_25 = __noswap_splatq_lane_s8(__rev0_25, __p1_25); \
9008		__ret_25 = __builtin_shufflevector(__ret_25, __ret_25, __lane_reverse_128_8); \
	7910	#define vdupq_lane_s64(__p0_25, __p1_25) __extension__ ({ \
	7911	int64x2_t __ret_25; \
	7912	int64x1_t __s0_25 = __p0_25; \
	7913	__ret_25 = __noswap_splatq_lane_s64(__s0_25, __p1_25); \
	7914	__ret_25 = __builtin_shufflevector(__ret_25, __ret_25, __lane_reverse_128_64); \
9009	7915	__ret_25; \
9010	7916	})
9011	7917	#endif
9012	7918
9013	7919	#ifdef __LITTLE_ENDIAN__
9014		#define vdupq_lane_f32(__p0_26, __p1_26) __extension__ ({ \
9015		float32x4_t __ret_26; \
9016		float32x2_t __s0_26 = __p0_26; \
9017		__ret_26 = splatq_lane_f32(__s0_26, __p1_26); \
	7920	#define vdupq_lane_s16(__p0_26, __p1_26) __extension__ ({ \
	7921	int16x8_t __ret_26; \
	7922	int16x4_t __s0_26 = __p0_26; \
	7923	__ret_26 = splatq_lane_s16(__s0_26, __p1_26); \
9018	7924	__ret_26; \
9019	7925	})
9020	7926	#else
9021		#define vdupq_lane_f32(__p0_27, __p1_27) __extension__ ({ \
9022		float32x4_t __ret_27; \
9023		float32x2_t __s0_27 = __p0_27; \
9024		float32x2_t __rev0_27; __rev0_27 = __builtin_shufflevector(__s0_27, __s0_27, __lane_reverse_64_32); \
9025		__ret_27 = __noswap_splatq_lane_f32(__rev0_27, __p1_27); \
9026		__ret_27 = __builtin_shufflevector(__ret_27, __ret_27, __lane_reverse_128_32); \
	7927	#define vdupq_lane_s16(__p0_27, __p1_27) __extension__ ({ \
	7928	int16x8_t __ret_27; \
	7929	int16x4_t __s0_27 = __p0_27; \
	7930	int16x4_t __rev0_27; __rev0_27 = __builtin_shufflevector(__s0_27, __s0_27, __lane_reverse_64_16); \
	7931	__ret_27 = __noswap_splatq_lane_s16(__rev0_27, __p1_27); \
	7932	__ret_27 = __builtin_shufflevector(__ret_27, __ret_27, __lane_reverse_128_16); \
9027	7933	__ret_27; \
9028	7934	})
9029	7935	#endif
9030	7936
9031	7937	#ifdef __LITTLE_ENDIAN__
9032		#define vdupq_lane_f16(__p0_28, __p1_28) __extension__ ({ \
9033		float16x8_t __ret_28; \
9034		float16x4_t __s0_28 = __p0_28; \
9035		__ret_28 = splatq_lane_f16(__s0_28, __p1_28); \
	7938	#define vdup_lane_u8(__p0_28, __p1_28) __extension__ ({ \
	7939	uint8x8_t __ret_28; \
	7940	uint8x8_t __s0_28 = __p0_28; \
	7941	__ret_28 = splat_lane_u8(__s0_28, __p1_28); \
9036	7942	__ret_28; \
9037	7943	})
9038	7944	#else
9039		#define vdupq_lane_f16(__p0_29, __p1_29) __extension__ ({ \
9040		float16x8_t __ret_29; \
9041		float16x4_t __s0_29 = __p0_29; \
9042		float16x4_t __rev0_29; __rev0_29 = __builtin_shufflevector(__s0_29, __s0_29, __lane_reverse_64_16); \
9043		__ret_29 = __noswap_splatq_lane_f16(__rev0_29, __p1_29); \
9044		__ret_29 = __builtin_shufflevector(__ret_29, __ret_29, __lane_reverse_128_16); \
	7945	#define vdup_lane_u8(__p0_29, __p1_29) __extension__ ({ \
	7946	uint8x8_t __ret_29; \
	7947	uint8x8_t __s0_29 = __p0_29; \
	7948	uint8x8_t __rev0_29; __rev0_29 = __builtin_shufflevector(__s0_29, __s0_29, __lane_reverse_64_8); \
	7949	__ret_29 = __noswap_splat_lane_u8(__rev0_29, __p1_29); \
	7950	__ret_29 = __builtin_shufflevector(__ret_29, __ret_29, __lane_reverse_64_8); \
9045	7951	__ret_29; \
9046	7952	})
9047	7953	#endif
9048	7954
9049	7955	#ifdef __LITTLE_ENDIAN__
9050		#define vdupq_lane_s32(__p0_30, __p1_30) __extension__ ({ \
9051		int32x4_t __ret_30; \
9052		int32x2_t __s0_30 = __p0_30; \
9053		__ret_30 = splatq_lane_s32(__s0_30, __p1_30); \
	7956	#define vdup_lane_u32(__p0_30, __p1_30) __extension__ ({ \
	7957	uint32x2_t __ret_30; \
	7958	uint32x2_t __s0_30 = __p0_30; \
	7959	__ret_30 = splat_lane_u32(__s0_30, __p1_30); \
9054	7960	__ret_30; \
9055	7961	})
9056	7962	#else
9057		#define vdupq_lane_s32(__p0_31, __p1_31) __extension__ ({ \
9058		int32x4_t __ret_31; \
9059		int32x2_t __s0_31 = __p0_31; \
9060		int32x2_t __rev0_31; __rev0_31 = __builtin_shufflevector(__s0_31, __s0_31, __lane_reverse_64_32); \
9061		__ret_31 = __noswap_splatq_lane_s32(__rev0_31, __p1_31); \
9062		__ret_31 = __builtin_shufflevector(__ret_31, __ret_31, __lane_reverse_128_32); \
	7963	#define vdup_lane_u32(__p0_31, __p1_31) __extension__ ({ \
	7964	uint32x2_t __ret_31; \
	7965	uint32x2_t __s0_31 = __p0_31; \
	7966	uint32x2_t __rev0_31; __rev0_31 = __builtin_shufflevector(__s0_31, __s0_31, __lane_reverse_64_32); \
	7967	__ret_31 = __noswap_splat_lane_u32(__rev0_31, __p1_31); \
	7968	__ret_31 = __builtin_shufflevector(__ret_31, __ret_31, __lane_reverse_64_32); \
9063	7969	__ret_31; \
9064	7970	})
9065	7971	#endif
9066	7972
9067		#ifdef __LITTLE_ENDIAN__
9068		#define vdupq_lane_s64(__p0_32, __p1_32) __extension__ ({ \
9069		int64x2_t __ret_32; \
9070		int64x1_t __s0_32 = __p0_32; \
9071		__ret_32 = splatq_lane_s64(__s0_32, __p1_32); \
	7973	#define vdup_lane_u64(__p0_32, __p1_32) __extension__ ({ \
	7974	uint64x1_t __ret_32; \
	7975	uint64x1_t __s0_32 = __p0_32; \
	7976	__ret_32 = splat_lane_u64(__s0_32, __p1_32); \
9072	7977	__ret_32; \
9073	7978	})
9074		#else
9075		#define vdupq_lane_s64(__p0_33, __p1_33) __extension__ ({ \
9076		int64x2_t __ret_33; \
9077		int64x1_t __s0_33 = __p0_33; \
9078		__ret_33 = __noswap_splatq_lane_s64(__s0_33, __p1_33); \
9079		__ret_33 = __builtin_shufflevector(__ret_33, __ret_33, __lane_reverse_128_64); \
	7979	#ifdef __LITTLE_ENDIAN__
	7980	#define vdup_lane_u16(__p0_33, __p1_33) __extension__ ({ \
	7981	uint16x4_t __ret_33; \
	7982	uint16x4_t __s0_33 = __p0_33; \
	7983	__ret_33 = splat_lane_u16(__s0_33, __p1_33); \
9080	7984	__ret_33; \
9081	7985	})
	7986	#else
	7987	#define vdup_lane_u16(__p0_34, __p1_34) __extension__ ({ \
	7988	uint16x4_t __ret_34; \
	7989	uint16x4_t __s0_34 = __p0_34; \
	7990	uint16x4_t __rev0_34; __rev0_34 = __builtin_shufflevector(__s0_34, __s0_34, __lane_reverse_64_16); \
	7991	__ret_34 = __noswap_splat_lane_u16(__rev0_34, __p1_34); \
	7992	__ret_34 = __builtin_shufflevector(__ret_34, __ret_34, __lane_reverse_64_16); \
	7993	__ret_34; \
	7994	})
9082	7995	#endif
9083	7996
9084	7997	#ifdef __LITTLE_ENDIAN__
9085		#define vdupq_lane_s16(__p0_34, __p1_34) __extension__ ({ \
9086		int16x8_t __ret_34; \
9087		int16x4_t __s0_34 = __p0_34; \
9088		__ret_34 = splatq_lane_s16(__s0_34, __p1_34); \
9089		__ret_34; \
	7998	#define vdup_lane_s8(__p0_35, __p1_35) __extension__ ({ \
	7999	int8x8_t __ret_35; \
	8000	int8x8_t __s0_35 = __p0_35; \
	8001	__ret_35 = splat_lane_s8(__s0_35, __p1_35); \
	8002	__ret_35; \
9090	8003	})
9091	8004	#else
9092		#define vdupq_lane_s16(__p0_35, __p1_35) __extension__ ({ \
9093		int16x8_t __ret_35; \
9094		int16x4_t __s0_35 = __p0_35; \
9095		int16x4_t __rev0_35; __rev0_35 = __builtin_shufflevector(__s0_35, __s0_35, __lane_reverse_64_16); \
9096		__ret_35 = __noswap_splatq_lane_s16(__rev0_35, __p1_35); \
9097		__ret_35 = __builtin_shufflevector(__ret_35, __ret_35, __lane_reverse_128_16); \
9098		__ret_35; \
	8005	#define vdup_lane_s8(__p0_36, __p1_36) __extension__ ({ \
	8006	int8x8_t __ret_36; \
	8007	int8x8_t __s0_36 = __p0_36; \
	8008	int8x8_t __rev0_36; __rev0_36 = __builtin_shufflevector(__s0_36, __s0_36, __lane_reverse_64_8); \
	8009	__ret_36 = __noswap_splat_lane_s8(__rev0_36, __p1_36); \
	8010	__ret_36 = __builtin_shufflevector(__ret_36, __ret_36, __lane_reverse_64_8); \
	8011	__ret_36; \
9099	8012	})
9100	8013	#endif
9101	8014
9102	8015	#ifdef __LITTLE_ENDIAN__
9103		#define vdup_lane_u8(__p0_36, __p1_36) __extension__ ({ \
9104		uint8x8_t __ret_36; \
9105		uint8x8_t __s0_36 = __p0_36; \
9106		__ret_36 = splat_lane_u8(__s0_36, __p1_36); \
9107		__ret_36; \
	8016	#define vdup_lane_f32(__p0_37, __p1_37) __extension__ ({ \
	8017	float32x2_t __ret_37; \
	8018	float32x2_t __s0_37 = __p0_37; \
	8019	__ret_37 = splat_lane_f32(__s0_37, __p1_37); \
	8020	__ret_37; \
9108	8021	})
9109	8022	#else
9110		#define vdup_lane_u8(__p0_37, __p1_37) __extension__ ({ \
9111		uint8x8_t __ret_37; \
9112		uint8x8_t __s0_37 = __p0_37; \
9113		uint8x8_t __rev0_37; __rev0_37 = __builtin_shufflevector(__s0_37, __s0_37, __lane_reverse_64_8); \
9114		__ret_37 = __noswap_splat_lane_u8(__rev0_37, __p1_37); \
9115		__ret_37 = __builtin_shufflevector(__ret_37, __ret_37, __lane_reverse_64_8); \
9116		__ret_37; \
	8023	#define vdup_lane_f32(__p0_38, __p1_38) __extension__ ({ \
	8024	float32x2_t __ret_38; \
	8025	float32x2_t __s0_38 = __p0_38; \
	8026	float32x2_t __rev0_38; __rev0_38 = __builtin_shufflevector(__s0_38, __s0_38, __lane_reverse_64_32); \
	8027	__ret_38 = __noswap_splat_lane_f32(__rev0_38, __p1_38); \
	8028	__ret_38 = __builtin_shufflevector(__ret_38, __ret_38, __lane_reverse_64_32); \
	8029	__ret_38; \
9117	8030	})
9118	8031	#endif
9119	8032
9120	8033	#ifdef __LITTLE_ENDIAN__
9121		#define vdup_lane_u32(__p0_38, __p1_38) __extension__ ({ \
9122		uint32x2_t __ret_38; \
9123		uint32x2_t __s0_38 = __p0_38; \
9124		__ret_38 = splat_lane_u32(__s0_38, __p1_38); \
9125		__ret_38; \
	8034	#define vdup_lane_f16(__p0_39, __p1_39) __extension__ ({ \
	8035	float16x4_t __ret_39; \
	8036	float16x4_t __s0_39 = __p0_39; \
	8037	__ret_39 = splat_lane_f16(__s0_39, __p1_39); \
	8038	__ret_39; \
9126	8039	})
9127	8040	#else
9128		#define vdup_lane_u32(__p0_39, __p1_39) __extension__ ({ \
9129		uint32x2_t __ret_39; \
9130		uint32x2_t __s0_39 = __p0_39; \
9131		uint32x2_t __rev0_39; __rev0_39 = __builtin_shufflevector(__s0_39, __s0_39, __lane_reverse_64_32); \
9132		__ret_39 = __noswap_splat_lane_u32(__rev0_39, __p1_39); \
9133		__ret_39 = __builtin_shufflevector(__ret_39, __ret_39, __lane_reverse_64_32); \
9134		__ret_39; \
	8041	#define vdup_lane_f16(__p0_40, __p1_40) __extension__ ({ \
	8042	float16x4_t __ret_40; \
	8043	float16x4_t __s0_40 = __p0_40; \
	8044	float16x4_t __rev0_40; __rev0_40 = __builtin_shufflevector(__s0_40, __s0_40, __lane_reverse_64_16); \
	8045	__ret_40 = __noswap_splat_lane_f16(__rev0_40, __p1_40); \
	8046	__ret_40 = __builtin_shufflevector(__ret_40, __ret_40, __lane_reverse_64_16); \
	8047	__ret_40; \
9135	8048	})
9136	8049	#endif
9137	8050
9138		#define vdup_lane_u64(__p0_40, __p1_40) __extension__ ({ \
9139		uint64x1_t __ret_40; \
9140		uint64x1_t __s0_40 = __p0_40; \
9141		__ret_40 = splat_lane_u64(__s0_40, __p1_40); \
9142		__ret_40; \
9143		})
9144	8051	#ifdef __LITTLE_ENDIAN__
9145		#define vdup_lane_u16(__p0_41, __p1_41) __extension__ ({ \
9146		uint16x4_t __ret_41; \
9147		uint16x4_t __s0_41 = __p0_41; \
9148		__ret_41 = splat_lane_u16(__s0_41, __p1_41); \
	8052	#define vdup_lane_s32(__p0_41, __p1_41) __extension__ ({ \
	8053	int32x2_t __ret_41; \
	8054	int32x2_t __s0_41 = __p0_41; \
	8055	__ret_41 = splat_lane_s32(__s0_41, __p1_41); \
9149	8056	__ret_41; \
9150	8057	})
9151	8058	#else
9152		#define vdup_lane_u16(__p0_42, __p1_42) __extension__ ({ \
9153		uint16x4_t __ret_42; \
9154		uint16x4_t __s0_42 = __p0_42; \
9155		uint16x4_t __rev0_42; __rev0_42 = __builtin_shufflevector(__s0_42, __s0_42, __lane_reverse_64_16); \
9156		__ret_42 = __noswap_splat_lane_u16(__rev0_42, __p1_42); \
9157		__ret_42 = __builtin_shufflevector(__ret_42, __ret_42, __lane_reverse_64_16); \
	8059	#define vdup_lane_s32(__p0_42, __p1_42) __extension__ ({ \
	8060	int32x2_t __ret_42; \
	8061	int32x2_t __s0_42 = __p0_42; \
	8062	int32x2_t __rev0_42; __rev0_42 = __builtin_shufflevector(__s0_42, __s0_42, __lane_reverse_64_32); \
	8063	__ret_42 = __noswap_splat_lane_s32(__rev0_42, __p1_42); \
	8064	__ret_42 = __builtin_shufflevector(__ret_42, __ret_42, __lane_reverse_64_32); \
9158	8065	__ret_42; \
9159	8066	})
9160	8067	#endif
9161	8068
9162		#ifdef __LITTLE_ENDIAN__
9163		#define vdup_lane_s8(__p0_43, __p1_43) __extension__ ({ \
9164		int8x8_t __ret_43; \
9165		int8x8_t __s0_43 = __p0_43; \
9166		__ret_43 = splat_lane_s8(__s0_43, __p1_43); \
	8069	#define vdup_lane_s64(__p0_43, __p1_43) __extension__ ({ \
	8070	int64x1_t __ret_43; \
	8071	int64x1_t __s0_43 = __p0_43; \
	8072	__ret_43 = splat_lane_s64(__s0_43, __p1_43); \
9167	8073	__ret_43; \
9168	8074	})
9169		#else
9170		#define vdup_lane_s8(__p0_44, __p1_44) __extension__ ({ \
9171		int8x8_t __ret_44; \
9172		int8x8_t __s0_44 = __p0_44; \
9173		int8x8_t __rev0_44; __rev0_44 = __builtin_shufflevector(__s0_44, __s0_44, __lane_reverse_64_8); \
9174		__ret_44 = __noswap_splat_lane_s8(__rev0_44, __p1_44); \
9175		__ret_44 = __builtin_shufflevector(__ret_44, __ret_44, __lane_reverse_64_8); \
	8075	#ifdef __LITTLE_ENDIAN__
	8076	#define vdup_lane_s16(__p0_44, __p1_44) __extension__ ({ \
	8077	int16x4_t __ret_44; \
	8078	int16x4_t __s0_44 = __p0_44; \
	8079	__ret_44 = splat_lane_s16(__s0_44, __p1_44); \
9176	8080	__ret_44; \
9177	8081	})
	8082	#else
	8083	#define vdup_lane_s16(__p0_45, __p1_45) __extension__ ({ \
	8084	int16x4_t __ret_45; \
	8085	int16x4_t __s0_45 = __p0_45; \
	8086	int16x4_t __rev0_45; __rev0_45 = __builtin_shufflevector(__s0_45, __s0_45, __lane_reverse_64_16); \
	8087	__ret_45 = __noswap_splat_lane_s16(__rev0_45, __p1_45); \
	8088	__ret_45 = __builtin_shufflevector(__ret_45, __ret_45, __lane_reverse_64_16); \
	8089	__ret_45; \
	8090	})
9178	8091	#endif
9179	8092
9180	8093	#ifdef __LITTLE_ENDIAN__
9181		#define vdup_lane_f32(__p0_45, __p1_45) __extension__ ({ \
9182		float32x2_t __ret_45; \
9183		float32x2_t __s0_45 = __p0_45; \
9184		__ret_45 = splat_lane_f32(__s0_45, __p1_45); \
9185		__ret_45; \
	8094	#define vdupq_lane_bf16(__p0_46, __p1_46) __extension__ ({ \
	8095	bfloat16x8_t __ret_46; \
	8096	bfloat16x4_t __s0_46 = __p0_46; \
	8097	__ret_46 = splatq_lane_bf16(__s0_46, __p1_46); \
	8098	__ret_46; \
9186	8099	})
9187	8100	#else
9188		#define vdup_lane_f32(__p0_46, __p1_46) __extension__ ({ \
9189		float32x2_t __ret_46; \
9190		float32x2_t __s0_46 = __p0_46; \
9191		float32x2_t __rev0_46; __rev0_46 = __builtin_shufflevector(__s0_46, __s0_46, __lane_reverse_64_32); \
9192		__ret_46 = __noswap_splat_lane_f32(__rev0_46, __p1_46); \
9193		__ret_46 = __builtin_shufflevector(__ret_46, __ret_46, __lane_reverse_64_32); \
9194		__ret_46; \
	8101	#define vdupq_lane_bf16(__p0_47, __p1_47) __extension__ ({ \
	8102	bfloat16x8_t __ret_47; \
	8103	bfloat16x4_t __s0_47 = __p0_47; \
	8104	bfloat16x4_t __rev0_47; __rev0_47 = __builtin_shufflevector(__s0_47, __s0_47, __lane_reverse_64_16); \
	8105	__ret_47 = __noswap_splatq_lane_bf16(__rev0_47, __p1_47); \
	8106	__ret_47 = __builtin_shufflevector(__ret_47, __ret_47, __lane_reverse_128_16); \
	8107	__ret_47; \
9195	8108	})
9196	8109	#endif
9197	8110
9198	8111	#ifdef __LITTLE_ENDIAN__
9199		#define vdup_lane_f16(__p0_47, __p1_47) __extension__ ({ \
9200		float16x4_t __ret_47; \
9201		float16x4_t __s0_47 = __p0_47; \
9202		__ret_47 = splat_lane_f16(__s0_47, __p1_47); \
9203		__ret_47; \
	8112	#define vdup_lane_bf16(__p0_48, __p1_48) __extension__ ({ \
	8113	bfloat16x4_t __ret_48; \
	8114	bfloat16x4_t __s0_48 = __p0_48; \
	8115	__ret_48 = splat_lane_bf16(__s0_48, __p1_48); \
	8116	__ret_48; \
9204	8117	})
9205	8118	#else
9206		#define vdup_lane_f16(__p0_48, __p1_48) __extension__ ({ \
9207		float16x4_t __ret_48; \
9208		float16x4_t __s0_48 = __p0_48; \
9209		float16x4_t __rev0_48; __rev0_48 = __builtin_shufflevector(__s0_48, __s0_48, __lane_reverse_64_16); \
9210		__ret_48 = __noswap_splat_lane_f16(__rev0_48, __p1_48); \
9211		__ret_48 = __builtin_shufflevector(__ret_48, __ret_48, __lane_reverse_64_16); \
9212		__ret_48; \
	8119	#define vdup_lane_bf16(__p0_49, __p1_49) __extension__ ({ \
	8120	bfloat16x4_t __ret_49; \
	8121	bfloat16x4_t __s0_49 = __p0_49; \
	8122	bfloat16x4_t __rev0_49; __rev0_49 = __builtin_shufflevector(__s0_49, __s0_49, __lane_reverse_64_16); \
	8123	__ret_49 = __noswap_splat_lane_bf16(__rev0_49, __p1_49); \
	8124	__ret_49 = __builtin_shufflevector(__ret_49, __ret_49, __lane_reverse_64_16); \
	8125	__ret_49; \
9213	8126	})
9214	8127	#endif
9215	8128
9216	8129	#ifdef __LITTLE_ENDIAN__
9217		#define vdup_lane_s32(__p0_49, __p1_49) __extension__ ({ \
9218		int32x2_t __ret_49; \
9219		int32x2_t __s0_49 = __p0_49; \
9220		__ret_49 = splat_lane_s32(__s0_49, __p1_49); \
9221		__ret_49; \
	8130	#define vduph_laneq_bf16(__p0, __p1) __extension__ ({ \
	8131	bfloat16_t __ret; \
	8132	bfloat16x8_t __s0 = __p0; \
	8133	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_laneq_bf16(__s0, __p1)); \
	8134	__ret; \
9222	8135	})
9223	8136	#else
9224		#define vdup_lane_s32(__p0_50, __p1_50) __extension__ ({ \
9225		int32x2_t __ret_50; \
9226		int32x2_t __s0_50 = __p0_50; \
9227		int32x2_t __rev0_50; __rev0_50 = __builtin_shufflevector(__s0_50, __s0_50, __lane_reverse_64_32); \
9228		__ret_50 = __noswap_splat_lane_s32(__rev0_50, __p1_50); \
9229		__ret_50 = __builtin_shufflevector(__ret_50, __ret_50, __lane_reverse_64_32); \
9230		__ret_50; \
	8137	#define vduph_laneq_bf16(__p0, __p1) __extension__ ({ \
	8138	bfloat16_t __ret; \
	8139	bfloat16x8_t __s0 = __p0; \
	8140	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	8141	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vduph_laneq_bf16(__rev0, __p1)); \
	8142	__ret; \
9231	8143	})
9232	8144	#endif
9233	8145
9234		#define vdup_lane_s64(__p0_51, __p1_51) __extension__ ({ \
9235		int64x1_t __ret_51; \
9236		int64x1_t __s0_51 = __p0_51; \
9237		__ret_51 = splat_lane_s64(__s0_51, __p1_51); \
	8146	#ifdef __LITTLE_ENDIAN__
	8147	#define vdupq_laneq_bf16(__p0_50, __p1_50) __extension__ ({ \
	8148	bfloat16x8_t __ret_50; \
	8149	bfloat16x8_t __s0_50 = __p0_50; \
	8150	__ret_50 = splatq_laneq_bf16(__s0_50, __p1_50); \
	8151	__ret_50; \
	8152	})
	8153	#else
	8154	#define vdupq_laneq_bf16(__p0_51, __p1_51) __extension__ ({ \
	8155	bfloat16x8_t __ret_51; \
	8156	bfloat16x8_t __s0_51 = __p0_51; \
	8157	bfloat16x8_t __rev0_51; __rev0_51 = __builtin_shufflevector(__s0_51, __s0_51, __lane_reverse_128_16); \
	8158	__ret_51 = __noswap_splatq_laneq_bf16(__rev0_51, __p1_51); \
	8159	__ret_51 = __builtin_shufflevector(__ret_51, __ret_51, __lane_reverse_128_16); \
9238	8160	__ret_51; \
9239	8161	})
	8162	#endif
	8163
9240	8164	#ifdef __LITTLE_ENDIAN__
9241		#define vdup_lane_s16(__p0_52, __p1_52) __extension__ ({ \
9242		int16x4_t __ret_52; \
9243		int16x4_t __s0_52 = __p0_52; \
9244		__ret_52 = splat_lane_s16(__s0_52, __p1_52); \
	8165	#define vdup_laneq_bf16(__p0_52, __p1_52) __extension__ ({ \
	8166	bfloat16x4_t __ret_52; \
	8167	bfloat16x8_t __s0_52 = __p0_52; \
	8168	__ret_52 = splat_laneq_bf16(__s0_52, __p1_52); \
9245	8169	__ret_52; \
9246	8170	})
9247	8171	#else
9248		#define vdup_lane_s16(__p0_53, __p1_53) __extension__ ({ \
9249		int16x4_t __ret_53; \
9250		int16x4_t __s0_53 = __p0_53; \
9251		int16x4_t __rev0_53; __rev0_53 = __builtin_shufflevector(__s0_53, __s0_53, __lane_reverse_64_16); \
9252		__ret_53 = __noswap_splat_lane_s16(__rev0_53, __p1_53); \
	8172	#define vdup_laneq_bf16(__p0_53, __p1_53) __extension__ ({ \
	8173	bfloat16x4_t __ret_53; \
	8174	bfloat16x8_t __s0_53 = __p0_53; \
	8175	bfloat16x8_t __rev0_53; __rev0_53 = __builtin_shufflevector(__s0_53, __s0_53, __lane_reverse_128_16); \
	8176	__ret_53 = __noswap_splat_laneq_bf16(__rev0_53, __p1_53); \
9253	8177	__ret_53 = __builtin_shufflevector(__ret_53, __ret_53, __lane_reverse_64_16); \
9254	8178	__ret_53; \
9255	8179	})
...	...	@@ -9599,6 +8523,36 @@ __ai __attribute__((target("neon"))) int16x4_t vdup_n_s16(int16_t __p0) {
9599	8523	}
9600	8524	#endif
9601	8525
	8526	#ifdef __LITTLE_ENDIAN__
	8527	__ai __attribute__((target("neon"))) bfloat16x8_t vdupq_n_bf16(bfloat16_t __p0) {
	8528	bfloat16x8_t __ret;
	8529	__ret = (bfloat16x8_t) {__p0, __p0, __p0, __p0, __p0, __p0, __p0, __p0};
	8530	return __ret;
	8531	}
	8532	#else
	8533	__ai __attribute__((target("neon"))) bfloat16x8_t vdupq_n_bf16(bfloat16_t __p0) {
	8534	bfloat16x8_t __ret;
	8535	__ret = (bfloat16x8_t) {__p0, __p0, __p0, __p0, __p0, __p0, __p0, __p0};
	8536	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
	8537	return __ret;
	8538	}
	8539	#endif
	8540
	8541	#ifdef __LITTLE_ENDIAN__
	8542	__ai __attribute__((target("neon"))) bfloat16x4_t vdup_n_bf16(bfloat16_t __p0) {
	8543	bfloat16x4_t __ret;
	8544	__ret = (bfloat16x4_t) {__p0, __p0, __p0, __p0};
	8545	return __ret;
	8546	}
	8547	#else
	8548	__ai __attribute__((target("neon"))) bfloat16x4_t vdup_n_bf16(bfloat16_t __p0) {
	8549	bfloat16x4_t __ret;
	8550	__ret = (bfloat16x4_t) {__p0, __p0, __p0, __p0};
	8551	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
	8552	return __ret;
	8553	}
	8554	#endif
	8555
9602	8556	#ifdef __LITTLE_ENDIAN__
9603	8557	__ai __attribute__((target("neon"))) uint8x16_t veorq_u8(uint8x16_t __p0, uint8x16_t __p1) {
9604	8558	uint8x16_t __ret;
...	...	@@ -10558,6 +9512,27 @@ __ai __attribute__((target("neon"))) int16x4_t __noswap_vget_high_s16(int16x8_t
10558	9512	}
10559	9513	#endif
10560	9514
	9515	#ifdef __LITTLE_ENDIAN__
	9516	__ai __attribute__((target("neon"))) bfloat16x4_t vget_high_bf16(bfloat16x8_t __p0) {
	9517	bfloat16x4_t __ret;
	9518	__ret = __builtin_shufflevector(__p0, __p0, 4, 5, 6, 7);
	9519	return __ret;
	9520	}
	9521	#else
	9522	__ai __attribute__((target("neon"))) bfloat16x4_t vget_high_bf16(bfloat16x8_t __p0) {
	9523	bfloat16x4_t __ret;
	9524	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	9525	__ret = __builtin_shufflevector(__rev0, __rev0, 4, 5, 6, 7);
	9526	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
	9527	return __ret;
	9528	}
	9529	__ai __attribute__((target("neon"))) bfloat16x4_t __noswap_vget_high_bf16(bfloat16x8_t __p0) {
	9530	bfloat16x4_t __ret;
	9531	__ret = __builtin_shufflevector(__p0, __p0, 4, 5, 6, 7);
	9532	return __ret;
	9533	}
	9534	#endif
	9535
10561	9536	#ifdef __LITTLE_ENDIAN__
10562	9537	#define vget_lane_p8(__p0, __p1) __extension__ ({ \
10563	9538	poly8_t __ret; \
...	...	@@ -11030,6 +10005,52 @@ __ai __attribute__((target("neon"))) int16x4_t __noswap_vget_high_s16(int16x8_t
11030	10005	})
11031	10006	#endif
11032	10007
	10008	#ifdef __LITTLE_ENDIAN__
	10009	#define vgetq_lane_bf16(__p0, __p1) __extension__ ({ \
	10010	bfloat16_t __ret; \
	10011	bfloat16x8_t __s0 = __p0; \
	10012	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vgetq_lane_bf16(__s0, __p1)); \
	10013	__ret; \
	10014	})
	10015	#else
	10016	#define vgetq_lane_bf16(__p0, __p1) __extension__ ({ \
	10017	bfloat16_t __ret; \
	10018	bfloat16x8_t __s0 = __p0; \
	10019	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	10020	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vgetq_lane_bf16(__rev0, __p1)); \
	10021	__ret; \
	10022	})
	10023	#define __noswap_vgetq_lane_bf16(__p0, __p1) __extension__ ({ \
	10024	bfloat16_t __ret; \
	10025	bfloat16x8_t __s0 = __p0; \
	10026	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vgetq_lane_bf16(__s0, __p1)); \
	10027	__ret; \
	10028	})
	10029	#endif
	10030
	10031	#ifdef __LITTLE_ENDIAN__
	10032	#define vget_lane_bf16(__p0, __p1) __extension__ ({ \
	10033	bfloat16_t __ret; \
	10034	bfloat16x4_t __s0 = __p0; \
	10035	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vget_lane_bf16(__s0, __p1)); \
	10036	__ret; \
	10037	})
	10038	#else
	10039	#define vget_lane_bf16(__p0, __p1) __extension__ ({ \
	10040	bfloat16_t __ret; \
	10041	bfloat16x4_t __s0 = __p0; \
	10042	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	10043	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vget_lane_bf16(__rev0, __p1)); \
	10044	__ret; \
	10045	})
	10046	#define __noswap_vget_lane_bf16(__p0, __p1) __extension__ ({ \
	10047	bfloat16_t __ret; \
	10048	bfloat16x4_t __s0 = __p0; \
	10049	__ret = __builtin_bit_cast(bfloat16_t, __builtin_neon_vget_lane_bf16(__s0, __p1)); \
	10050	__ret; \
	10051	})
	10052	#endif
	10053
11033	10054	#ifdef __LITTLE_ENDIAN__
11034	10055	__ai __attribute__((target("neon"))) poly8x8_t vget_low_p8(poly8x16_t __p0) {
11035	10056	poly8x8_t __ret;
...	...	@@ -11220,6 +10241,27 @@ __ai __attribute__((target("neon"))) int16x4_t vget_low_s16(int16x8_t __p0) {
11220	10241	}
11221	10242	#endif
11222	10243
	10244	#ifdef __LITTLE_ENDIAN__
	10245	__ai __attribute__((target("neon"))) bfloat16x4_t vget_low_bf16(bfloat16x8_t __p0) {
	10246	bfloat16x4_t __ret;
	10247	__ret = __builtin_shufflevector(__p0, __p0, 0, 1, 2, 3);
	10248	return __ret;
	10249	}
	10250	#else
	10251	__ai __attribute__((target("neon"))) bfloat16x4_t vget_low_bf16(bfloat16x8_t __p0) {
	10252	bfloat16x4_t __ret;
	10253	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	10254	__ret = __builtin_shufflevector(__rev0, __rev0, 0, 1, 2, 3);
	10255	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
	10256	return __ret;
	10257	}
	10258	__ai __attribute__((target("neon"))) bfloat16x4_t __noswap_vget_low_bf16(bfloat16x8_t __p0) {
	10259	bfloat16x4_t __ret;
	10260	__ret = __builtin_shufflevector(__p0, __p0, 0, 1, 2, 3);
	10261	return __ret;
	10262	}
	10263	#endif
	10264
11223	10265	#ifdef __LITTLE_ENDIAN__
11224	10266	__ai __attribute__((target("neon"))) uint8x16_t vhaddq_u8(uint8x16_t __p0, uint8x16_t __p1) {
11225	10267	uint8x16_t __ret;
...	...	@@ -11938,6 +10980,36 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
11938	10980	})
11939	10981	#endif
11940	10982
	10983	#ifdef __LITTLE_ENDIAN__
	10984	#define vld1q_bf16(__p0) __extension__ ({ \
	10985	bfloat16x8_t __ret; \
	10986	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_v(__p0, 43)); \
	10987	__ret; \
	10988	})
	10989	#else
	10990	#define vld1q_bf16(__p0) __extension__ ({ \
	10991	bfloat16x8_t __ret; \
	10992	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_v(__p0, 43)); \
	10993	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	10994	__ret; \
	10995	})
	10996	#endif
	10997
	10998	#ifdef __LITTLE_ENDIAN__
	10999	#define vld1_bf16(__p0) __extension__ ({ \
	11000	bfloat16x4_t __ret; \
	11001	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_v(__p0, 11)); \
	11002	__ret; \
	11003	})
	11004	#else
	11005	#define vld1_bf16(__p0) __extension__ ({ \
	11006	bfloat16x4_t __ret; \
	11007	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_v(__p0, 11)); \
	11008	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	11009	__ret; \
	11010	})
	11011	#endif
	11012
11941	11013	#ifdef __LITTLE_ENDIAN__
11942	11014	#define vld1_dup_p8(__p0) __extension__ ({ \
11943	11015	poly8x8_t __ret; \
...	...	@@ -12248,6 +11320,36 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
12248	11320	})
12249	11321	#endif
12250	11322
	11323	#ifdef __LITTLE_ENDIAN__
	11324	#define vld1q_dup_bf16(__p0) __extension__ ({ \
	11325	bfloat16x8_t __ret; \
	11326	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_dup_v(__p0, 43)); \
	11327	__ret; \
	11328	})
	11329	#else
	11330	#define vld1q_dup_bf16(__p0) __extension__ ({ \
	11331	bfloat16x8_t __ret; \
	11332	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_dup_v(__p0, 43)); \
	11333	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	11334	__ret; \
	11335	})
	11336	#endif
	11337
	11338	#ifdef __LITTLE_ENDIAN__
	11339	#define vld1_dup_bf16(__p0) __extension__ ({ \
	11340	bfloat16x4_t __ret; \
	11341	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_dup_v(__p0, 11)); \
	11342	__ret; \
	11343	})
	11344	#else
	11345	#define vld1_dup_bf16(__p0) __extension__ ({ \
	11346	bfloat16x4_t __ret; \
	11347	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_dup_v(__p0, 11)); \
	11348	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	11349	__ret; \
	11350	})
	11351	#endif
	11352
12251	11353	#ifdef __LITTLE_ENDIAN__
12252	11354	#define vld1_lane_p8(__p0, __p1, __p2) __extension__ ({ \
12253	11355	poly8x8_t __ret; \
...	...	@@ -12620,6 +11722,42 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
12620	11722	})
12621	11723	#endif
12622	11724
	11725	#ifdef __LITTLE_ENDIAN__
	11726	#define vld1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	11727	bfloat16x8_t __ret; \
	11728	bfloat16x8_t __s1 = __p1; \
	11729	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
	11730	__ret; \
	11731	})
	11732	#else
	11733	#define vld1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	11734	bfloat16x8_t __ret; \
	11735	bfloat16x8_t __s1 = __p1; \
	11736	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	11737	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vld1q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
	11738	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	11739	__ret; \
	11740	})
	11741	#endif
	11742
	11743	#ifdef __LITTLE_ENDIAN__
	11744	#define vld1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	11745	bfloat16x4_t __ret; \
	11746	bfloat16x4_t __s1 = __p1; \
	11747	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_lane_v(__p0, __builtin_bit_cast(int8x8_t, __s1), __p2, 11)); \
	11748	__ret; \
	11749	})
	11750	#else
	11751	#define vld1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	11752	bfloat16x4_t __ret; \
	11753	bfloat16x4_t __s1 = __p1; \
	11754	bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	11755	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vld1_lane_v(__p0, __builtin_bit_cast(int8x8_t, __rev1), __p2, 11)); \
	11756	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	11757	__ret; \
	11758	})
	11759	#endif
	11760
12623	11761	#ifdef __LITTLE_ENDIAN__
12624	11762	#define vld1_p8_x2(__p0) __extension__ ({ \
12625	11763	poly8x8x2_t __ret; \
...	...	@@ -12970,6 +12108,40 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
12970	12108	})
12971	12109	#endif
12972	12110
	12111	#ifdef __LITTLE_ENDIAN__
	12112	#define vld1q_bf16_x2(__p0) __extension__ ({ \
	12113	bfloat16x8x2_t __ret; \
	12114	__builtin_neon_vld1q_x2_v(&__ret, __p0, 43); \
	12115	__ret; \
	12116	})
	12117	#else
	12118	#define vld1q_bf16_x2(__p0) __extension__ ({ \
	12119	bfloat16x8x2_t __ret; \
	12120	__builtin_neon_vld1q_x2_v(&__ret, __p0, 43); \
	12121	\
	12122	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	12123	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	12124	__ret; \
	12125	})
	12126	#endif
	12127
	12128	#ifdef __LITTLE_ENDIAN__
	12129	#define vld1_bf16_x2(__p0) __extension__ ({ \
	12130	bfloat16x4x2_t __ret; \
	12131	__builtin_neon_vld1_x2_v(&__ret, __p0, 11); \
	12132	__ret; \
	12133	})
	12134	#else
	12135	#define vld1_bf16_x2(__p0) __extension__ ({ \
	12136	bfloat16x4x2_t __ret; \
	12137	__builtin_neon_vld1_x2_v(&__ret, __p0, 11); \
	12138	\
	12139	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	12140	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	12141	__ret; \
	12142	})
	12143	#endif
	12144
12973	12145	#ifdef __LITTLE_ENDIAN__
12974	12146	#define vld1_p8_x3(__p0) __extension__ ({ \
12975	12147	poly8x8x3_t __ret; \
...	...	@@ -13340,6 +12512,42 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
13340	12512	})
13341	12513	#endif
13342	12514
	12515	#ifdef __LITTLE_ENDIAN__
	12516	#define vld1q_bf16_x3(__p0) __extension__ ({ \
	12517	bfloat16x8x3_t __ret; \
	12518	__builtin_neon_vld1q_x3_v(&__ret, __p0, 43); \
	12519	__ret; \
	12520	})
	12521	#else
	12522	#define vld1q_bf16_x3(__p0) __extension__ ({ \
	12523	bfloat16x8x3_t __ret; \
	12524	__builtin_neon_vld1q_x3_v(&__ret, __p0, 43); \
	12525	\
	12526	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	12527	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	12528	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	12529	__ret; \
	12530	})
	12531	#endif
	12532
	12533	#ifdef __LITTLE_ENDIAN__
	12534	#define vld1_bf16_x3(__p0) __extension__ ({ \
	12535	bfloat16x4x3_t __ret; \
	12536	__builtin_neon_vld1_x3_v(&__ret, __p0, 11); \
	12537	__ret; \
	12538	})
	12539	#else
	12540	#define vld1_bf16_x3(__p0) __extension__ ({ \
	12541	bfloat16x4x3_t __ret; \
	12542	__builtin_neon_vld1_x3_v(&__ret, __p0, 11); \
	12543	\
	12544	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	12545	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	12546	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	12547	__ret; \
	12548	})
	12549	#endif
	12550
13343	12551	#ifdef __LITTLE_ENDIAN__
13344	12552	#define vld1_p8_x4(__p0) __extension__ ({ \
13345	12553	poly8x8x4_t __ret; \
...	...	@@ -13730,6 +12938,44 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
13730	12938	})
13731	12939	#endif
13732	12940
	12941	#ifdef __LITTLE_ENDIAN__
	12942	#define vld1q_bf16_x4(__p0) __extension__ ({ \
	12943	bfloat16x8x4_t __ret; \
	12944	__builtin_neon_vld1q_x4_v(&__ret, __p0, 43); \
	12945	__ret; \
	12946	})
	12947	#else
	12948	#define vld1q_bf16_x4(__p0) __extension__ ({ \
	12949	bfloat16x8x4_t __ret; \
	12950	__builtin_neon_vld1q_x4_v(&__ret, __p0, 43); \
	12951	\
	12952	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	12953	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	12954	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	12955	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
	12956	__ret; \
	12957	})
	12958	#endif
	12959
	12960	#ifdef __LITTLE_ENDIAN__
	12961	#define vld1_bf16_x4(__p0) __extension__ ({ \
	12962	bfloat16x4x4_t __ret; \
	12963	__builtin_neon_vld1_x4_v(&__ret, __p0, 11); \
	12964	__ret; \
	12965	})
	12966	#else
	12967	#define vld1_bf16_x4(__p0) __extension__ ({ \
	12968	bfloat16x4x4_t __ret; \
	12969	__builtin_neon_vld1_x4_v(&__ret, __p0, 11); \
	12970	\
	12971	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	12972	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	12973	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	12974	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
	12975	__ret; \
	12976	})
	12977	#endif
	12978
13733	12979	#ifdef __LITTLE_ENDIAN__
13734	12980	#define vld2_p8(__p0) __extension__ ({ \
13735	12981	poly8x8x2_t __ret; \
...	...	@@ -14046,6 +13292,40 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
14046	13292	})
14047	13293	#endif
14048	13294
	13295	#ifdef __LITTLE_ENDIAN__
	13296	#define vld2q_bf16(__p0) __extension__ ({ \
	13297	bfloat16x8x2_t __ret; \
	13298	__builtin_neon_vld2q_v(&__ret, __p0, 43); \
	13299	__ret; \
	13300	})
	13301	#else
	13302	#define vld2q_bf16(__p0) __extension__ ({ \
	13303	bfloat16x8x2_t __ret; \
	13304	__builtin_neon_vld2q_v(&__ret, __p0, 43); \
	13305	\
	13306	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	13307	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	13308	__ret; \
	13309	})
	13310	#endif
	13311
	13312	#ifdef __LITTLE_ENDIAN__
	13313	#define vld2_bf16(__p0) __extension__ ({ \
	13314	bfloat16x4x2_t __ret; \
	13315	__builtin_neon_vld2_v(&__ret, __p0, 11); \
	13316	__ret; \
	13317	})
	13318	#else
	13319	#define vld2_bf16(__p0) __extension__ ({ \
	13320	bfloat16x4x2_t __ret; \
	13321	__builtin_neon_vld2_v(&__ret, __p0, 11); \
	13322	\
	13323	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	13324	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	13325	__ret; \
	13326	})
	13327	#endif
	13328
14049	13329	#ifdef __LITTLE_ENDIAN__
14050	13330	#define vld2_dup_p8(__p0) __extension__ ({ \
14051	13331	poly8x8x2_t __ret; \
...	...	@@ -14396,6 +13676,40 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
14396	13676	})
14397	13677	#endif
14398	13678
	13679	#ifdef __LITTLE_ENDIAN__
	13680	#define vld2q_dup_bf16(__p0) __extension__ ({ \
	13681	bfloat16x8x2_t __ret; \
	13682	__builtin_neon_vld2q_dup_v(&__ret, __p0, 43); \
	13683	__ret; \
	13684	})
	13685	#else
	13686	#define vld2q_dup_bf16(__p0) __extension__ ({ \
	13687	bfloat16x8x2_t __ret; \
	13688	__builtin_neon_vld2q_dup_v(&__ret, __p0, 43); \
	13689	\
	13690	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	13691	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	13692	__ret; \
	13693	})
	13694	#endif
	13695
	13696	#ifdef __LITTLE_ENDIAN__
	13697	#define vld2_dup_bf16(__p0) __extension__ ({ \
	13698	bfloat16x4x2_t __ret; \
	13699	__builtin_neon_vld2_dup_v(&__ret, __p0, 11); \
	13700	__ret; \
	13701	})
	13702	#else
	13703	#define vld2_dup_bf16(__p0) __extension__ ({ \
	13704	bfloat16x4x2_t __ret; \
	13705	__builtin_neon_vld2_dup_v(&__ret, __p0, 11); \
	13706	\
	13707	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	13708	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	13709	__ret; \
	13710	})
	13711	#endif
	13712
14399	13713	#ifdef __LITTLE_ENDIAN__
14400	13714	#define vld2_lane_p8(__p0, __p1, __p2) __extension__ ({ \
14401	13715	poly8x8x2_t __ret; \
...	...	@@ -14726,6 +14040,50 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
14726	14040	})
14727	14041	#endif
14728	14042
	14043	#ifdef __LITTLE_ENDIAN__
	14044	#define vld2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	14045	bfloat16x8x2_t __ret; \
	14046	bfloat16x8x2_t __s1 = __p1; \
	14047	__builtin_neon_vld2q_lane_v(&__ret, __p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __p2, 43); \
	14048	__ret; \
	14049	})
	14050	#else
	14051	#define vld2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	14052	bfloat16x8x2_t __ret; \
	14053	bfloat16x8x2_t __s1 = __p1; \
	14054	bfloat16x8x2_t __rev1; \
	14055	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	14056	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	14057	__builtin_neon_vld2q_lane_v(&__ret, __p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __p2, 43); \
	14058	\
	14059	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	14060	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	14061	__ret; \
	14062	})
	14063	#endif
	14064
	14065	#ifdef __LITTLE_ENDIAN__
	14066	#define vld2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	14067	bfloat16x4x2_t __ret; \
	14068	bfloat16x4x2_t __s1 = __p1; \
	14069	__builtin_neon_vld2_lane_v(&__ret, __p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __p2, 11); \
	14070	__ret; \
	14071	})
	14072	#else
	14073	#define vld2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	14074	bfloat16x4x2_t __ret; \
	14075	bfloat16x4x2_t __s1 = __p1; \
	14076	bfloat16x4x2_t __rev1; \
	14077	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	14078	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	14079	__builtin_neon_vld2_lane_v(&__ret, __p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __p2, 11); \
	14080	\
	14081	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	14082	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	14083	__ret; \
	14084	})
	14085	#endif
	14086
14729	14087	#ifdef __LITTLE_ENDIAN__
14730	14088	#define vld3_p8(__p0) __extension__ ({ \
14731	14089	poly8x8x3_t __ret; \
...	...	@@ -15060,6 +14418,42 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
15060	14418	})
15061	14419	#endif
15062	14420
	14421	#ifdef __LITTLE_ENDIAN__
	14422	#define vld3q_bf16(__p0) __extension__ ({ \
	14423	bfloat16x8x3_t __ret; \
	14424	__builtin_neon_vld3q_v(&__ret, __p0, 43); \
	14425	__ret; \
	14426	})
	14427	#else
	14428	#define vld3q_bf16(__p0) __extension__ ({ \
	14429	bfloat16x8x3_t __ret; \
	14430	__builtin_neon_vld3q_v(&__ret, __p0, 43); \
	14431	\
	14432	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	14433	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	14434	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	14435	__ret; \
	14436	})
	14437	#endif
	14438
	14439	#ifdef __LITTLE_ENDIAN__
	14440	#define vld3_bf16(__p0) __extension__ ({ \
	14441	bfloat16x4x3_t __ret; \
	14442	__builtin_neon_vld3_v(&__ret, __p0, 11); \
	14443	__ret; \
	14444	})
	14445	#else
	14446	#define vld3_bf16(__p0) __extension__ ({ \
	14447	bfloat16x4x3_t __ret; \
	14448	__builtin_neon_vld3_v(&__ret, __p0, 11); \
	14449	\
	14450	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	14451	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	14452	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	14453	__ret; \
	14454	})
	14455	#endif
	14456
15063	14457	#ifdef __LITTLE_ENDIAN__
15064	14458	#define vld3_dup_p8(__p0) __extension__ ({ \
15065	14459	poly8x8x3_t __ret; \
...	...	@@ -15430,6 +14824,42 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
15430	14824	})
15431	14825	#endif
15432	14826
	14827	#ifdef __LITTLE_ENDIAN__
	14828	#define vld3q_dup_bf16(__p0) __extension__ ({ \
	14829	bfloat16x8x3_t __ret; \
	14830	__builtin_neon_vld3q_dup_v(&__ret, __p0, 43); \
	14831	__ret; \
	14832	})
	14833	#else
	14834	#define vld3q_dup_bf16(__p0) __extension__ ({ \
	14835	bfloat16x8x3_t __ret; \
	14836	__builtin_neon_vld3q_dup_v(&__ret, __p0, 43); \
	14837	\
	14838	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	14839	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	14840	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	14841	__ret; \
	14842	})
	14843	#endif
	14844
	14845	#ifdef __LITTLE_ENDIAN__
	14846	#define vld3_dup_bf16(__p0) __extension__ ({ \
	14847	bfloat16x4x3_t __ret; \
	14848	__builtin_neon_vld3_dup_v(&__ret, __p0, 11); \
	14849	__ret; \
	14850	})
	14851	#else
	14852	#define vld3_dup_bf16(__p0) __extension__ ({ \
	14853	bfloat16x4x3_t __ret; \
	14854	__builtin_neon_vld3_dup_v(&__ret, __p0, 11); \
	14855	\
	14856	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	14857	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	14858	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	14859	__ret; \
	14860	})
	14861	#endif
	14862
15433	14863	#ifdef __LITTLE_ENDIAN__
15434	14864	#define vld3_lane_p8(__p0, __p1, __p2) __extension__ ({ \
15435	14865	poly8x8x3_t __ret; \
...	...	@@ -15790,6 +15220,54 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
15790	15220	})
15791	15221	#endif
15792	15222
	15223	#ifdef __LITTLE_ENDIAN__
	15224	#define vld3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	15225	bfloat16x8x3_t __ret; \
	15226	bfloat16x8x3_t __s1 = __p1; \
	15227	__builtin_neon_vld3q_lane_v(&__ret, __p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __p2, 43); \
	15228	__ret; \
	15229	})
	15230	#else
	15231	#define vld3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	15232	bfloat16x8x3_t __ret; \
	15233	bfloat16x8x3_t __s1 = __p1; \
	15234	bfloat16x8x3_t __rev1; \
	15235	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	15236	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	15237	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	15238	__builtin_neon_vld3q_lane_v(&__ret, __p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __p2, 43); \
	15239	\
	15240	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	15241	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	15242	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	15243	__ret; \
	15244	})
	15245	#endif
	15246
	15247	#ifdef __LITTLE_ENDIAN__
	15248	#define vld3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	15249	bfloat16x4x3_t __ret; \
	15250	bfloat16x4x3_t __s1 = __p1; \
	15251	__builtin_neon_vld3_lane_v(&__ret, __p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __p2, 11); \
	15252	__ret; \
	15253	})
	15254	#else
	15255	#define vld3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	15256	bfloat16x4x3_t __ret; \
	15257	bfloat16x4x3_t __s1 = __p1; \
	15258	bfloat16x4x3_t __rev1; \
	15259	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	15260	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	15261	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	15262	__builtin_neon_vld3_lane_v(&__ret, __p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __p2, 11); \
	15263	\
	15264	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	15265	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	15266	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	15267	__ret; \
	15268	})
	15269	#endif
	15270
15793	15271	#ifdef __LITTLE_ENDIAN__
15794	15272	#define vld4_p8(__p0) __extension__ ({ \
15795	15273	poly8x8x4_t __ret; \
...	...	@@ -16142,6 +15620,44 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
16142	15620	})
16143	15621	#endif
16144	15622
	15623	#ifdef __LITTLE_ENDIAN__
	15624	#define vld4q_bf16(__p0) __extension__ ({ \
	15625	bfloat16x8x4_t __ret; \
	15626	__builtin_neon_vld4q_v(&__ret, __p0, 43); \
	15627	__ret; \
	15628	})
	15629	#else
	15630	#define vld4q_bf16(__p0) __extension__ ({ \
	15631	bfloat16x8x4_t __ret; \
	15632	__builtin_neon_vld4q_v(&__ret, __p0, 43); \
	15633	\
	15634	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	15635	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	15636	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	15637	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
	15638	__ret; \
	15639	})
	15640	#endif
	15641
	15642	#ifdef __LITTLE_ENDIAN__
	15643	#define vld4_bf16(__p0) __extension__ ({ \
	15644	bfloat16x4x4_t __ret; \
	15645	__builtin_neon_vld4_v(&__ret, __p0, 11); \
	15646	__ret; \
	15647	})
	15648	#else
	15649	#define vld4_bf16(__p0) __extension__ ({ \
	15650	bfloat16x4x4_t __ret; \
	15651	__builtin_neon_vld4_v(&__ret, __p0, 11); \
	15652	\
	15653	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	15654	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	15655	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	15656	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
	15657	__ret; \
	15658	})
	15659	#endif
	15660
16145	15661	#ifdef __LITTLE_ENDIAN__
16146	15662	#define vld4_dup_p8(__p0) __extension__ ({ \
16147	15663	poly8x8x4_t __ret; \
...	...	@@ -16532,6 +16048,44 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
16532	16048	})
16533	16049	#endif
16534	16050
	16051	#ifdef __LITTLE_ENDIAN__
	16052	#define vld4q_dup_bf16(__p0) __extension__ ({ \
	16053	bfloat16x8x4_t __ret; \
	16054	__builtin_neon_vld4q_dup_v(&__ret, __p0, 43); \
	16055	__ret; \
	16056	})
	16057	#else
	16058	#define vld4q_dup_bf16(__p0) __extension__ ({ \
	16059	bfloat16x8x4_t __ret; \
	16060	__builtin_neon_vld4q_dup_v(&__ret, __p0, 43); \
	16061	\
	16062	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	16063	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	16064	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	16065	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
	16066	__ret; \
	16067	})
	16068	#endif
	16069
	16070	#ifdef __LITTLE_ENDIAN__
	16071	#define vld4_dup_bf16(__p0) __extension__ ({ \
	16072	bfloat16x4x4_t __ret; \
	16073	__builtin_neon_vld4_dup_v(&__ret, __p0, 11); \
	16074	__ret; \
	16075	})
	16076	#else
	16077	#define vld4_dup_bf16(__p0) __extension__ ({ \
	16078	bfloat16x4x4_t __ret; \
	16079	__builtin_neon_vld4_dup_v(&__ret, __p0, 11); \
	16080	\
	16081	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	16082	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	16083	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	16084	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
	16085	__ret; \
	16086	})
	16087	#endif
	16088
16535	16089	#ifdef __LITTLE_ENDIAN__
16536	16090	#define vld4_lane_p8(__p0, __p1, __p2) __extension__ ({ \
16537	16091	poly8x8x4_t __ret; \
...	...	@@ -16922,6 +16476,58 @@ __ai __attribute__((target("neon"))) int16x4_t vhsub_s16(int16x4_t __p0, int16x4
16922	16476	})
16923	16477	#endif
16924	16478
	16479	#ifdef __LITTLE_ENDIAN__
	16480	#define vld4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	16481	bfloat16x8x4_t __ret; \
	16482	bfloat16x8x4_t __s1 = __p1; \
	16483	__builtin_neon_vld4q_lane_v(&__ret, __p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), __p2, 43); \
	16484	__ret; \
	16485	})
	16486	#else
	16487	#define vld4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	16488	bfloat16x8x4_t __ret; \
	16489	bfloat16x8x4_t __s1 = __p1; \
	16490	bfloat16x8x4_t __rev1; \
	16491	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	16492	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	16493	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	16494	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
	16495	__builtin_neon_vld4q_lane_v(&__ret, __p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), __p2, 43); \
	16496	\
	16497	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_128_16); \
	16498	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_128_16); \
	16499	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_128_16); \
	16500	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_128_16); \
	16501	__ret; \
	16502	})
	16503	#endif
	16504
	16505	#ifdef __LITTLE_ENDIAN__
	16506	#define vld4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	16507	bfloat16x4x4_t __ret; \
	16508	bfloat16x4x4_t __s1 = __p1; \
	16509	__builtin_neon_vld4_lane_v(&__ret, __p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), __p2, 11); \
	16510	__ret; \
	16511	})
	16512	#else
	16513	#define vld4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	16514	bfloat16x4x4_t __ret; \
	16515	bfloat16x4x4_t __s1 = __p1; \
	16516	bfloat16x4x4_t __rev1; \
	16517	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	16518	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	16519	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	16520	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
	16521	__builtin_neon_vld4_lane_v(&__ret, __p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), __p2, 11); \
	16522	\
	16523	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], __lane_reverse_64_16); \
	16524	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], __lane_reverse_64_16); \
	16525	__ret.val[2] = __builtin_shufflevector(__ret.val[2], __ret.val[2], __lane_reverse_64_16); \
	16526	__ret.val[3] = __builtin_shufflevector(__ret.val[3], __ret.val[3], __lane_reverse_64_16); \
	16527	__ret; \
	16528	})
	16529	#endif
	16530
16925	16531	#ifdef __LITTLE_ENDIAN__
16926	16532	__ai __attribute__((target("neon"))) uint8x16_t vmaxq_u8(uint8x16_t __p0, uint8x16_t __p1) {
16927	16533	uint8x16_t __ret;
...	...	@@ -27576,6 +27182,60 @@ __ai __attribute__((target("neon"))) int8x8_t __noswap_vrsubhn_s16(int16x8_t __p
27576	27182	})
27577	27183	#endif
27578	27184
	27185	#ifdef __LITTLE_ENDIAN__
	27186	#define vsetq_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	27187	bfloat16x8_t __ret; \
	27188	bfloat16_t __s0 = __p0; \
	27189	bfloat16x8_t __s1 = __p1; \
	27190	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vsetq_lane_bf16(__s0, __s1, __p2)); \
	27191	__ret; \
	27192	})
	27193	#else
	27194	#define vsetq_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	27195	bfloat16x8_t __ret; \
	27196	bfloat16_t __s0 = __p0; \
	27197	bfloat16x8_t __s1 = __p1; \
	27198	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	27199	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vsetq_lane_bf16(__s0, __rev1, __p2)); \
	27200	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	27201	__ret; \
	27202	})
	27203	#define __noswap_vsetq_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	27204	bfloat16x8_t __ret; \
	27205	bfloat16_t __s0 = __p0; \
	27206	bfloat16x8_t __s1 = __p1; \
	27207	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vsetq_lane_bf16(__s0, __s1, __p2)); \
	27208	__ret; \
	27209	})
	27210	#endif
	27211
	27212	#ifdef __LITTLE_ENDIAN__
	27213	#define vset_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	27214	bfloat16x4_t __ret; \
	27215	bfloat16_t __s0 = __p0; \
	27216	bfloat16x4_t __s1 = __p1; \
	27217	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vset_lane_bf16(__s0, __s1, __p2)); \
	27218	__ret; \
	27219	})
	27220	#else
	27221	#define vset_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	27222	bfloat16x4_t __ret; \
	27223	bfloat16_t __s0 = __p0; \
	27224	bfloat16x4_t __s1 = __p1; \
	27225	bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	27226	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vset_lane_bf16(__s0, __rev1, __p2)); \
	27227	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	27228	__ret; \
	27229	})
	27230	#define __noswap_vset_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	27231	bfloat16x4_t __ret; \
	27232	bfloat16_t __s0 = __p0; \
	27233	bfloat16x4_t __s1 = __p1; \
	27234	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vset_lane_bf16(__s0, __s1, __p2)); \
	27235	__ret; \
	27236	})
	27237	#endif
	27238
27579	27239	#ifdef __LITTLE_ENDIAN__
27580	27240	__ai __attribute__((target("neon"))) uint8x16_t vshlq_u8(uint8x16_t __p0, int8x16_t __p1) {
27581	27241	uint8x16_t __ret;
...	...	@@ -30000,6 +29660,32 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
30000	29660	})
30001	29661	#endif
30002	29662
	29663	#ifdef __LITTLE_ENDIAN__
	29664	#define vst1q_bf16(__p0, __p1) __extension__ ({ \
	29665	bfloat16x8_t __s1 = __p1; \
	29666	__builtin_neon_vst1q_v(__p0, __builtin_bit_cast(int8x16_t, __s1), 43); \
	29667	})
	29668	#else
	29669	#define vst1q_bf16(__p0, __p1) __extension__ ({ \
	29670	bfloat16x8_t __s1 = __p1; \
	29671	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	29672	__builtin_neon_vst1q_v(__p0, __builtin_bit_cast(int8x16_t, __rev1), 43); \
	29673	})
	29674	#endif
	29675
	29676	#ifdef __LITTLE_ENDIAN__
	29677	#define vst1_bf16(__p0, __p1) __extension__ ({ \
	29678	bfloat16x4_t __s1 = __p1; \
	29679	__builtin_neon_vst1_v(__p0, __builtin_bit_cast(int8x8_t, __s1), 11); \
	29680	})
	29681	#else
	29682	#define vst1_bf16(__p0, __p1) __extension__ ({ \
	29683	bfloat16x4_t __s1 = __p1; \
	29684	bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	29685	__builtin_neon_vst1_v(__p0, __builtin_bit_cast(int8x8_t, __rev1), 11); \
	29686	})
	29687	#endif
	29688
30003	29689	#ifdef __LITTLE_ENDIAN__
30004	29690	#define vst1_lane_p8(__p0, __p1, __p2) __extension__ ({ \
30005	29691	poly8x8_t __s1 = __p1; \
...	...	@@ -30268,6 +29954,32 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
30268	29954	})
30269	29955	#endif
30270	29956
	29957	#ifdef __LITTLE_ENDIAN__
	29958	#define vst1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	29959	bfloat16x8_t __s1 = __p1; \
	29960	__builtin_neon_vst1q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __s1), __p2, 43); \
	29961	})
	29962	#else
	29963	#define vst1q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	29964	bfloat16x8_t __s1 = __p1; \
	29965	bfloat16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	29966	__builtin_neon_vst1q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __rev1), __p2, 43); \
	29967	})
	29968	#endif
	29969
	29970	#ifdef __LITTLE_ENDIAN__
	29971	#define vst1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	29972	bfloat16x4_t __s1 = __p1; \
	29973	__builtin_neon_vst1_lane_v(__p0, __builtin_bit_cast(int8x8_t, __s1), __p2, 11); \
	29974	})
	29975	#else
	29976	#define vst1_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	29977	bfloat16x4_t __s1 = __p1; \
	29978	bfloat16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	29979	__builtin_neon_vst1_lane_v(__p0, __builtin_bit_cast(int8x8_t, __rev1), __p2, 11); \
	29980	})
	29981	#endif
	29982
30271	29983	#ifdef __LITTLE_ENDIAN__
30272	29984	#define vst1_p8_x2(__p0, __p1) __extension__ ({ \
30273	29985	poly8x8x2_t __s1 = __p1; \
...	...	@@ -30576,6 +30288,36 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
30576	30288	})
30577	30289	#endif
30578	30290
	30291	#ifdef __LITTLE_ENDIAN__
	30292	#define vst1q_bf16_x2(__p0, __p1) __extension__ ({ \
	30293	bfloat16x8x2_t __s1 = __p1; \
	30294	__builtin_neon_vst1q_x2_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), 43); \
	30295	})
	30296	#else
	30297	#define vst1q_bf16_x2(__p0, __p1) __extension__ ({ \
	30298	bfloat16x8x2_t __s1 = __p1; \
	30299	bfloat16x8x2_t __rev1; \
	30300	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	30301	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	30302	__builtin_neon_vst1q_x2_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), 43); \
	30303	})
	30304	#endif
	30305
	30306	#ifdef __LITTLE_ENDIAN__
	30307	#define vst1_bf16_x2(__p0, __p1) __extension__ ({ \
	30308	bfloat16x4x2_t __s1 = __p1; \
	30309	__builtin_neon_vst1_x2_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), 11); \
	30310	})
	30311	#else
	30312	#define vst1_bf16_x2(__p0, __p1) __extension__ ({ \
	30313	bfloat16x4x2_t __s1 = __p1; \
	30314	bfloat16x4x2_t __rev1; \
	30315	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	30316	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	30317	__builtin_neon_vst1_x2_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), 11); \
	30318	})
	30319	#endif
	30320
30579	30321	#ifdef __LITTLE_ENDIAN__
30580	30322	#define vst1_p8_x3(__p0, __p1) __extension__ ({ \
30581	30323	poly8x8x3_t __s1 = __p1; \
...	...	@@ -30904,6 +30646,38 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
30904	30646	})
30905	30647	#endif
30906	30648
	30649	#ifdef __LITTLE_ENDIAN__
	30650	#define vst1q_bf16_x3(__p0, __p1) __extension__ ({ \
	30651	bfloat16x8x3_t __s1 = __p1; \
	30652	__builtin_neon_vst1q_x3_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), 43); \
	30653	})
	30654	#else
	30655	#define vst1q_bf16_x3(__p0, __p1) __extension__ ({ \
	30656	bfloat16x8x3_t __s1 = __p1; \
	30657	bfloat16x8x3_t __rev1; \
	30658	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	30659	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	30660	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	30661	__builtin_neon_vst1q_x3_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), 43); \
	30662	})
	30663	#endif
	30664
	30665	#ifdef __LITTLE_ENDIAN__
	30666	#define vst1_bf16_x3(__p0, __p1) __extension__ ({ \
	30667	bfloat16x4x3_t __s1 = __p1; \
	30668	__builtin_neon_vst1_x3_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), 11); \
	30669	})
	30670	#else
	30671	#define vst1_bf16_x3(__p0, __p1) __extension__ ({ \
	30672	bfloat16x4x3_t __s1 = __p1; \
	30673	bfloat16x4x3_t __rev1; \
	30674	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	30675	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	30676	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	30677	__builtin_neon_vst1_x3_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), 11); \
	30678	})
	30679	#endif
	30680
30907	30681	#ifdef __LITTLE_ENDIAN__
30908	30682	#define vst1_p8_x4(__p0, __p1) __extension__ ({ \
30909	30683	poly8x8x4_t __s1 = __p1; \
...	...	@@ -31252,6 +31026,40 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
31252	31026	})
31253	31027	#endif
31254	31028
	31029	#ifdef __LITTLE_ENDIAN__
	31030	#define vst1q_bf16_x4(__p0, __p1) __extension__ ({ \
	31031	bfloat16x8x4_t __s1 = __p1; \
	31032	__builtin_neon_vst1q_x4_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), 43); \
	31033	})
	31034	#else
	31035	#define vst1q_bf16_x4(__p0, __p1) __extension__ ({ \
	31036	bfloat16x8x4_t __s1 = __p1; \
	31037	bfloat16x8x4_t __rev1; \
	31038	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	31039	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	31040	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	31041	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
	31042	__builtin_neon_vst1q_x4_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), 43); \
	31043	})
	31044	#endif
	31045
	31046	#ifdef __LITTLE_ENDIAN__
	31047	#define vst1_bf16_x4(__p0, __p1) __extension__ ({ \
	31048	bfloat16x4x4_t __s1 = __p1; \
	31049	__builtin_neon_vst1_x4_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), 11); \
	31050	})
	31051	#else
	31052	#define vst1_bf16_x4(__p0, __p1) __extension__ ({ \
	31053	bfloat16x4x4_t __s1 = __p1; \
	31054	bfloat16x4x4_t __rev1; \
	31055	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	31056	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	31057	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	31058	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
	31059	__builtin_neon_vst1_x4_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), 11); \
	31060	})
	31061	#endif
	31062
31255	31063	#ifdef __LITTLE_ENDIAN__
31256	31064	#define vst2_p8(__p0, __p1) __extension__ ({ \
31257	31065	poly8x8x2_t __s1 = __p1; \
...	...	@@ -31530,6 +31338,36 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
31530	31338	})
31531	31339	#endif
31532	31340
	31341	#ifdef __LITTLE_ENDIAN__
	31342	#define vst2q_bf16(__p0, __p1) __extension__ ({ \
	31343	bfloat16x8x2_t __s1 = __p1; \
	31344	__builtin_neon_vst2q_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), 43); \
	31345	})
	31346	#else
	31347	#define vst2q_bf16(__p0, __p1) __extension__ ({ \
	31348	bfloat16x8x2_t __s1 = __p1; \
	31349	bfloat16x8x2_t __rev1; \
	31350	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	31351	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	31352	__builtin_neon_vst2q_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), 43); \
	31353	})
	31354	#endif
	31355
	31356	#ifdef __LITTLE_ENDIAN__
	31357	#define vst2_bf16(__p0, __p1) __extension__ ({ \
	31358	bfloat16x4x2_t __s1 = __p1; \
	31359	__builtin_neon_vst2_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), 11); \
	31360	})
	31361	#else
	31362	#define vst2_bf16(__p0, __p1) __extension__ ({ \
	31363	bfloat16x4x2_t __s1 = __p1; \
	31364	bfloat16x4x2_t __rev1; \
	31365	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	31366	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	31367	__builtin_neon_vst2_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), 11); \
	31368	})
	31369	#endif
	31370
31533	31371	#ifdef __LITTLE_ENDIAN__
31534	31372	#define vst2_lane_p8(__p0, __p1, __p2) __extension__ ({ \
31535	31373	poly8x8x2_t __s1 = __p1; \
...	...	@@ -31755,6 +31593,36 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
31755	31593	})
31756	31594	#endif
31757	31595
	31596	#ifdef __LITTLE_ENDIAN__
	31597	#define vst2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	31598	bfloat16x8x2_t __s1 = __p1; \
	31599	__builtin_neon_vst2q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __p2, 43); \
	31600	})
	31601	#else
	31602	#define vst2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	31603	bfloat16x8x2_t __s1 = __p1; \
	31604	bfloat16x8x2_t __rev1; \
	31605	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	31606	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	31607	__builtin_neon_vst2q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __p2, 43); \
	31608	})
	31609	#endif
	31610
	31611	#ifdef __LITTLE_ENDIAN__
	31612	#define vst2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	31613	bfloat16x4x2_t __s1 = __p1; \
	31614	__builtin_neon_vst2_lane_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __p2, 11); \
	31615	})
	31616	#else
	31617	#define vst2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	31618	bfloat16x4x2_t __s1 = __p1; \
	31619	bfloat16x4x2_t __rev1; \
	31620	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	31621	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	31622	__builtin_neon_vst2_lane_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __p2, 11); \
	31623	})
	31624	#endif
	31625
31758	31626	#ifdef __LITTLE_ENDIAN__
31759	31627	#define vst3_p8(__p0, __p1) __extension__ ({ \
31760	31628	poly8x8x3_t __s1 = __p1; \
...	...	@@ -32051,6 +31919,38 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
32051	31919	})
32052	31920	#endif
32053	31921
	31922	#ifdef __LITTLE_ENDIAN__
	31923	#define vst3q_bf16(__p0, __p1) __extension__ ({ \
	31924	bfloat16x8x3_t __s1 = __p1; \
	31925	__builtin_neon_vst3q_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), 43); \
	31926	})
	31927	#else
	31928	#define vst3q_bf16(__p0, __p1) __extension__ ({ \
	31929	bfloat16x8x3_t __s1 = __p1; \
	31930	bfloat16x8x3_t __rev1; \
	31931	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	31932	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	31933	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	31934	__builtin_neon_vst3q_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), 43); \
	31935	})
	31936	#endif
	31937
	31938	#ifdef __LITTLE_ENDIAN__
	31939	#define vst3_bf16(__p0, __p1) __extension__ ({ \
	31940	bfloat16x4x3_t __s1 = __p1; \
	31941	__builtin_neon_vst3_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), 11); \
	31942	})
	31943	#else
	31944	#define vst3_bf16(__p0, __p1) __extension__ ({ \
	31945	bfloat16x4x3_t __s1 = __p1; \
	31946	bfloat16x4x3_t __rev1; \
	31947	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	31948	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	31949	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	31950	__builtin_neon_vst3_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), 11); \
	31951	})
	31952	#endif
	31953
32054	31954	#ifdef __LITTLE_ENDIAN__
32055	31955	#define vst3_lane_p8(__p0, __p1, __p2) __extension__ ({ \
32056	31956	poly8x8x3_t __s1 = __p1; \
...	...	@@ -32291,6 +32191,38 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
32291	32191	})
32292	32192	#endif
32293	32193
	32194	#ifdef __LITTLE_ENDIAN__
	32195	#define vst3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32196	bfloat16x8x3_t __s1 = __p1; \
	32197	__builtin_neon_vst3q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __p2, 43); \
	32198	})
	32199	#else
	32200	#define vst3q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32201	bfloat16x8x3_t __s1 = __p1; \
	32202	bfloat16x8x3_t __rev1; \
	32203	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	32204	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	32205	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	32206	__builtin_neon_vst3q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __p2, 43); \
	32207	})
	32208	#endif
	32209
	32210	#ifdef __LITTLE_ENDIAN__
	32211	#define vst3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32212	bfloat16x4x3_t __s1 = __p1; \
	32213	__builtin_neon_vst3_lane_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __p2, 11); \
	32214	})
	32215	#else
	32216	#define vst3_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32217	bfloat16x4x3_t __s1 = __p1; \
	32218	bfloat16x4x3_t __rev1; \
	32219	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	32220	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	32221	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	32222	__builtin_neon_vst3_lane_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __p2, 11); \
	32223	})
	32224	#endif
	32225
32294	32226	#ifdef __LITTLE_ENDIAN__
32295	32227	#define vst4_p8(__p0, __p1) __extension__ ({ \
32296	32228	poly8x8x4_t __s1 = __p1; \
...	...	@@ -32605,6 +32537,40 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
32605	32537	})
32606	32538	#endif
32607	32539
	32540	#ifdef __LITTLE_ENDIAN__
	32541	#define vst4q_bf16(__p0, __p1) __extension__ ({ \
	32542	bfloat16x8x4_t __s1 = __p1; \
	32543	__builtin_neon_vst4q_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), 43); \
	32544	})
	32545	#else
	32546	#define vst4q_bf16(__p0, __p1) __extension__ ({ \
	32547	bfloat16x8x4_t __s1 = __p1; \
	32548	bfloat16x8x4_t __rev1; \
	32549	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	32550	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	32551	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	32552	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
	32553	__builtin_neon_vst4q_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), 43); \
	32554	})
	32555	#endif
	32556
	32557	#ifdef __LITTLE_ENDIAN__
	32558	#define vst4_bf16(__p0, __p1) __extension__ ({ \
	32559	bfloat16x4x4_t __s1 = __p1; \
	32560	__builtin_neon_vst4_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), 11); \
	32561	})
	32562	#else
	32563	#define vst4_bf16(__p0, __p1) __extension__ ({ \
	32564	bfloat16x4x4_t __s1 = __p1; \
	32565	bfloat16x4x4_t __rev1; \
	32566	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	32567	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	32568	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	32569	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
	32570	__builtin_neon_vst4_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), 11); \
	32571	})
	32572	#endif
	32573
32608	32574	#ifdef __LITTLE_ENDIAN__
32609	32575	#define vst4_lane_p8(__p0, __p1, __p2) __extension__ ({ \
32610	32576	poly8x8x4_t __s1 = __p1; \
...	...	@@ -32860,6 +32826,40 @@ __ai __attribute__((target("neon"))) int16x4_t vshl_s16(int16x4_t __p0, int16x4_
32860	32826	})
32861	32827	#endif
32862	32828
	32829	#ifdef __LITTLE_ENDIAN__
	32830	#define vst4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32831	bfloat16x8x4_t __s1 = __p1; \
	32832	__builtin_neon_vst4q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __s1.val[0]), __builtin_bit_cast(int8x16_t, __s1.val[1]), __builtin_bit_cast(int8x16_t, __s1.val[2]), __builtin_bit_cast(int8x16_t, __s1.val[3]), __p2, 43); \
	32833	})
	32834	#else
	32835	#define vst4q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32836	bfloat16x8x4_t __s1 = __p1; \
	32837	bfloat16x8x4_t __rev1; \
	32838	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_128_16); \
	32839	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_128_16); \
	32840	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_128_16); \
	32841	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_128_16); \
	32842	__builtin_neon_vst4q_lane_v(__p0, __builtin_bit_cast(int8x16_t, __rev1.val[0]), __builtin_bit_cast(int8x16_t, __rev1.val[1]), __builtin_bit_cast(int8x16_t, __rev1.val[2]), __builtin_bit_cast(int8x16_t, __rev1.val[3]), __p2, 43); \
	32843	})
	32844	#endif
	32845
	32846	#ifdef __LITTLE_ENDIAN__
	32847	#define vst4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32848	bfloat16x4x4_t __s1 = __p1; \
	32849	__builtin_neon_vst4_lane_v(__p0, __builtin_bit_cast(int8x8_t, __s1.val[0]), __builtin_bit_cast(int8x8_t, __s1.val[1]), __builtin_bit_cast(int8x8_t, __s1.val[2]), __builtin_bit_cast(int8x8_t, __s1.val[3]), __p2, 11); \
	32850	})
	32851	#else
	32852	#define vst4_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	32853	bfloat16x4x4_t __s1 = __p1; \
	32854	bfloat16x4x4_t __rev1; \
	32855	__rev1.val[0] = __builtin_shufflevector(__s1.val[0], __s1.val[0], __lane_reverse_64_16); \
	32856	__rev1.val[1] = __builtin_shufflevector(__s1.val[1], __s1.val[1], __lane_reverse_64_16); \
	32857	__rev1.val[2] = __builtin_shufflevector(__s1.val[2], __s1.val[2], __lane_reverse_64_16); \
	32858	__rev1.val[3] = __builtin_shufflevector(__s1.val[3], __s1.val[3], __lane_reverse_64_16); \
	32859	__builtin_neon_vst4_lane_v(__p0, __builtin_bit_cast(int8x8_t, __rev1.val[0]), __builtin_bit_cast(int8x8_t, __rev1.val[1]), __builtin_bit_cast(int8x8_t, __rev1.val[2]), __builtin_bit_cast(int8x8_t, __rev1.val[3]), __p2, 11); \
	32860	})
	32861	#endif
	32862
32863	32863	#ifdef __LITTLE_ENDIAN__
32864	32864	__ai __attribute__((target("neon"))) uint8x16_t vsubq_u8(uint8x16_t __p0, uint8x16_t __p1) {
32865	32865	uint8x16_t __ret;
...	...	@@ -37083,266 +37083,6 @@ __ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_low_bf16_f32(float3
37083	37083	}
37084	37084	#endif
37085	37085
37086		__ai __attribute__((target("bf16,neon"))) poly8x8_t vreinterpret_p8_bf16(bfloat16x4_t __p0) {
37087		poly8x8_t __ret;
37088		__ret = __builtin_bit_cast(poly8x8_t, __p0);
37089		return __ret;
37090		}
37091		__ai __attribute__((target("bf16,neon"))) poly64x1_t vreinterpret_p64_bf16(bfloat16x4_t __p0) {
37092		poly64x1_t __ret;
37093		__ret = __builtin_bit_cast(poly64x1_t, __p0);
37094		return __ret;
37095		}
37096		__ai __attribute__((target("bf16,neon"))) poly16x4_t vreinterpret_p16_bf16(bfloat16x4_t __p0) {
37097		poly16x4_t __ret;
37098		__ret = __builtin_bit_cast(poly16x4_t, __p0);
37099		return __ret;
37100		}
37101		__ai __attribute__((target("bf16,neon"))) poly8x16_t vreinterpretq_p8_bf16(bfloat16x8_t __p0) {
37102		poly8x16_t __ret;
37103		__ret = __builtin_bit_cast(poly8x16_t, __p0);
37104		return __ret;
37105		}
37106		__ai __attribute__((target("bf16,neon"))) poly64x2_t vreinterpretq_p64_bf16(bfloat16x8_t __p0) {
37107		poly64x2_t __ret;
37108		__ret = __builtin_bit_cast(poly64x2_t, __p0);
37109		return __ret;
37110		}
37111		__ai __attribute__((target("bf16,neon"))) poly16x8_t vreinterpretq_p16_bf16(bfloat16x8_t __p0) {
37112		poly16x8_t __ret;
37113		__ret = __builtin_bit_cast(poly16x8_t, __p0);
37114		return __ret;
37115		}
37116		__ai __attribute__((target("bf16,neon"))) uint8x16_t vreinterpretq_u8_bf16(bfloat16x8_t __p0) {
37117		uint8x16_t __ret;
37118		__ret = __builtin_bit_cast(uint8x16_t, __p0);
37119		return __ret;
37120		}
37121		__ai __attribute__((target("bf16,neon"))) uint32x4_t vreinterpretq_u32_bf16(bfloat16x8_t __p0) {
37122		uint32x4_t __ret;
37123		__ret = __builtin_bit_cast(uint32x4_t, __p0);
37124		return __ret;
37125		}
37126		__ai __attribute__((target("bf16,neon"))) uint64x2_t vreinterpretq_u64_bf16(bfloat16x8_t __p0) {
37127		uint64x2_t __ret;
37128		__ret = __builtin_bit_cast(uint64x2_t, __p0);
37129		return __ret;
37130		}
37131		__ai __attribute__((target("bf16,neon"))) uint16x8_t vreinterpretq_u16_bf16(bfloat16x8_t __p0) {
37132		uint16x8_t __ret;
37133		__ret = __builtin_bit_cast(uint16x8_t, __p0);
37134		return __ret;
37135		}
37136		__ai __attribute__((target("bf16,neon"))) int8x16_t vreinterpretq_s8_bf16(bfloat16x8_t __p0) {
37137		int8x16_t __ret;
37138		__ret = __builtin_bit_cast(int8x16_t, __p0);
37139		return __ret;
37140		}
37141		__ai __attribute__((target("bf16,neon"))) float32x4_t vreinterpretq_f32_bf16(bfloat16x8_t __p0) {
37142		float32x4_t __ret;
37143		__ret = __builtin_bit_cast(float32x4_t, __p0);
37144		return __ret;
37145		}
37146		__ai __attribute__((target("bf16,neon"))) float16x8_t vreinterpretq_f16_bf16(bfloat16x8_t __p0) {
37147		float16x8_t __ret;
37148		__ret = __builtin_bit_cast(float16x8_t, __p0);
37149		return __ret;
37150		}
37151		__ai __attribute__((target("bf16,neon"))) int32x4_t vreinterpretq_s32_bf16(bfloat16x8_t __p0) {
37152		int32x4_t __ret;
37153		__ret = __builtin_bit_cast(int32x4_t, __p0);
37154		return __ret;
37155		}
37156		__ai __attribute__((target("bf16,neon"))) int64x2_t vreinterpretq_s64_bf16(bfloat16x8_t __p0) {
37157		int64x2_t __ret;
37158		__ret = __builtin_bit_cast(int64x2_t, __p0);
37159		return __ret;
37160		}
37161		__ai __attribute__((target("bf16,neon"))) int16x8_t vreinterpretq_s16_bf16(bfloat16x8_t __p0) {
37162		int16x8_t __ret;
37163		__ret = __builtin_bit_cast(int16x8_t, __p0);
37164		return __ret;
37165		}
37166		__ai __attribute__((target("bf16,neon"))) uint8x8_t vreinterpret_u8_bf16(bfloat16x4_t __p0) {
37167		uint8x8_t __ret;
37168		__ret = __builtin_bit_cast(uint8x8_t, __p0);
37169		return __ret;
37170		}
37171		__ai __attribute__((target("bf16,neon"))) uint32x2_t vreinterpret_u32_bf16(bfloat16x4_t __p0) {
37172		uint32x2_t __ret;
37173		__ret = __builtin_bit_cast(uint32x2_t, __p0);
37174		return __ret;
37175		}
37176		__ai __attribute__((target("bf16,neon"))) uint64x1_t vreinterpret_u64_bf16(bfloat16x4_t __p0) {
37177		uint64x1_t __ret;
37178		__ret = __builtin_bit_cast(uint64x1_t, __p0);
37179		return __ret;
37180		}
37181		__ai __attribute__((target("bf16,neon"))) uint16x4_t vreinterpret_u16_bf16(bfloat16x4_t __p0) {
37182		uint16x4_t __ret;
37183		__ret = __builtin_bit_cast(uint16x4_t, __p0);
37184		return __ret;
37185		}
37186		__ai __attribute__((target("bf16,neon"))) int8x8_t vreinterpret_s8_bf16(bfloat16x4_t __p0) {
37187		int8x8_t __ret;
37188		__ret = __builtin_bit_cast(int8x8_t, __p0);
37189		return __ret;
37190		}
37191		__ai __attribute__((target("bf16,neon"))) float32x2_t vreinterpret_f32_bf16(bfloat16x4_t __p0) {
37192		float32x2_t __ret;
37193		__ret = __builtin_bit_cast(float32x2_t, __p0);
37194		return __ret;
37195		}
37196		__ai __attribute__((target("bf16,neon"))) float16x4_t vreinterpret_f16_bf16(bfloat16x4_t __p0) {
37197		float16x4_t __ret;
37198		__ret = __builtin_bit_cast(float16x4_t, __p0);
37199		return __ret;
37200		}
37201		__ai __attribute__((target("bf16,neon"))) int32x2_t vreinterpret_s32_bf16(bfloat16x4_t __p0) {
37202		int32x2_t __ret;
37203		__ret = __builtin_bit_cast(int32x2_t, __p0);
37204		return __ret;
37205		}
37206		__ai __attribute__((target("bf16,neon"))) int64x1_t vreinterpret_s64_bf16(bfloat16x4_t __p0) {
37207		int64x1_t __ret;
37208		__ret = __builtin_bit_cast(int64x1_t, __p0);
37209		return __ret;
37210		}
37211		__ai __attribute__((target("bf16,neon"))) int16x4_t vreinterpret_s16_bf16(bfloat16x4_t __p0) {
37212		int16x4_t __ret;
37213		__ret = __builtin_bit_cast(int16x4_t, __p0);
37214		return __ret;
37215		}
37216		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p8(poly8x16_t __p0) {
37217		bfloat16x8_t __ret;
37218		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37219		return __ret;
37220		}
37221		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p64(poly64x2_t __p0) {
37222		bfloat16x8_t __ret;
37223		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37224		return __ret;
37225		}
37226		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p16(poly16x8_t __p0) {
37227		bfloat16x8_t __ret;
37228		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37229		return __ret;
37230		}
37231		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u8(uint8x16_t __p0) {
37232		bfloat16x8_t __ret;
37233		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37234		return __ret;
37235		}
37236		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u32(uint32x4_t __p0) {
37237		bfloat16x8_t __ret;
37238		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37239		return __ret;
37240		}
37241		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u64(uint64x2_t __p0) {
37242		bfloat16x8_t __ret;
37243		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37244		return __ret;
37245		}
37246		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u16(uint16x8_t __p0) {
37247		bfloat16x8_t __ret;
37248		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37249		return __ret;
37250		}
37251		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s8(int8x16_t __p0) {
37252		bfloat16x8_t __ret;
37253		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37254		return __ret;
37255		}
37256		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_f32(float32x4_t __p0) {
37257		bfloat16x8_t __ret;
37258		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37259		return __ret;
37260		}
37261		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_f16(float16x8_t __p0) {
37262		bfloat16x8_t __ret;
37263		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37264		return __ret;
37265		}
37266		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s32(int32x4_t __p0) {
37267		bfloat16x8_t __ret;
37268		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37269		return __ret;
37270		}
37271		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s64(int64x2_t __p0) {
37272		bfloat16x8_t __ret;
37273		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37274		return __ret;
37275		}
37276		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s16(int16x8_t __p0) {
37277		bfloat16x8_t __ret;
37278		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
37279		return __ret;
37280		}
37281		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_p8(poly8x8_t __p0) {
37282		bfloat16x4_t __ret;
37283		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37284		return __ret;
37285		}
37286		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_p64(poly64x1_t __p0) {
37287		bfloat16x4_t __ret;
37288		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37289		return __ret;
37290		}
37291		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_p16(poly16x4_t __p0) {
37292		bfloat16x4_t __ret;
37293		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37294		return __ret;
37295		}
37296		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u8(uint8x8_t __p0) {
37297		bfloat16x4_t __ret;
37298		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37299		return __ret;
37300		}
37301		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u32(uint32x2_t __p0) {
37302		bfloat16x4_t __ret;
37303		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37304		return __ret;
37305		}
37306		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u64(uint64x1_t __p0) {
37307		bfloat16x4_t __ret;
37308		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37309		return __ret;
37310		}
37311		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u16(uint16x4_t __p0) {
37312		bfloat16x4_t __ret;
37313		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37314		return __ret;
37315		}
37316		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s8(int8x8_t __p0) {
37317		bfloat16x4_t __ret;
37318		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37319		return __ret;
37320		}
37321		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_f32(float32x2_t __p0) {
37322		bfloat16x4_t __ret;
37323		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37324		return __ret;
37325		}
37326		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_f16(float16x4_t __p0) {
37327		bfloat16x4_t __ret;
37328		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37329		return __ret;
37330		}
37331		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s32(int32x2_t __p0) {
37332		bfloat16x4_t __ret;
37333		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37334		return __ret;
37335		}
37336		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s64(int64x1_t __p0) {
37337		bfloat16x4_t __ret;
37338		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37339		return __ret;
37340		}
37341		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s16(int16x4_t __p0) {
37342		bfloat16x4_t __ret;
37343		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
37344		return __ret;
37345		}
37346	37086	#ifdef __LITTLE_ENDIAN__
37347	37087	#define vqdmulhq_lane_s32(__p0_214, __p1_214, __p2_214) __extension__ ({ \
37348	37088	int32x4_t __ret_214; \
...	...	@@ -38831,6 +38571,266 @@ __ai __attribute__((target("neon"))) int16x4_t vreinterpret_s16_s64(int64x1_t __
38831	38571	__ret = __builtin_bit_cast(int16x4_t, __p0);
38832	38572	return __ret;
38833	38573	}
	38574	__ai __attribute__((target("neon"))) poly8x8_t vreinterpret_p8_bf16(bfloat16x4_t __p0) {
	38575	poly8x8_t __ret;
	38576	__ret = __builtin_bit_cast(poly8x8_t, __p0);
	38577	return __ret;
	38578	}
	38579	__ai __attribute__((target("neon"))) poly64x1_t vreinterpret_p64_bf16(bfloat16x4_t __p0) {
	38580	poly64x1_t __ret;
	38581	__ret = __builtin_bit_cast(poly64x1_t, __p0);
	38582	return __ret;
	38583	}
	38584	__ai __attribute__((target("neon"))) poly16x4_t vreinterpret_p16_bf16(bfloat16x4_t __p0) {
	38585	poly16x4_t __ret;
	38586	__ret = __builtin_bit_cast(poly16x4_t, __p0);
	38587	return __ret;
	38588	}
	38589	__ai __attribute__((target("neon"))) poly8x16_t vreinterpretq_p8_bf16(bfloat16x8_t __p0) {
	38590	poly8x16_t __ret;
	38591	__ret = __builtin_bit_cast(poly8x16_t, __p0);
	38592	return __ret;
	38593	}
	38594	__ai __attribute__((target("neon"))) poly64x2_t vreinterpretq_p64_bf16(bfloat16x8_t __p0) {
	38595	poly64x2_t __ret;
	38596	__ret = __builtin_bit_cast(poly64x2_t, __p0);
	38597	return __ret;
	38598	}
	38599	__ai __attribute__((target("neon"))) poly16x8_t vreinterpretq_p16_bf16(bfloat16x8_t __p0) {
	38600	poly16x8_t __ret;
	38601	__ret = __builtin_bit_cast(poly16x8_t, __p0);
	38602	return __ret;
	38603	}
	38604	__ai __attribute__((target("neon"))) uint8x16_t vreinterpretq_u8_bf16(bfloat16x8_t __p0) {
	38605	uint8x16_t __ret;
	38606	__ret = __builtin_bit_cast(uint8x16_t, __p0);
	38607	return __ret;
	38608	}
	38609	__ai __attribute__((target("neon"))) uint32x4_t vreinterpretq_u32_bf16(bfloat16x8_t __p0) {
	38610	uint32x4_t __ret;
	38611	__ret = __builtin_bit_cast(uint32x4_t, __p0);
	38612	return __ret;
	38613	}
	38614	__ai __attribute__((target("neon"))) uint64x2_t vreinterpretq_u64_bf16(bfloat16x8_t __p0) {
	38615	uint64x2_t __ret;
	38616	__ret = __builtin_bit_cast(uint64x2_t, __p0);
	38617	return __ret;
	38618	}
	38619	__ai __attribute__((target("neon"))) uint16x8_t vreinterpretq_u16_bf16(bfloat16x8_t __p0) {
	38620	uint16x8_t __ret;
	38621	__ret = __builtin_bit_cast(uint16x8_t, __p0);
	38622	return __ret;
	38623	}
	38624	__ai __attribute__((target("neon"))) int8x16_t vreinterpretq_s8_bf16(bfloat16x8_t __p0) {
	38625	int8x16_t __ret;
	38626	__ret = __builtin_bit_cast(int8x16_t, __p0);
	38627	return __ret;
	38628	}
	38629	__ai __attribute__((target("neon"))) float32x4_t vreinterpretq_f32_bf16(bfloat16x8_t __p0) {
	38630	float32x4_t __ret;
	38631	__ret = __builtin_bit_cast(float32x4_t, __p0);
	38632	return __ret;
	38633	}
	38634	__ai __attribute__((target("neon"))) float16x8_t vreinterpretq_f16_bf16(bfloat16x8_t __p0) {
	38635	float16x8_t __ret;
	38636	__ret = __builtin_bit_cast(float16x8_t, __p0);
	38637	return __ret;
	38638	}
	38639	__ai __attribute__((target("neon"))) int32x4_t vreinterpretq_s32_bf16(bfloat16x8_t __p0) {
	38640	int32x4_t __ret;
	38641	__ret = __builtin_bit_cast(int32x4_t, __p0);
	38642	return __ret;
	38643	}
	38644	__ai __attribute__((target("neon"))) int64x2_t vreinterpretq_s64_bf16(bfloat16x8_t __p0) {
	38645	int64x2_t __ret;
	38646	__ret = __builtin_bit_cast(int64x2_t, __p0);
	38647	return __ret;
	38648	}
	38649	__ai __attribute__((target("neon"))) int16x8_t vreinterpretq_s16_bf16(bfloat16x8_t __p0) {
	38650	int16x8_t __ret;
	38651	__ret = __builtin_bit_cast(int16x8_t, __p0);
	38652	return __ret;
	38653	}
	38654	__ai __attribute__((target("neon"))) uint8x8_t vreinterpret_u8_bf16(bfloat16x4_t __p0) {
	38655	uint8x8_t __ret;
	38656	__ret = __builtin_bit_cast(uint8x8_t, __p0);
	38657	return __ret;
	38658	}
	38659	__ai __attribute__((target("neon"))) uint32x2_t vreinterpret_u32_bf16(bfloat16x4_t __p0) {
	38660	uint32x2_t __ret;
	38661	__ret = __builtin_bit_cast(uint32x2_t, __p0);
	38662	return __ret;
	38663	}
	38664	__ai __attribute__((target("neon"))) uint64x1_t vreinterpret_u64_bf16(bfloat16x4_t __p0) {
	38665	uint64x1_t __ret;
	38666	__ret = __builtin_bit_cast(uint64x1_t, __p0);
	38667	return __ret;
	38668	}
	38669	__ai __attribute__((target("neon"))) uint16x4_t vreinterpret_u16_bf16(bfloat16x4_t __p0) {
	38670	uint16x4_t __ret;
	38671	__ret = __builtin_bit_cast(uint16x4_t, __p0);
	38672	return __ret;
	38673	}
	38674	__ai __attribute__((target("neon"))) int8x8_t vreinterpret_s8_bf16(bfloat16x4_t __p0) {
	38675	int8x8_t __ret;
	38676	__ret = __builtin_bit_cast(int8x8_t, __p0);
	38677	return __ret;
	38678	}
	38679	__ai __attribute__((target("neon"))) float32x2_t vreinterpret_f32_bf16(bfloat16x4_t __p0) {
	38680	float32x2_t __ret;
	38681	__ret = __builtin_bit_cast(float32x2_t, __p0);
	38682	return __ret;
	38683	}
	38684	__ai __attribute__((target("neon"))) float16x4_t vreinterpret_f16_bf16(bfloat16x4_t __p0) {
	38685	float16x4_t __ret;
	38686	__ret = __builtin_bit_cast(float16x4_t, __p0);
	38687	return __ret;
	38688	}
	38689	__ai __attribute__((target("neon"))) int32x2_t vreinterpret_s32_bf16(bfloat16x4_t __p0) {
	38690	int32x2_t __ret;
	38691	__ret = __builtin_bit_cast(int32x2_t, __p0);
	38692	return __ret;
	38693	}
	38694	__ai __attribute__((target("neon"))) int64x1_t vreinterpret_s64_bf16(bfloat16x4_t __p0) {
	38695	int64x1_t __ret;
	38696	__ret = __builtin_bit_cast(int64x1_t, __p0);
	38697	return __ret;
	38698	}
	38699	__ai __attribute__((target("neon"))) int16x4_t vreinterpret_s16_bf16(bfloat16x4_t __p0) {
	38700	int16x4_t __ret;
	38701	__ret = __builtin_bit_cast(int16x4_t, __p0);
	38702	return __ret;
	38703	}
	38704	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p8(poly8x16_t __p0) {
	38705	bfloat16x8_t __ret;
	38706	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38707	return __ret;
	38708	}
	38709	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p64(poly64x2_t __p0) {
	38710	bfloat16x8_t __ret;
	38711	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38712	return __ret;
	38713	}
	38714	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p16(poly16x8_t __p0) {
	38715	bfloat16x8_t __ret;
	38716	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38717	return __ret;
	38718	}
	38719	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u8(uint8x16_t __p0) {
	38720	bfloat16x8_t __ret;
	38721	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38722	return __ret;
	38723	}
	38724	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u32(uint32x4_t __p0) {
	38725	bfloat16x8_t __ret;
	38726	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38727	return __ret;
	38728	}
	38729	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u64(uint64x2_t __p0) {
	38730	bfloat16x8_t __ret;
	38731	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38732	return __ret;
	38733	}
	38734	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u16(uint16x8_t __p0) {
	38735	bfloat16x8_t __ret;
	38736	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38737	return __ret;
	38738	}
	38739	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s8(int8x16_t __p0) {
	38740	bfloat16x8_t __ret;
	38741	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38742	return __ret;
	38743	}
	38744	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_f32(float32x4_t __p0) {
	38745	bfloat16x8_t __ret;
	38746	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38747	return __ret;
	38748	}
	38749	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_f16(float16x8_t __p0) {
	38750	bfloat16x8_t __ret;
	38751	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38752	return __ret;
	38753	}
	38754	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s32(int32x4_t __p0) {
	38755	bfloat16x8_t __ret;
	38756	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38757	return __ret;
	38758	}
	38759	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s64(int64x2_t __p0) {
	38760	bfloat16x8_t __ret;
	38761	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38762	return __ret;
	38763	}
	38764	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s16(int16x8_t __p0) {
	38765	bfloat16x8_t __ret;
	38766	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	38767	return __ret;
	38768	}
	38769	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_p8(poly8x8_t __p0) {
	38770	bfloat16x4_t __ret;
	38771	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38772	return __ret;
	38773	}
	38774	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_p64(poly64x1_t __p0) {
	38775	bfloat16x4_t __ret;
	38776	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38777	return __ret;
	38778	}
	38779	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_p16(poly16x4_t __p0) {
	38780	bfloat16x4_t __ret;
	38781	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38782	return __ret;
	38783	}
	38784	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u8(uint8x8_t __p0) {
	38785	bfloat16x4_t __ret;
	38786	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38787	return __ret;
	38788	}
	38789	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u32(uint32x2_t __p0) {
	38790	bfloat16x4_t __ret;
	38791	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38792	return __ret;
	38793	}
	38794	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u64(uint64x1_t __p0) {
	38795	bfloat16x4_t __ret;
	38796	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38797	return __ret;
	38798	}
	38799	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u16(uint16x4_t __p0) {
	38800	bfloat16x4_t __ret;
	38801	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38802	return __ret;
	38803	}
	38804	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s8(int8x8_t __p0) {
	38805	bfloat16x4_t __ret;
	38806	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38807	return __ret;
	38808	}
	38809	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_f32(float32x2_t __p0) {
	38810	bfloat16x4_t __ret;
	38811	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38812	return __ret;
	38813	}
	38814	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_f16(float16x4_t __p0) {
	38815	bfloat16x4_t __ret;
	38816	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38817	return __ret;
	38818	}
	38819	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s32(int32x2_t __p0) {
	38820	bfloat16x4_t __ret;
	38821	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38822	return __ret;
	38823	}
	38824	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s64(int64x1_t __p0) {
	38825	bfloat16x4_t __ret;
	38826	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38827	return __ret;
	38828	}
	38829	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s16(int16x4_t __p0) {
	38830	bfloat16x4_t __ret;
	38831	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	38832	return __ret;
	38833	}
38834	38834	#endif
38835	38835	#if (__ARM_FP & 2)
38836	38836	#ifdef __LITTLE_ENDIAN__
...	...	@@ -41141,6 +41141,174 @@ __ai __attribute__((target("neon"))) float32x2_t vfms_f32(float32x2_t __p0, floa
41141	41141
41142	41142	#endif
41143	41143	#if defined(__aarch64__)
	41144	#ifdef __LITTLE_ENDIAN__
	41145	__ai __attribute__((target("f16f32dot,neon"))) float32x4_t vdotq_f32_f16(float32x4_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41146	float32x4_t __ret;
	41147	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vdotq_f32_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	41148	return __ret;
	41149	}
	41150	#else
	41151	__ai __attribute__((target("f16f32dot,neon"))) float32x4_t vdotq_f32_f16(float32x4_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41152	float32x4_t __ret;
	41153	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	41154	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	41155	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	41156	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vdotq_f32_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
	41157	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
	41158	return __ret;
	41159	}
	41160	#endif
	41161
	41162	#ifdef __LITTLE_ENDIAN__
	41163	__ai __attribute__((target("f16f32dot,neon"))) float32x2_t vdot_f32_f16(float32x2_t __p0, float16x4_t __p1, float16x4_t __p2) {
	41164	float32x2_t __ret;
	41165	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vdot_f32_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), __builtin_bit_cast(int8x8_t, __p2), 9));
	41166	return __ret;
	41167	}
	41168	#else
	41169	__ai __attribute__((target("f16f32dot,neon"))) float32x2_t vdot_f32_f16(float32x2_t __p0, float16x4_t __p1, float16x4_t __p2) {
	41170	float32x2_t __ret;
	41171	float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
	41172	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
	41173	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_64_16);
	41174	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vdot_f32_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __builtin_bit_cast(int8x8_t, __rev2), 9));
	41175	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
	41176	return __ret;
	41177	}
	41178	#endif
	41179
	41180	#ifdef __LITTLE_ENDIAN__
	41181	#define vdotq_lane_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41182	float32x4_t __ret; \
	41183	float32x4_t __s0 = __p0; \
	41184	float16x8_t __s1 = __p1; \
	41185	float16x4_t __s2 = __p2; \
	41186	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vdotq_lane_f32_f16(__builtin_bit_cast(int8x16_t, __s0), __builtin_bit_cast(int8x16_t, __s1), __builtin_bit_cast(int8x8_t, __s2), __p3, 41)); \
	41187	__ret; \
	41188	})
	41189	#else
	41190	#define vdotq_lane_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41191	float32x4_t __ret; \
	41192	float32x4_t __s0 = __p0; \
	41193	float16x8_t __s1 = __p1; \
	41194	float16x4_t __s2 = __p2; \
	41195	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_32); \
	41196	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	41197	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, __lane_reverse_64_16); \
	41198	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vdotq_lane_f32_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x8_t, __rev2), __p3, 41)); \
	41199	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32); \
	41200	__ret; \
	41201	})
	41202	#endif
	41203
	41204	#ifdef __LITTLE_ENDIAN__
	41205	#define vdot_lane_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41206	float32x2_t __ret; \
	41207	float32x2_t __s0 = __p0; \
	41208	float16x4_t __s1 = __p1; \
	41209	float16x4_t __s2 = __p2; \
	41210	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vdot_lane_f32_f16(__builtin_bit_cast(int8x8_t, __s0), __builtin_bit_cast(int8x8_t, __s1), __builtin_bit_cast(int8x8_t, __s2), __p3, 9)); \
	41211	__ret; \
	41212	})
	41213	#else
	41214	#define vdot_lane_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41215	float32x2_t __ret; \
	41216	float32x2_t __s0 = __p0; \
	41217	float16x4_t __s1 = __p1; \
	41218	float16x4_t __s2 = __p2; \
	41219	float32x2_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_32); \
	41220	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	41221	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, __lane_reverse_64_16); \
	41222	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vdot_lane_f32_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __builtin_bit_cast(int8x8_t, __rev2), __p3, 9)); \
	41223	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32); \
	41224	__ret; \
	41225	})
	41226	#endif
	41227
	41228	#ifdef __LITTLE_ENDIAN__
	41229	#define vdotq_laneq_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41230	float32x4_t __ret; \
	41231	float32x4_t __s0 = __p0; \
	41232	float16x8_t __s1 = __p1; \
	41233	float16x8_t __s2 = __p2; \
	41234	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vdotq_laneq_f32_f16(__builtin_bit_cast(int8x16_t, __s0), __builtin_bit_cast(int8x16_t, __s1), __builtin_bit_cast(int8x16_t, __s2), __p3, 41)); \
	41235	__ret; \
	41236	})
	41237	#else
	41238	#define vdotq_laneq_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41239	float32x4_t __ret; \
	41240	float32x4_t __s0 = __p0; \
	41241	float16x8_t __s1 = __p1; \
	41242	float16x8_t __s2 = __p2; \
	41243	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_32); \
	41244	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	41245	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, __lane_reverse_128_16); \
	41246	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vdotq_laneq_f32_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), __p3, 41)); \
	41247	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32); \
	41248	__ret; \
	41249	})
	41250	#endif
	41251
	41252	#ifdef __LITTLE_ENDIAN__
	41253	#define vdot_laneq_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41254	float32x2_t __ret; \
	41255	float32x2_t __s0 = __p0; \
	41256	float16x4_t __s1 = __p1; \
	41257	float16x8_t __s2 = __p2; \
	41258	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vdot_laneq_f32_f16(__builtin_bit_cast(int8x8_t, __s0), __builtin_bit_cast(int8x8_t, __s1), __builtin_bit_cast(int8x16_t, __s2), __p3, 9)); \
	41259	__ret; \
	41260	})
	41261	#else
	41262	#define vdot_laneq_f32_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41263	float32x2_t __ret; \
	41264	float32x2_t __s0 = __p0; \
	41265	float16x4_t __s1 = __p1; \
	41266	float16x8_t __s2 = __p2; \
	41267	float32x2_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_32); \
	41268	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	41269	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, __lane_reverse_128_16); \
	41270	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vdot_laneq_f32_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), __p3, 9)); \
	41271	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32); \
	41272	__ret; \
	41273	})
	41274	#endif
	41275
	41276	#ifdef __LITTLE_ENDIAN__
	41277	__ai __attribute__((target("f16f32mm,neon"))) float32x4_t vmmlaq_f32_f16(float32x4_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41278	float32x4_t __ret;
	41279	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vmmlaq_f32_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 41));
	41280	return __ret;
	41281	}
	41282	#else
	41283	__ai __attribute__((target("f16f32mm,neon"))) float32x4_t vmmlaq_f32_f16(float32x4_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41284	float32x4_t __ret;
	41285	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	41286	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	41287	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	41288	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vmmlaq_f32_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 41));
	41289	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
	41290	return __ret;
	41291	}
	41292	#endif
	41293
	41294	#ifdef __LITTLE_ENDIAN__
	41295	__ai __attribute__((target("f16mm,neon"))) float16x8_t vmmlaq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41296	float16x8_t __ret;
	41297	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmmlaq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), __builtin_bit_cast(int8x16_t, __p2), 40));
	41298	return __ret;
	41299	}
	41300	#else
	41301	__ai __attribute__((target("f16mm,neon"))) float16x8_t vmmlaq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41302	float16x8_t __ret;
	41303	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	41304	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	41305	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, __lane_reverse_128_16);
	41306	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmmlaq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __builtin_bit_cast(int8x16_t, __rev2), 40));
	41307	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
	41308	return __ret;
	41309	}
	41310	#endif
	41311
41144	41312	#ifdef __LITTLE_ENDIAN__
41145	41313	__ai __attribute__((target("f8f16mm,neon"))) float16x8_t vmmlaq_f16_mf8_fpm(float16x8_t __p0, mfloat8x16_t __p1, mfloat8x16_t __p2, fpm_t __p3) {
41146	41314	float16x8_t __ret;
...	...	@@ -42391,6 +42559,48 @@ __ai __attribute__((target("fp8fma,neon"))) float16x8_t vmlaltq_f16_mf8_fpm(floa
42391	42559	})
42392	42560	#endif
42393	42561
	42562	#ifdef __LITTLE_ENDIAN__
	42563	#define vluti2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	42564	bfloat16x8_t __ret; \
	42565	bfloat16x8_t __s0 = __p0; \
	42566	uint8x8_t __s1 = __p1; \
	42567	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_lane_bf16(__builtin_bit_cast(int8x16_t, __s0), __builtin_bit_cast(int8x8_t, __s1), __p2, 43)); \
	42568	__ret; \
	42569	})
	42570	#else
	42571	#define vluti2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	42572	bfloat16x8_t __ret; \
	42573	bfloat16x8_t __s0 = __p0; \
	42574	uint8x8_t __s1 = __p1; \
	42575	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	42576	uint8x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_8); \
	42577	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_lane_bf16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __p2, 43)); \
	42578	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	42579	__ret; \
	42580	})
	42581	#endif
	42582
	42583	#ifdef __LITTLE_ENDIAN__
	42584	#define vluti2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	42585	bfloat16x8_t __ret; \
	42586	bfloat16x4_t __s0 = __p0; \
	42587	uint8x8_t __s1 = __p1; \
	42588	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_lane_bf16(__builtin_bit_cast(int8x8_t, __s0), __builtin_bit_cast(int8x8_t, __s1), __p2, 43)); \
	42589	__ret; \
	42590	})
	42591	#else
	42592	#define vluti2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
	42593	bfloat16x8_t __ret; \
	42594	bfloat16x4_t __s0 = __p0; \
	42595	uint8x8_t __s1 = __p1; \
	42596	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	42597	uint8x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_8); \
	42598	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_lane_bf16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __p2, 43)); \
	42599	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	42600	__ret; \
	42601	})
	42602	#endif
	42603
42394	42604	#ifdef __LITTLE_ENDIAN__
42395	42605	#define vluti2_lane_p16(__p0, __p1, __p2) __extension__ ({ \
42396	42606	poly16x8_t __ret; \
...	...	@@ -42559,6 +42769,48 @@ __ai __attribute__((target("fp8fma,neon"))) float16x8_t vmlaltq_f16_mf8_fpm(floa
42559	42769	})
42560	42770	#endif
42561	42771
	42772	#ifdef __LITTLE_ENDIAN__
	42773	#define vluti2q_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
	42774	bfloat16x8_t __ret; \
	42775	bfloat16x8_t __s0 = __p0; \
	42776	uint8x16_t __s1 = __p1; \
	42777	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_laneq_bf16(__builtin_bit_cast(int8x16_t, __s0), __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
	42778	__ret; \
	42779	})
	42780	#else
	42781	#define vluti2q_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
	42782	bfloat16x8_t __ret; \
	42783	bfloat16x8_t __s0 = __p0; \
	42784	uint8x16_t __s1 = __p1; \
	42785	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	42786	uint8x16_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_8); \
	42787	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_laneq_bf16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
	42788	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	42789	__ret; \
	42790	})
	42791	#endif
	42792
	42793	#ifdef __LITTLE_ENDIAN__
	42794	#define vluti2_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
	42795	bfloat16x8_t __ret; \
	42796	bfloat16x4_t __s0 = __p0; \
	42797	uint8x16_t __s1 = __p1; \
	42798	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_laneq_bf16(__builtin_bit_cast(int8x8_t, __s0), __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
	42799	__ret; \
	42800	})
	42801	#else
	42802	#define vluti2_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
	42803	bfloat16x8_t __ret; \
	42804	bfloat16x4_t __s0 = __p0; \
	42805	uint8x16_t __s1 = __p1; \
	42806	bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	42807	uint8x16_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_8); \
	42808	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_laneq_bf16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
	42809	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	42810	__ret; \
	42811	})
	42812	#endif
	42813
42562	42814	#ifdef __LITTLE_ENDIAN__
42563	42815	#define vluti2_laneq_p8(__p0, __p1, __p2) __extension__ ({ \
42564	42816	poly8x16_t __ret; \
...	...	@@ -42979,6 +43231,29 @@ __ai __attribute__((target("fp8fma,neon"))) float16x8_t vmlaltq_f16_mf8_fpm(floa
42979	43231	})
42980	43232	#endif
42981	43233
	43234	#ifdef __LITTLE_ENDIAN__
	43235	#define vluti4q_lane_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
	43236	bfloat16x8_t __ret; \
	43237	bfloat16x8x2_t __s0 = __p0; \
	43238	uint8x8_t __s1 = __p1; \
	43239	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_lane_bf16_x2(__builtin_bit_cast(int8x16_t, __s0.val[0]), __builtin_bit_cast(int8x16_t, __s0.val[1]), __builtin_bit_cast(int8x8_t, __s1), __p2, 43)); \
	43240	__ret; \
	43241	})
	43242	#else
	43243	#define vluti4q_lane_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
	43244	bfloat16x8_t __ret; \
	43245	bfloat16x8x2_t __s0 = __p0; \
	43246	uint8x8_t __s1 = __p1; \
	43247	bfloat16x8x2_t __rev0; \
	43248	__rev0.val[0] = __builtin_shufflevector(__s0.val[0], __s0.val[0], __lane_reverse_128_16); \
	43249	__rev0.val[1] = __builtin_shufflevector(__s0.val[1], __s0.val[1], __lane_reverse_128_16); \
	43250	uint8x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_8); \
	43251	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_lane_bf16_x2(__builtin_bit_cast(int8x16_t, __rev0.val[0]), __builtin_bit_cast(int8x16_t, __rev0.val[1]), __builtin_bit_cast(int8x8_t, __rev1), __p2, 43)); \
	43252	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	43253	__ret; \
	43254	})
	43255	#endif
	43256
42982	43257	#ifdef __LITTLE_ENDIAN__
42983	43258	#define vluti4q_lane_p16_x2(__p0, __p1, __p2) __extension__ ({ \
42984	43259	poly16x8_t __ret; \
...	...	@@ -43155,6 +43430,29 @@ __ai __attribute__((target("fp8fma,neon"))) float16x8_t vmlaltq_f16_mf8_fpm(floa
43155	43430	})
43156	43431	#endif
43157	43432
	43433	#ifdef __LITTLE_ENDIAN__
	43434	#define vluti4q_laneq_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
	43435	bfloat16x8_t __ret; \
	43436	bfloat16x8x2_t __s0 = __p0; \
	43437	uint8x16_t __s1 = __p1; \
	43438	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_laneq_bf16_x2(__builtin_bit_cast(int8x16_t, __s0.val[0]), __builtin_bit_cast(int8x16_t, __s0.val[1]), __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
	43439	__ret; \
	43440	})
	43441	#else
	43442	#define vluti4q_laneq_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
	43443	bfloat16x8_t __ret; \
	43444	bfloat16x8x2_t __s0 = __p0; \
	43445	uint8x16_t __s1 = __p1; \
	43446	bfloat16x8x2_t __rev0; \
	43447	__rev0.val[0] = __builtin_shufflevector(__s0.val[0], __s0.val[0], __lane_reverse_128_16); \
	43448	__rev0.val[1] = __builtin_shufflevector(__s0.val[1], __s0.val[1], __lane_reverse_128_16); \
	43449	uint8x16_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_8); \
	43450	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_laneq_bf16_x2(__builtin_bit_cast(int8x16_t, __rev0.val[0]), __builtin_bit_cast(int8x16_t, __rev0.val[1]), __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
	43451	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	43452	__ret; \
	43453	})
	43454	#endif
	43455
43158	43456	#ifdef __LITTLE_ENDIAN__
43159	43457	#define vluti4q_laneq_p16_x2(__p0, __p1, __p2) __extension__ ({ \
43160	43458	poly16x8_t __ret; \
...	...	@@ -43247,136 +43545,6 @@ __ai __attribute__((target("fp8fma,neon"))) float16x8_t vmlaltq_f16_mf8_fpm(floa
43247	43545	})
43248	43546	#endif
43249	43547
43250		#ifdef __LITTLE_ENDIAN__
43251		#define vluti2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
43252		bfloat16x8_t __ret; \
43253		bfloat16x8_t __s0 = __p0; \
43254		uint8x8_t __s1 = __p1; \
43255		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_lane_bf16(__builtin_bit_cast(int8x16_t, __s0), __builtin_bit_cast(int8x8_t, __s1), __p2, 43)); \
43256		__ret; \
43257		})
43258		#else
43259		#define vluti2q_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
43260		bfloat16x8_t __ret; \
43261		bfloat16x8_t __s0 = __p0; \
43262		uint8x8_t __s1 = __p1; \
43263		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
43264		uint8x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_8); \
43265		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_lane_bf16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __p2, 43)); \
43266		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
43267		__ret; \
43268		})
43269		#endif
43270
43271		#ifdef __LITTLE_ENDIAN__
43272		#define vluti2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
43273		bfloat16x8_t __ret; \
43274		bfloat16x4_t __s0 = __p0; \
43275		uint8x8_t __s1 = __p1; \
43276		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_lane_bf16(__builtin_bit_cast(int8x8_t, __s0), __builtin_bit_cast(int8x8_t, __s1), __p2, 43)); \
43277		__ret; \
43278		})
43279		#else
43280		#define vluti2_lane_bf16(__p0, __p1, __p2) __extension__ ({ \
43281		bfloat16x8_t __ret; \
43282		bfloat16x4_t __s0 = __p0; \
43283		uint8x8_t __s1 = __p1; \
43284		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
43285		uint8x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_8); \
43286		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_lane_bf16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), __p2, 43)); \
43287		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
43288		__ret; \
43289		})
43290		#endif
43291
43292		#ifdef __LITTLE_ENDIAN__
43293		#define vluti2q_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
43294		bfloat16x8_t __ret; \
43295		bfloat16x8_t __s0 = __p0; \
43296		uint8x16_t __s1 = __p1; \
43297		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_laneq_bf16(__builtin_bit_cast(int8x16_t, __s0), __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
43298		__ret; \
43299		})
43300		#else
43301		#define vluti2q_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
43302		bfloat16x8_t __ret; \
43303		bfloat16x8_t __s0 = __p0; \
43304		uint8x16_t __s1 = __p1; \
43305		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
43306		uint8x16_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_8); \
43307		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2q_laneq_bf16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
43308		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
43309		__ret; \
43310		})
43311		#endif
43312
43313		#ifdef __LITTLE_ENDIAN__
43314		#define vluti2_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
43315		bfloat16x8_t __ret; \
43316		bfloat16x4_t __s0 = __p0; \
43317		uint8x16_t __s1 = __p1; \
43318		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_laneq_bf16(__builtin_bit_cast(int8x8_t, __s0), __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
43319		__ret; \
43320		})
43321		#else
43322		#define vluti2_laneq_bf16(__p0, __p1, __p2) __extension__ ({ \
43323		bfloat16x8_t __ret; \
43324		bfloat16x4_t __s0 = __p0; \
43325		uint8x16_t __s1 = __p1; \
43326		bfloat16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
43327		uint8x16_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_8); \
43328		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti2_laneq_bf16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
43329		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
43330		__ret; \
43331		})
43332		#endif
43333
43334		#ifdef __LITTLE_ENDIAN__
43335		#define vluti4q_lane_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
43336		bfloat16x8_t __ret; \
43337		bfloat16x8x2_t __s0 = __p0; \
43338		uint8x8_t __s1 = __p1; \
43339		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_lane_bf16_x2(__builtin_bit_cast(int8x16_t, __s0.val[0]), __builtin_bit_cast(int8x16_t, __s0.val[1]), __builtin_bit_cast(int8x8_t, __s1), __p2, 43)); \
43340		__ret; \
43341		})
43342		#else
43343		#define vluti4q_lane_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
43344		bfloat16x8_t __ret; \
43345		bfloat16x8x2_t __s0 = __p0; \
43346		uint8x8_t __s1 = __p1; \
43347		bfloat16x8x2_t __rev0; \
43348		__rev0.val[0] = __builtin_shufflevector(__s0.val[0], __s0.val[0], __lane_reverse_128_16); \
43349		__rev0.val[1] = __builtin_shufflevector(__s0.val[1], __s0.val[1], __lane_reverse_128_16); \
43350		uint8x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_8); \
43351		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_lane_bf16_x2(__builtin_bit_cast(int8x16_t, __rev0.val[0]), __builtin_bit_cast(int8x16_t, __rev0.val[1]), __builtin_bit_cast(int8x8_t, __rev1), __p2, 43)); \
43352		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
43353		__ret; \
43354		})
43355		#endif
43356
43357		#ifdef __LITTLE_ENDIAN__
43358		#define vluti4q_laneq_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
43359		bfloat16x8_t __ret; \
43360		bfloat16x8x2_t __s0 = __p0; \
43361		uint8x16_t __s1 = __p1; \
43362		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_laneq_bf16_x2(__builtin_bit_cast(int8x16_t, __s0.val[0]), __builtin_bit_cast(int8x16_t, __s0.val[1]), __builtin_bit_cast(int8x16_t, __s1), __p2, 43)); \
43363		__ret; \
43364		})
43365		#else
43366		#define vluti4q_laneq_bf16_x2(__p0, __p1, __p2) __extension__ ({ \
43367		bfloat16x8_t __ret; \
43368		bfloat16x8x2_t __s0 = __p0; \
43369		uint8x16_t __s1 = __p1; \
43370		bfloat16x8x2_t __rev0; \
43371		__rev0.val[0] = __builtin_shufflevector(__s0.val[0], __s0.val[0], __lane_reverse_128_16); \
43372		__rev0.val[1] = __builtin_shufflevector(__s0.val[1], __s0.val[1], __lane_reverse_128_16); \
43373		uint8x16_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_8); \
43374		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vluti4q_laneq_bf16_x2(__builtin_bit_cast(int8x16_t, __rev0.val[0]), __builtin_bit_cast(int8x16_t, __rev0.val[1]), __builtin_bit_cast(int8x16_t, __rev1), __p2, 43)); \
43375		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
43376		__ret; \
43377		})
43378		#endif
43379
43380	43548	#ifdef __LITTLE_ENDIAN__
43381	43549	#define splatq_lane_mf8(__p0, __p1) __extension__ ({ \
43382	43550	mfloat8x16_t __ret; \
...	...	@@ -44171,698 +44339,324 @@ __ai __attribute__((target("neon"))) mfloat8x8x2_t vzip_mf8(mfloat8x8_t __p0, mf
44171	44339	#endif
44172	44340
44173	44341	#ifdef __LITTLE_ENDIAN__
44174		__ai __attribute__((target("neon,faminmax"))) float64x2_t vamaxq_f64(float64x2_t __p0, float64x2_t __p1) {
44175		float64x2_t __ret;
44176		__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vamaxq_f64(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 42));
44177		return __ret;
44178		}
44179		#else
44180		__ai __attribute__((target("neon,faminmax"))) float64x2_t vamaxq_f64(float64x2_t __p0, float64x2_t __p1) {
44181		float64x2_t __ret;
44182		float64x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_64);
44183		float64x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_64);
44184		__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vamaxq_f64(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 42));
44185		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_64);
44186		return __ret;
44187		}
44188		#endif
44189
44190		#ifdef __LITTLE_ENDIAN__
44191		__ai __attribute__((target("neon,faminmax"))) float32x4_t vamaxq_f32(float32x4_t __p0, float32x4_t __p1) {
44192		float32x4_t __ret;
44193		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vamaxq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 41));
44194		return __ret;
44195		}
44196		#else
44197		__ai __attribute__((target("neon,faminmax"))) float32x4_t vamaxq_f32(float32x4_t __p0, float32x4_t __p1) {
44198		float32x4_t __ret;
44199		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
44200		float32x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_32);
44201		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vamaxq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 41));
44202		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
44203		return __ret;
44204		}
44205		#endif
44206
44207		#ifdef __LITTLE_ENDIAN__
44208		__ai __attribute__((target("neon,faminmax"))) float16x8_t vamaxq_f16(float16x8_t __p0, float16x8_t __p1) {
44209		float16x8_t __ret;
44210		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vamaxq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
44211		return __ret;
44212		}
44213		#else
44214		__ai __attribute__((target("neon,faminmax"))) float16x8_t vamaxq_f16(float16x8_t __p0, float16x8_t __p1) {
44215		float16x8_t __ret;
44216		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
44217		float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
44218		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vamaxq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 40));
44219		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44220		return __ret;
44221		}
44222		#endif
44223
44224		#ifdef __LITTLE_ENDIAN__
44225		__ai __attribute__((target("neon,faminmax"))) float32x2_t vamax_f32(float32x2_t __p0, float32x2_t __p1) {
44226		float32x2_t __ret;
44227		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamax_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 9));
44228		return __ret;
44229		}
44230		#else
44231		__ai __attribute__((target("neon,faminmax"))) float32x2_t vamax_f32(float32x2_t __p0, float32x2_t __p1) {
44232		float32x2_t __ret;
44233		float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
44234		float32x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_32);
44235		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamax_f32(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 9));
44236		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
44237		return __ret;
44238		}
44239		#endif
44240
44241		#ifdef __LITTLE_ENDIAN__
44242		__ai __attribute__((target("neon,faminmax"))) float16x4_t vamax_f16(float16x4_t __p0, float16x4_t __p1) {
44243		float16x4_t __ret;
44244		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamax_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
44245		return __ret;
44246		}
44247		#else
44248		__ai __attribute__((target("neon,faminmax"))) float16x4_t vamax_f16(float16x4_t __p0, float16x4_t __p1) {
44249		float16x4_t __ret;
44250		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
44251		float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
44252		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamax_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 8));
44253		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
44254		return __ret;
44255		}
44256		#endif
44257
44258		#ifdef __LITTLE_ENDIAN__
44259		__ai __attribute__((target("neon,faminmax"))) float64x2_t vaminq_f64(float64x2_t __p0, float64x2_t __p1) {
44260		float64x2_t __ret;
44261		__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vaminq_f64(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 42));
44262		return __ret;
44263		}
44264		#else
44265		__ai __attribute__((target("neon,faminmax"))) float64x2_t vaminq_f64(float64x2_t __p0, float64x2_t __p1) {
44266		float64x2_t __ret;
44267		float64x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_64);
44268		float64x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_64);
44269		__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vaminq_f64(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 42));
44270		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_64);
44271		return __ret;
44272		}
44273		#endif
44274
44275		#ifdef __LITTLE_ENDIAN__
44276		__ai __attribute__((target("neon,faminmax"))) float32x4_t vaminq_f32(float32x4_t __p0, float32x4_t __p1) {
44277		float32x4_t __ret;
44278		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vaminq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 41));
44279		return __ret;
44280		}
44281		#else
44282		__ai __attribute__((target("neon,faminmax"))) float32x4_t vaminq_f32(float32x4_t __p0, float32x4_t __p1) {
44283		float32x4_t __ret;
44284		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
44285		float32x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_32);
44286		__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vaminq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 41));
44287		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
44288		return __ret;
44289		}
44290		#endif
44291
44292		#ifdef __LITTLE_ENDIAN__
44293		__ai __attribute__((target("neon,faminmax"))) float16x8_t vaminq_f16(float16x8_t __p0, float16x8_t __p1) {
44294		float16x8_t __ret;
44295		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vaminq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
44296		return __ret;
44297		}
44298		#else
44299		__ai __attribute__((target("neon,faminmax"))) float16x8_t vaminq_f16(float16x8_t __p0, float16x8_t __p1) {
44300		float16x8_t __ret;
44301		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
44302		float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
44303		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vaminq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 40));
44304		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44305		return __ret;
44306		}
44307		#endif
44308
44309		#ifdef __LITTLE_ENDIAN__
44310		__ai __attribute__((target("neon,faminmax"))) float32x2_t vamin_f32(float32x2_t __p0, float32x2_t __p1) {
44311		float32x2_t __ret;
44312		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamin_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 9));
44313		return __ret;
44314		}
44315		#else
44316		__ai __attribute__((target("neon,faminmax"))) float32x2_t vamin_f32(float32x2_t __p0, float32x2_t __p1) {
44317		float32x2_t __ret;
44318		float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
44319		float32x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_32);
44320		__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamin_f32(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 9));
44321		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
44322		return __ret;
44323		}
44324		#endif
44325
44326		#ifdef __LITTLE_ENDIAN__
44327		__ai __attribute__((target("neon,faminmax"))) float16x4_t vamin_f16(float16x4_t __p0, float16x4_t __p1) {
44328		float16x4_t __ret;
44329		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamin_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
44330		return __ret;
44331		}
44332		#else
44333		__ai __attribute__((target("neon,faminmax"))) float16x4_t vamin_f16(float16x4_t __p0, float16x4_t __p1) {
44334		float16x4_t __ret;
44335		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
44336		float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
44337		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamin_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 8));
44338		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
44339		return __ret;
44340		}
44341		#endif
44342
44343		#endif
44344		#if defined(__aarch64__) \|\| defined(__arm64ec__)
44345		__ai __attribute__((target("aes,neon"))) poly128_t vmull_p64(poly64_t __p0, poly64_t __p1) {
44346		poly128_t __ret;
44347		__ret = __builtin_bit_cast(poly128_t, __builtin_neon_vmull_p64(__p0, __p1));
44348		return __ret;
44349		}
44350		#ifdef __LITTLE_ENDIAN__
44351		#define vcopyq_lane_bf16(__p0_234, __p1_234, __p2_234, __p3_234) __extension__ ({ \
44352		bfloat16x8_t __ret_234; \
44353		bfloat16x8_t __s0_234 = __p0_234; \
44354		bfloat16x4_t __s2_234 = __p2_234; \
44355		__ret_234 = vsetq_lane_bf16(vget_lane_bf16(__s2_234, __p3_234), __s0_234, __p1_234); \
44356		__ret_234; \
44357		})
44358		#else
44359		#define vcopyq_lane_bf16(__p0_235, __p1_235, __p2_235, __p3_235) __extension__ ({ \
44360		bfloat16x8_t __ret_235; \
44361		bfloat16x8_t __s0_235 = __p0_235; \
44362		bfloat16x4_t __s2_235 = __p2_235; \
44363		bfloat16x8_t __rev0_235; __rev0_235 = __builtin_shufflevector(__s0_235, __s0_235, __lane_reverse_128_16); \
44364		bfloat16x4_t __rev2_235; __rev2_235 = __builtin_shufflevector(__s2_235, __s2_235, __lane_reverse_64_16); \
44365		__ret_235 = __noswap_vsetq_lane_bf16(__noswap_vget_lane_bf16(__rev2_235, __p3_235), __rev0_235, __p1_235); \
44366		__ret_235 = __builtin_shufflevector(__ret_235, __ret_235, __lane_reverse_128_16); \
44367		__ret_235; \
44368		})
44369		#endif
44370
44371		#ifdef __LITTLE_ENDIAN__
44372		#define vcopy_lane_bf16(__p0_236, __p1_236, __p2_236, __p3_236) __extension__ ({ \
44373		bfloat16x4_t __ret_236; \
44374		bfloat16x4_t __s0_236 = __p0_236; \
44375		bfloat16x4_t __s2_236 = __p2_236; \
44376		__ret_236 = vset_lane_bf16(vget_lane_bf16(__s2_236, __p3_236), __s0_236, __p1_236); \
44377		__ret_236; \
44378		})
44379		#else
44380		#define vcopy_lane_bf16(__p0_237, __p1_237, __p2_237, __p3_237) __extension__ ({ \
44381		bfloat16x4_t __ret_237; \
44382		bfloat16x4_t __s0_237 = __p0_237; \
44383		bfloat16x4_t __s2_237 = __p2_237; \
44384		bfloat16x4_t __rev0_237; __rev0_237 = __builtin_shufflevector(__s0_237, __s0_237, __lane_reverse_64_16); \
44385		bfloat16x4_t __rev2_237; __rev2_237 = __builtin_shufflevector(__s2_237, __s2_237, __lane_reverse_64_16); \
44386		__ret_237 = __noswap_vset_lane_bf16(__noswap_vget_lane_bf16(__rev2_237, __p3_237), __rev0_237, __p1_237); \
44387		__ret_237 = __builtin_shufflevector(__ret_237, __ret_237, __lane_reverse_64_16); \
44388		__ret_237; \
44389		})
44390		#endif
44391
44392		#ifdef __LITTLE_ENDIAN__
44393		#define vcopyq_laneq_bf16(__p0_238, __p1_238, __p2_238, __p3_238) __extension__ ({ \
44394		bfloat16x8_t __ret_238; \
44395		bfloat16x8_t __s0_238 = __p0_238; \
44396		bfloat16x8_t __s2_238 = __p2_238; \
44397		__ret_238 = vsetq_lane_bf16(vgetq_lane_bf16(__s2_238, __p3_238), __s0_238, __p1_238); \
44398		__ret_238; \
44399		})
44400		#else
44401		#define vcopyq_laneq_bf16(__p0_239, __p1_239, __p2_239, __p3_239) __extension__ ({ \
44402		bfloat16x8_t __ret_239; \
44403		bfloat16x8_t __s0_239 = __p0_239; \
44404		bfloat16x8_t __s2_239 = __p2_239; \
44405		bfloat16x8_t __rev0_239; __rev0_239 = __builtin_shufflevector(__s0_239, __s0_239, __lane_reverse_128_16); \
44406		bfloat16x8_t __rev2_239; __rev2_239 = __builtin_shufflevector(__s2_239, __s2_239, __lane_reverse_128_16); \
44407		__ret_239 = __noswap_vsetq_lane_bf16(__noswap_vgetq_lane_bf16(__rev2_239, __p3_239), __rev0_239, __p1_239); \
44408		__ret_239 = __builtin_shufflevector(__ret_239, __ret_239, __lane_reverse_128_16); \
44409		__ret_239; \
44410		})
44411		#endif
44412
44413		#ifdef __LITTLE_ENDIAN__
44414		#define vcopy_laneq_bf16(__p0_240, __p1_240, __p2_240, __p3_240) __extension__ ({ \
44415		bfloat16x4_t __ret_240; \
44416		bfloat16x4_t __s0_240 = __p0_240; \
44417		bfloat16x8_t __s2_240 = __p2_240; \
44418		__ret_240 = vset_lane_bf16(vgetq_lane_bf16(__s2_240, __p3_240), __s0_240, __p1_240); \
44419		__ret_240; \
44420		})
44421		#else
44422		#define vcopy_laneq_bf16(__p0_241, __p1_241, __p2_241, __p3_241) __extension__ ({ \
44423		bfloat16x4_t __ret_241; \
44424		bfloat16x4_t __s0_241 = __p0_241; \
44425		bfloat16x8_t __s2_241 = __p2_241; \
44426		bfloat16x4_t __rev0_241; __rev0_241 = __builtin_shufflevector(__s0_241, __s0_241, __lane_reverse_64_16); \
44427		bfloat16x8_t __rev2_241; __rev2_241 = __builtin_shufflevector(__s2_241, __s2_241, __lane_reverse_128_16); \
44428		__ret_241 = __noswap_vset_lane_bf16(__noswap_vgetq_lane_bf16(__rev2_241, __p3_241), __rev0_241, __p1_241); \
44429		__ret_241 = __builtin_shufflevector(__ret_241, __ret_241, __lane_reverse_64_16); \
44430		__ret_241; \
44431		})
44432		#endif
44433
44434		#ifdef __LITTLE_ENDIAN__
44435		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vcvt_bf16_f32(float32x4_t __p0) {
44436		bfloat16x4_t __ret;
44437		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vcvt_bf16_f32(__builtin_bit_cast(int8x16_t, __p0), 11));
44438		return __ret;
44439		}
44440		#else
44441		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vcvt_bf16_f32(float32x4_t __p0) {
44442		bfloat16x4_t __ret;
44443		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
44444		__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vcvt_bf16_f32(__builtin_bit_cast(int8x16_t, __rev0), 11));
44445		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
44446		return __ret;
44447		}
44448		#endif
44449
44450		#ifdef __LITTLE_ENDIAN__
44451		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_high_bf16_f32(bfloat16x8_t __p0, float32x4_t __p1) {
44452		bfloat16x8_t __ret;
44453		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_high_bf16_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 43));
44454		return __ret;
44455		}
44456		#else
44457		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_high_bf16_f32(bfloat16x8_t __p0, float32x4_t __p1) {
44458		bfloat16x8_t __ret;
44459		bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
44460		float32x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_32);
44461		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_high_bf16_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 43));
44462		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44463		return __ret;
44464		}
44465		#endif
44466
44467		#ifdef __LITTLE_ENDIAN__
44468		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_low_bf16_f32(float32x4_t __p0) {
44469		bfloat16x8_t __ret;
44470		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_low_bf16_f32(__builtin_bit_cast(int8x16_t, __p0), 43));
44471		return __ret;
44472		}
44473		#else
44474		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_low_bf16_f32(float32x4_t __p0) {
44475		bfloat16x8_t __ret;
44476		float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
44477		__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_low_bf16_f32(__builtin_bit_cast(int8x16_t, __rev0), 43));
44478		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44479		return __ret;
44480		}
44481		#endif
44482
44483		__ai __attribute__((target("bf16,neon"))) poly8x8_t vreinterpret_p8_bf16(bfloat16x4_t __p0) {
44484		poly8x8_t __ret;
44485		__ret = __builtin_bit_cast(poly8x8_t, __p0);
44486		return __ret;
44487		}
44488		__ai __attribute__((target("bf16,neon"))) poly64x1_t vreinterpret_p64_bf16(bfloat16x4_t __p0) {
44489		poly64x1_t __ret;
44490		__ret = __builtin_bit_cast(poly64x1_t, __p0);
44491		return __ret;
44492		}
44493		__ai __attribute__((target("bf16,neon"))) poly16x4_t vreinterpret_p16_bf16(bfloat16x4_t __p0) {
44494		poly16x4_t __ret;
44495		__ret = __builtin_bit_cast(poly16x4_t, __p0);
44496		return __ret;
44497		}
44498		__ai __attribute__((target("bf16,neon"))) poly8x16_t vreinterpretq_p8_bf16(bfloat16x8_t __p0) {
44499		poly8x16_t __ret;
44500		__ret = __builtin_bit_cast(poly8x16_t, __p0);
44501		return __ret;
44502		}
44503		__ai __attribute__((target("bf16,neon"))) poly128_t vreinterpretq_p128_bf16(bfloat16x8_t __p0) {
44504		poly128_t __ret;
44505		__ret = __builtin_bit_cast(poly128_t, __p0);
44506		return __ret;
44507		}
44508		__ai __attribute__((target("bf16,neon"))) poly64x2_t vreinterpretq_p64_bf16(bfloat16x8_t __p0) {
44509		poly64x2_t __ret;
44510		__ret = __builtin_bit_cast(poly64x2_t, __p0);
44511		return __ret;
44512		}
44513		__ai __attribute__((target("bf16,neon"))) poly16x8_t vreinterpretq_p16_bf16(bfloat16x8_t __p0) {
44514		poly16x8_t __ret;
44515		__ret = __builtin_bit_cast(poly16x8_t, __p0);
44516		return __ret;
44517		}
44518		__ai __attribute__((target("bf16,neon"))) uint8x16_t vreinterpretq_u8_bf16(bfloat16x8_t __p0) {
44519		uint8x16_t __ret;
44520		__ret = __builtin_bit_cast(uint8x16_t, __p0);
44521		return __ret;
44522		}
44523		__ai __attribute__((target("bf16,neon"))) uint32x4_t vreinterpretq_u32_bf16(bfloat16x8_t __p0) {
44524		uint32x4_t __ret;
44525		__ret = __builtin_bit_cast(uint32x4_t, __p0);
44526		return __ret;
44527		}
44528		__ai __attribute__((target("bf16,neon"))) uint64x2_t vreinterpretq_u64_bf16(bfloat16x8_t __p0) {
44529		uint64x2_t __ret;
44530		__ret = __builtin_bit_cast(uint64x2_t, __p0);
44531		return __ret;
44532		}
44533		__ai __attribute__((target("bf16,neon"))) uint16x8_t vreinterpretq_u16_bf16(bfloat16x8_t __p0) {
44534		uint16x8_t __ret;
44535		__ret = __builtin_bit_cast(uint16x8_t, __p0);
44536		return __ret;
44537		}
44538		__ai __attribute__((target("bf16,neon"))) int8x16_t vreinterpretq_s8_bf16(bfloat16x8_t __p0) {
44539		int8x16_t __ret;
44540		__ret = __builtin_bit_cast(int8x16_t, __p0);
44541		return __ret;
44542		}
44543		__ai __attribute__((target("bf16,neon"))) float64x2_t vreinterpretq_f64_bf16(bfloat16x8_t __p0) {
44544		float64x2_t __ret;
44545		__ret = __builtin_bit_cast(float64x2_t, __p0);
44546		return __ret;
44547		}
44548		__ai __attribute__((target("bf16,neon"))) float32x4_t vreinterpretq_f32_bf16(bfloat16x8_t __p0) {
44549		float32x4_t __ret;
44550		__ret = __builtin_bit_cast(float32x4_t, __p0);
44551		return __ret;
44552		}
44553		__ai __attribute__((target("bf16,neon"))) float16x8_t vreinterpretq_f16_bf16(bfloat16x8_t __p0) {
44554		float16x8_t __ret;
44555		__ret = __builtin_bit_cast(float16x8_t, __p0);
44556		return __ret;
44557		}
44558		__ai __attribute__((target("bf16,neon"))) int32x4_t vreinterpretq_s32_bf16(bfloat16x8_t __p0) {
44559		int32x4_t __ret;
44560		__ret = __builtin_bit_cast(int32x4_t, __p0);
44561		return __ret;
44562		}
44563		__ai __attribute__((target("bf16,neon"))) int64x2_t vreinterpretq_s64_bf16(bfloat16x8_t __p0) {
44564		int64x2_t __ret;
44565		__ret = __builtin_bit_cast(int64x2_t, __p0);
44566		return __ret;
44567		}
44568		__ai __attribute__((target("bf16,neon"))) int16x8_t vreinterpretq_s16_bf16(bfloat16x8_t __p0) {
44569		int16x8_t __ret;
44570		__ret = __builtin_bit_cast(int16x8_t, __p0);
44571		return __ret;
44572		}
44573		__ai __attribute__((target("bf16,neon"))) uint8x8_t vreinterpret_u8_bf16(bfloat16x4_t __p0) {
44574		uint8x8_t __ret;
44575		__ret = __builtin_bit_cast(uint8x8_t, __p0);
44576		return __ret;
44577		}
44578		__ai __attribute__((target("bf16,neon"))) uint32x2_t vreinterpret_u32_bf16(bfloat16x4_t __p0) {
44579		uint32x2_t __ret;
44580		__ret = __builtin_bit_cast(uint32x2_t, __p0);
44581		return __ret;
44582		}
44583		__ai __attribute__((target("bf16,neon"))) uint64x1_t vreinterpret_u64_bf16(bfloat16x4_t __p0) {
44584		uint64x1_t __ret;
44585		__ret = __builtin_bit_cast(uint64x1_t, __p0);
44586		return __ret;
44587		}
44588		__ai __attribute__((target("bf16,neon"))) uint16x4_t vreinterpret_u16_bf16(bfloat16x4_t __p0) {
44589		uint16x4_t __ret;
44590		__ret = __builtin_bit_cast(uint16x4_t, __p0);
44591		return __ret;
44592		}
44593		__ai __attribute__((target("bf16,neon"))) int8x8_t vreinterpret_s8_bf16(bfloat16x4_t __p0) {
44594		int8x8_t __ret;
44595		__ret = __builtin_bit_cast(int8x8_t, __p0);
44596		return __ret;
44597		}
44598		__ai __attribute__((target("bf16,neon"))) float64x1_t vreinterpret_f64_bf16(bfloat16x4_t __p0) {
44599		float64x1_t __ret;
44600		__ret = __builtin_bit_cast(float64x1_t, __p0);
44601		return __ret;
44602		}
44603		__ai __attribute__((target("bf16,neon"))) float32x2_t vreinterpret_f32_bf16(bfloat16x4_t __p0) {
44604		float32x2_t __ret;
44605		__ret = __builtin_bit_cast(float32x2_t, __p0);
44606		return __ret;
44607		}
44608		__ai __attribute__((target("bf16,neon"))) float16x4_t vreinterpret_f16_bf16(bfloat16x4_t __p0) {
44609		float16x4_t __ret;
44610		__ret = __builtin_bit_cast(float16x4_t, __p0);
44611		return __ret;
44612		}
44613		__ai __attribute__((target("bf16,neon"))) int32x2_t vreinterpret_s32_bf16(bfloat16x4_t __p0) {
44614		int32x2_t __ret;
44615		__ret = __builtin_bit_cast(int32x2_t, __p0);
44616		return __ret;
44617		}
44618		__ai __attribute__((target("bf16,neon"))) int64x1_t vreinterpret_s64_bf16(bfloat16x4_t __p0) {
44619		int64x1_t __ret;
44620		__ret = __builtin_bit_cast(int64x1_t, __p0);
44621		return __ret;
44622		}
44623		__ai __attribute__((target("bf16,neon"))) int16x4_t vreinterpret_s16_bf16(bfloat16x4_t __p0) {
44624		int16x4_t __ret;
44625		__ret = __builtin_bit_cast(int16x4_t, __p0);
44626		return __ret;
44627		}
44628		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p8(poly8x16_t __p0) {
44629		bfloat16x8_t __ret;
44630		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
44631		return __ret;
44632		}
44633		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p128(poly128_t __p0) {
44634		bfloat16x8_t __ret;
44635		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
44636		return __ret;
44637		}
44638		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p64(poly64x2_t __p0) {
44639		bfloat16x8_t __ret;
44640		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44342	__ai __attribute__((target("neon,faminmax"))) float64x2_t vamaxq_f64(float64x2_t __p0, float64x2_t __p1) {
	44343	float64x2_t __ret;
	44344	__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vamaxq_f64(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 42));
44641	44345	return __ret;
44642	44346	}
44643		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_p16(poly16x8_t __p0) {
44644		bfloat16x8_t __ret;
44645		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44347	#else
	44348	__ai __attribute__((target("neon,faminmax"))) float64x2_t vamaxq_f64(float64x2_t __p0, float64x2_t __p1) {
	44349	float64x2_t __ret;
	44350	float64x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_64);
	44351	float64x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_64);
	44352	__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vamaxq_f64(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 42));
	44353	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_64);
44646	44354	return __ret;
44647	44355	}
44648		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u8(uint8x16_t __p0) {
44649		bfloat16x8_t __ret;
44650		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44356	#endif
	44357
	44358	#ifdef __LITTLE_ENDIAN__
	44359	__ai __attribute__((target("neon,faminmax"))) float32x4_t vamaxq_f32(float32x4_t __p0, float32x4_t __p1) {
	44360	float32x4_t __ret;
	44361	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vamaxq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 41));
44651	44362	return __ret;
44652	44363	}
44653		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u32(uint32x4_t __p0) {
44654		bfloat16x8_t __ret;
44655		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44364	#else
	44365	__ai __attribute__((target("neon,faminmax"))) float32x4_t vamaxq_f32(float32x4_t __p0, float32x4_t __p1) {
	44366	float32x4_t __ret;
	44367	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	44368	float32x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_32);
	44369	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vamaxq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 41));
	44370	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
44656	44371	return __ret;
44657	44372	}
44658		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u64(uint64x2_t __p0) {
44659		bfloat16x8_t __ret;
44660		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44373	#endif
	44374
	44375	#ifdef __LITTLE_ENDIAN__
	44376	__ai __attribute__((target("neon,faminmax"))) float16x8_t vamaxq_f16(float16x8_t __p0, float16x8_t __p1) {
	44377	float16x8_t __ret;
	44378	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vamaxq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
44661	44379	return __ret;
44662	44380	}
44663		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_u16(uint16x8_t __p0) {
44664		bfloat16x8_t __ret;
44665		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44381	#else
	44382	__ai __attribute__((target("neon,faminmax"))) float16x8_t vamaxq_f16(float16x8_t __p0, float16x8_t __p1) {
	44383	float16x8_t __ret;
	44384	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	44385	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	44386	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vamaxq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 40));
	44387	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44666	44388	return __ret;
44667	44389	}
44668		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s8(int8x16_t __p0) {
44669		bfloat16x8_t __ret;
44670		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44390	#endif
	44391
	44392	#ifdef __LITTLE_ENDIAN__
	44393	__ai __attribute__((target("neon,faminmax"))) float32x2_t vamax_f32(float32x2_t __p0, float32x2_t __p1) {
	44394	float32x2_t __ret;
	44395	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamax_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 9));
44671	44396	return __ret;
44672	44397	}
44673		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_f64(float64x2_t __p0) {
44674		bfloat16x8_t __ret;
44675		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44398	#else
	44399	__ai __attribute__((target("neon,faminmax"))) float32x2_t vamax_f32(float32x2_t __p0, float32x2_t __p1) {
	44400	float32x2_t __ret;
	44401	float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
	44402	float32x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_32);
	44403	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamax_f32(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 9));
	44404	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
44676	44405	return __ret;
44677	44406	}
44678		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_f32(float32x4_t __p0) {
44679		bfloat16x8_t __ret;
44680		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44407	#endif
	44408
	44409	#ifdef __LITTLE_ENDIAN__
	44410	__ai __attribute__((target("neon,faminmax"))) float16x4_t vamax_f16(float16x4_t __p0, float16x4_t __p1) {
	44411	float16x4_t __ret;
	44412	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamax_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
44681	44413	return __ret;
44682	44414	}
44683		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_f16(float16x8_t __p0) {
44684		bfloat16x8_t __ret;
44685		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44415	#else
	44416	__ai __attribute__((target("neon,faminmax"))) float16x4_t vamax_f16(float16x4_t __p0, float16x4_t __p1) {
	44417	float16x4_t __ret;
	44418	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
	44419	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
	44420	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamax_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 8));
	44421	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
44686	44422	return __ret;
44687	44423	}
44688		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s32(int32x4_t __p0) {
44689		bfloat16x8_t __ret;
44690		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44424	#endif
	44425
	44426	#ifdef __LITTLE_ENDIAN__
	44427	__ai __attribute__((target("neon,faminmax"))) float64x2_t vaminq_f64(float64x2_t __p0, float64x2_t __p1) {
	44428	float64x2_t __ret;
	44429	__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vaminq_f64(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 42));
44691	44430	return __ret;
44692	44431	}
44693		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s64(int64x2_t __p0) {
44694		bfloat16x8_t __ret;
44695		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44432	#else
	44433	__ai __attribute__((target("neon,faminmax"))) float64x2_t vaminq_f64(float64x2_t __p0, float64x2_t __p1) {
	44434	float64x2_t __ret;
	44435	float64x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_64);
	44436	float64x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_64);
	44437	__ret = __builtin_bit_cast(float64x2_t, __builtin_neon_vaminq_f64(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 42));
	44438	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_64);
44696	44439	return __ret;
44697	44440	}
44698		__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vreinterpretq_bf16_s16(int16x8_t __p0) {
44699		bfloat16x8_t __ret;
44700		__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	44441	#endif
	44442
	44443	#ifdef __LITTLE_ENDIAN__
	44444	__ai __attribute__((target("neon,faminmax"))) float32x4_t vaminq_f32(float32x4_t __p0, float32x4_t __p1) {
	44445	float32x4_t __ret;
	44446	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vaminq_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 41));
44701	44447	return __ret;
44702	44448	}
44703		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_p8(poly8x8_t __p0) {
44704		bfloat16x4_t __ret;
44705		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44449	#else
	44450	__ai __attribute__((target("neon,faminmax"))) float32x4_t vaminq_f32(float32x4_t __p0, float32x4_t __p1) {
	44451	float32x4_t __ret;
	44452	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	44453	float32x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_32);
	44454	__ret = __builtin_bit_cast(float32x4_t, __builtin_neon_vaminq_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 41));
	44455	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_32);
44706	44456	return __ret;
44707	44457	}
44708		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_p64(poly64x1_t __p0) {
44709		bfloat16x4_t __ret;
44710		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44458	#endif
	44459
	44460	#ifdef __LITTLE_ENDIAN__
	44461	__ai __attribute__((target("neon,faminmax"))) float16x8_t vaminq_f16(float16x8_t __p0, float16x8_t __p1) {
	44462	float16x8_t __ret;
	44463	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vaminq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
44711	44464	return __ret;
44712	44465	}
44713		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_p16(poly16x4_t __p0) {
44714		bfloat16x4_t __ret;
44715		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44466	#else
	44467	__ai __attribute__((target("neon,faminmax"))) float16x8_t vaminq_f16(float16x8_t __p0, float16x8_t __p1) {
	44468	float16x8_t __ret;
	44469	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	44470	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	44471	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vaminq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 40));
	44472	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44716	44473	return __ret;
44717	44474	}
44718		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u8(uint8x8_t __p0) {
44719		bfloat16x4_t __ret;
44720		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44475	#endif
	44476
	44477	#ifdef __LITTLE_ENDIAN__
	44478	__ai __attribute__((target("neon,faminmax"))) float32x2_t vamin_f32(float32x2_t __p0, float32x2_t __p1) {
	44479	float32x2_t __ret;
	44480	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamin_f32(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 9));
44721	44481	return __ret;
44722	44482	}
44723		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u32(uint32x2_t __p0) {
44724		bfloat16x4_t __ret;
44725		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44483	#else
	44484	__ai __attribute__((target("neon,faminmax"))) float32x2_t vamin_f32(float32x2_t __p0, float32x2_t __p1) {
	44485	float32x2_t __ret;
	44486	float32x2_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_32);
	44487	float32x2_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_32);
	44488	__ret = __builtin_bit_cast(float32x2_t, __builtin_neon_vamin_f32(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 9));
	44489	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_32);
44726	44490	return __ret;
44727	44491	}
44728		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u64(uint64x1_t __p0) {
44729		bfloat16x4_t __ret;
44730		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44492	#endif
	44493
	44494	#ifdef __LITTLE_ENDIAN__
	44495	__ai __attribute__((target("neon,faminmax"))) float16x4_t vamin_f16(float16x4_t __p0, float16x4_t __p1) {
	44496	float16x4_t __ret;
	44497	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamin_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
44731	44498	return __ret;
44732	44499	}
44733		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_u16(uint16x4_t __p0) {
44734		bfloat16x4_t __ret;
44735		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44500	#else
	44501	__ai __attribute__((target("neon,faminmax"))) float16x4_t vamin_f16(float16x4_t __p0, float16x4_t __p1) {
	44502	float16x4_t __ret;
	44503	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
	44504	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
	44505	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vamin_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 8));
	44506	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
44736	44507	return __ret;
44737	44508	}
44738		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s8(int8x8_t __p0) {
44739		bfloat16x4_t __ret;
44740		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44509	#endif
	44510
	44511	#endif
	44512	#if defined(__aarch64__) \|\| defined(__arm64ec__)
	44513	__ai __attribute__((target("aes,neon"))) poly128_t vmull_p64(poly64_t __p0, poly64_t __p1) {
	44514	poly128_t __ret;
	44515	__ret = __builtin_bit_cast(poly128_t, __builtin_neon_vmull_p64(__p0, __p1));
44741	44516	return __ret;
44742	44517	}
44743		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_f64(float64x1_t __p0) {
	44518	#ifdef __LITTLE_ENDIAN__
	44519	__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vcvt_bf16_f32(float32x4_t __p0) {
44744	44520	bfloat16x4_t __ret;
44745		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44521	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vcvt_bf16_f32(__builtin_bit_cast(int8x16_t, __p0), 11));
44746	44522	return __ret;
44747	44523	}
44748		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_f32(float32x2_t __p0) {
	44524	#else
	44525	__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vcvt_bf16_f32(float32x4_t __p0) {
44749	44526	bfloat16x4_t __ret;
44750		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44527	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	44528	__ret = __builtin_bit_cast(bfloat16x4_t, __builtin_neon_vcvt_bf16_f32(__builtin_bit_cast(int8x16_t, __rev0), 11));
	44529	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
44751	44530	return __ret;
44752	44531	}
44753		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_f16(float16x4_t __p0) {
44754		bfloat16x4_t __ret;
44755		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44532	#endif
	44533
	44534	#ifdef __LITTLE_ENDIAN__
	44535	__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_high_bf16_f32(bfloat16x8_t __p0, float32x4_t __p1) {
	44536	bfloat16x8_t __ret;
	44537	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_high_bf16_f32(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 43));
44756	44538	return __ret;
44757	44539	}
44758		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s32(int32x2_t __p0) {
44759		bfloat16x4_t __ret;
44760		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44540	#else
	44541	__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_high_bf16_f32(bfloat16x8_t __p0, float32x4_t __p1) {
	44542	bfloat16x8_t __ret;
	44543	bfloat16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	44544	float32x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_32);
	44545	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_high_bf16_f32(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 43));
	44546	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44761	44547	return __ret;
44762	44548	}
44763		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s64(int64x1_t __p0) {
44764		bfloat16x4_t __ret;
44765		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44549	#endif
	44550
	44551	#ifdef __LITTLE_ENDIAN__
	44552	__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_low_bf16_f32(float32x4_t __p0) {
	44553	bfloat16x8_t __ret;
	44554	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_low_bf16_f32(__builtin_bit_cast(int8x16_t, __p0), 43));
44766	44555	return __ret;
44767	44556	}
44768		__ai __attribute__((target("bf16,neon"))) bfloat16x4_t vreinterpret_bf16_s16(int16x4_t __p0) {
44769		bfloat16x4_t __ret;
44770		__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	44557	#else
	44558	__ai __attribute__((target("bf16,neon"))) bfloat16x8_t vcvtq_low_bf16_f32(float32x4_t __p0) {
	44559	bfloat16x8_t __ret;
	44560	float32x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_32);
	44561	__ret = __builtin_bit_cast(bfloat16x8_t, __builtin_neon_vcvtq_low_bf16_f32(__builtin_bit_cast(int8x16_t, __rev0), 43));
	44562	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
44771	44563	return __ret;
44772	44564	}
	44565	#endif
	44566
44773	44567	#ifdef __LITTLE_ENDIAN__
44774		#define vdotq_laneq_u32(__p0_242, __p1_242, __p2_242, __p3_242) __extension__ ({ \
44775		uint32x4_t __ret_242; \
44776		uint32x4_t __s0_242 = __p0_242; \
44777		uint8x16_t __s1_242 = __p1_242; \
44778		uint8x16_t __s2_242 = __p2_242; \
44779		__ret_242 = vdotq_u32(__s0_242, __s1_242, __builtin_bit_cast(uint8x16_t, splatq_laneq_u32(__builtin_bit_cast(uint32x4_t, __s2_242), __p3_242))); \
44780		__ret_242; \
	44568	#define vdotq_laneq_u32(__p0_234, __p1_234, __p2_234, __p3_234) __extension__ ({ \
	44569	uint32x4_t __ret_234; \
	44570	uint32x4_t __s0_234 = __p0_234; \
	44571	uint8x16_t __s1_234 = __p1_234; \
	44572	uint8x16_t __s2_234 = __p2_234; \
	44573	__ret_234 = vdotq_u32(__s0_234, __s1_234, __builtin_bit_cast(uint8x16_t, splatq_laneq_u32(__builtin_bit_cast(uint32x4_t, __s2_234), __p3_234))); \
	44574	__ret_234; \
44781	44575	})
44782	44576	#else
44783		#define vdotq_laneq_u32(__p0_243, __p1_243, __p2_243, __p3_243) __extension__ ({ \
44784		uint32x4_t __ret_243; \
44785		uint32x4_t __s0_243 = __p0_243; \
44786		uint8x16_t __s1_243 = __p1_243; \
44787		uint8x16_t __s2_243 = __p2_243; \
44788		uint32x4_t __rev0_243; __rev0_243 = __builtin_shufflevector(__s0_243, __s0_243, __lane_reverse_128_32); \
44789		uint8x16_t __rev1_243; __rev1_243 = __builtin_shufflevector(__s1_243, __s1_243, __lane_reverse_128_8); \
44790		uint8x16_t __rev2_243; __rev2_243 = __builtin_shufflevector(__s2_243, __s2_243, __lane_reverse_128_8); \
44791		__ret_243 = __noswap_vdotq_u32(__rev0_243, __rev1_243, __builtin_bit_cast(uint8x16_t, __noswap_splatq_laneq_u32(__builtin_bit_cast(uint32x4_t, __rev2_243), __p3_243))); \
44792		__ret_243 = __builtin_shufflevector(__ret_243, __ret_243, __lane_reverse_128_32); \
44793		__ret_243; \
	44577	#define vdotq_laneq_u32(__p0_235, __p1_235, __p2_235, __p3_235) __extension__ ({ \
	44578	uint32x4_t __ret_235; \
	44579	uint32x4_t __s0_235 = __p0_235; \
	44580	uint8x16_t __s1_235 = __p1_235; \
	44581	uint8x16_t __s2_235 = __p2_235; \
	44582	uint32x4_t __rev0_235; __rev0_235 = __builtin_shufflevector(__s0_235, __s0_235, __lane_reverse_128_32); \
	44583	uint8x16_t __rev1_235; __rev1_235 = __builtin_shufflevector(__s1_235, __s1_235, __lane_reverse_128_8); \
	44584	uint8x16_t __rev2_235; __rev2_235 = __builtin_shufflevector(__s2_235, __s2_235, __lane_reverse_128_8); \
	44585	__ret_235 = __noswap_vdotq_u32(__rev0_235, __rev1_235, __builtin_bit_cast(uint8x16_t, __noswap_splatq_laneq_u32(__builtin_bit_cast(uint32x4_t, __rev2_235), __p3_235))); \
	44586	__ret_235 = __builtin_shufflevector(__ret_235, __ret_235, __lane_reverse_128_32); \
	44587	__ret_235; \
44794	44588	})
44795	44589	#endif
44796	44590
44797	44591	#ifdef __LITTLE_ENDIAN__
44798		#define vdotq_laneq_s32(__p0_244, __p1_244, __p2_244, __p3_244) __extension__ ({ \
44799		int32x4_t __ret_244; \
44800		int32x4_t __s0_244 = __p0_244; \
44801		int8x16_t __s1_244 = __p1_244; \
44802		int8x16_t __s2_244 = __p2_244; \
44803		__ret_244 = vdotq_s32(__s0_244, __s1_244, __builtin_bit_cast(int8x16_t, splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_244), __p3_244))); \
44804		__ret_244; \
	44592	#define vdotq_laneq_s32(__p0_236, __p1_236, __p2_236, __p3_236) __extension__ ({ \
	44593	int32x4_t __ret_236; \
	44594	int32x4_t __s0_236 = __p0_236; \
	44595	int8x16_t __s1_236 = __p1_236; \
	44596	int8x16_t __s2_236 = __p2_236; \
	44597	__ret_236 = vdotq_s32(__s0_236, __s1_236, __builtin_bit_cast(int8x16_t, splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_236), __p3_236))); \
	44598	__ret_236; \
44805	44599	})
44806	44600	#else
44807		#define vdotq_laneq_s32(__p0_245, __p1_245, __p2_245, __p3_245) __extension__ ({ \
44808		int32x4_t __ret_245; \
44809		int32x4_t __s0_245 = __p0_245; \
44810		int8x16_t __s1_245 = __p1_245; \
44811		int8x16_t __s2_245 = __p2_245; \
44812		int32x4_t __rev0_245; __rev0_245 = __builtin_shufflevector(__s0_245, __s0_245, __lane_reverse_128_32); \
44813		int8x16_t __rev1_245; __rev1_245 = __builtin_shufflevector(__s1_245, __s1_245, __lane_reverse_128_8); \
44814		int8x16_t __rev2_245; __rev2_245 = __builtin_shufflevector(__s2_245, __s2_245, __lane_reverse_128_8); \
44815		__ret_245 = __noswap_vdotq_s32(__rev0_245, __rev1_245, __builtin_bit_cast(int8x16_t, __noswap_splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_245), __p3_245))); \
44816		__ret_245 = __builtin_shufflevector(__ret_245, __ret_245, __lane_reverse_128_32); \
44817		__ret_245; \
	44601	#define vdotq_laneq_s32(__p0_237, __p1_237, __p2_237, __p3_237) __extension__ ({ \
	44602	int32x4_t __ret_237; \
	44603	int32x4_t __s0_237 = __p0_237; \
	44604	int8x16_t __s1_237 = __p1_237; \
	44605	int8x16_t __s2_237 = __p2_237; \
	44606	int32x4_t __rev0_237; __rev0_237 = __builtin_shufflevector(__s0_237, __s0_237, __lane_reverse_128_32); \
	44607	int8x16_t __rev1_237; __rev1_237 = __builtin_shufflevector(__s1_237, __s1_237, __lane_reverse_128_8); \
	44608	int8x16_t __rev2_237; __rev2_237 = __builtin_shufflevector(__s2_237, __s2_237, __lane_reverse_128_8); \
	44609	__ret_237 = __noswap_vdotq_s32(__rev0_237, __rev1_237, __builtin_bit_cast(int8x16_t, __noswap_splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_237), __p3_237))); \
	44610	__ret_237 = __builtin_shufflevector(__ret_237, __ret_237, __lane_reverse_128_32); \
	44611	__ret_237; \
44818	44612	})
44819	44613	#endif
44820	44614
44821	44615	#ifdef __LITTLE_ENDIAN__
44822		#define vdot_laneq_u32(__p0_246, __p1_246, __p2_246, __p3_246) __extension__ ({ \
44823		uint32x2_t __ret_246; \
44824		uint32x2_t __s0_246 = __p0_246; \
44825		uint8x8_t __s1_246 = __p1_246; \
44826		uint8x16_t __s2_246 = __p2_246; \
44827		__ret_246 = vdot_u32(__s0_246, __s1_246, __builtin_bit_cast(uint8x8_t, splat_laneq_u32(__builtin_bit_cast(uint32x4_t, __s2_246), __p3_246))); \
44828		__ret_246; \
	44616	#define vdot_laneq_u32(__p0_238, __p1_238, __p2_238, __p3_238) __extension__ ({ \
	44617	uint32x2_t __ret_238; \
	44618	uint32x2_t __s0_238 = __p0_238; \
	44619	uint8x8_t __s1_238 = __p1_238; \
	44620	uint8x16_t __s2_238 = __p2_238; \
	44621	__ret_238 = vdot_u32(__s0_238, __s1_238, __builtin_bit_cast(uint8x8_t, splat_laneq_u32(__builtin_bit_cast(uint32x4_t, __s2_238), __p3_238))); \
	44622	__ret_238; \
44829	44623	})
44830	44624	#else
44831		#define vdot_laneq_u32(__p0_247, __p1_247, __p2_247, __p3_247) __extension__ ({ \
44832		uint32x2_t __ret_247; \
44833		uint32x2_t __s0_247 = __p0_247; \
44834		uint8x8_t __s1_247 = __p1_247; \
44835		uint8x16_t __s2_247 = __p2_247; \
44836		uint32x2_t __rev0_247; __rev0_247 = __builtin_shufflevector(__s0_247, __s0_247, __lane_reverse_64_32); \
44837		uint8x8_t __rev1_247; __rev1_247 = __builtin_shufflevector(__s1_247, __s1_247, __lane_reverse_64_8); \
44838		uint8x16_t __rev2_247; __rev2_247 = __builtin_shufflevector(__s2_247, __s2_247, __lane_reverse_128_8); \
44839		__ret_247 = __noswap_vdot_u32(__rev0_247, __rev1_247, __builtin_bit_cast(uint8x8_t, __noswap_splat_laneq_u32(__builtin_bit_cast(uint32x4_t, __rev2_247), __p3_247))); \
44840		__ret_247 = __builtin_shufflevector(__ret_247, __ret_247, __lane_reverse_64_32); \
44841		__ret_247; \
	44625	#define vdot_laneq_u32(__p0_239, __p1_239, __p2_239, __p3_239) __extension__ ({ \
	44626	uint32x2_t __ret_239; \
	44627	uint32x2_t __s0_239 = __p0_239; \
	44628	uint8x8_t __s1_239 = __p1_239; \
	44629	uint8x16_t __s2_239 = __p2_239; \
	44630	uint32x2_t __rev0_239; __rev0_239 = __builtin_shufflevector(__s0_239, __s0_239, __lane_reverse_64_32); \
	44631	uint8x8_t __rev1_239; __rev1_239 = __builtin_shufflevector(__s1_239, __s1_239, __lane_reverse_64_8); \
	44632	uint8x16_t __rev2_239; __rev2_239 = __builtin_shufflevector(__s2_239, __s2_239, __lane_reverse_128_8); \
	44633	__ret_239 = __noswap_vdot_u32(__rev0_239, __rev1_239, __builtin_bit_cast(uint8x8_t, __noswap_splat_laneq_u32(__builtin_bit_cast(uint32x4_t, __rev2_239), __p3_239))); \
	44634	__ret_239 = __builtin_shufflevector(__ret_239, __ret_239, __lane_reverse_64_32); \
	44635	__ret_239; \
44842	44636	})
44843	44637	#endif
44844	44638
44845	44639	#ifdef __LITTLE_ENDIAN__
44846		#define vdot_laneq_s32(__p0_248, __p1_248, __p2_248, __p3_248) __extension__ ({ \
44847		int32x2_t __ret_248; \
44848		int32x2_t __s0_248 = __p0_248; \
44849		int8x8_t __s1_248 = __p1_248; \
44850		int8x16_t __s2_248 = __p2_248; \
44851		__ret_248 = vdot_s32(__s0_248, __s1_248, __builtin_bit_cast(int8x8_t, splat_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_248), __p3_248))); \
44852		__ret_248; \
	44640	#define vdot_laneq_s32(__p0_240, __p1_240, __p2_240, __p3_240) __extension__ ({ \
	44641	int32x2_t __ret_240; \
	44642	int32x2_t __s0_240 = __p0_240; \
	44643	int8x8_t __s1_240 = __p1_240; \
	44644	int8x16_t __s2_240 = __p2_240; \
	44645	__ret_240 = vdot_s32(__s0_240, __s1_240, __builtin_bit_cast(int8x8_t, splat_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_240), __p3_240))); \
	44646	__ret_240; \
44853	44647	})
44854	44648	#else
44855		#define vdot_laneq_s32(__p0_249, __p1_249, __p2_249, __p3_249) __extension__ ({ \
44856		int32x2_t __ret_249; \
44857		int32x2_t __s0_249 = __p0_249; \
44858		int8x8_t __s1_249 = __p1_249; \
44859		int8x16_t __s2_249 = __p2_249; \
44860		int32x2_t __rev0_249; __rev0_249 = __builtin_shufflevector(__s0_249, __s0_249, __lane_reverse_64_32); \
44861		int8x8_t __rev1_249; __rev1_249 = __builtin_shufflevector(__s1_249, __s1_249, __lane_reverse_64_8); \
44862		int8x16_t __rev2_249; __rev2_249 = __builtin_shufflevector(__s2_249, __s2_249, __lane_reverse_128_8); \
44863		__ret_249 = __noswap_vdot_s32(__rev0_249, __rev1_249, __builtin_bit_cast(int8x8_t, __noswap_splat_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_249), __p3_249))); \
44864		__ret_249 = __builtin_shufflevector(__ret_249, __ret_249, __lane_reverse_64_32); \
44865		__ret_249; \
	44649	#define vdot_laneq_s32(__p0_241, __p1_241, __p2_241, __p3_241) __extension__ ({ \
	44650	int32x2_t __ret_241; \
	44651	int32x2_t __s0_241 = __p0_241; \
	44652	int8x8_t __s1_241 = __p1_241; \
	44653	int8x16_t __s2_241 = __p2_241; \
	44654	int32x2_t __rev0_241; __rev0_241 = __builtin_shufflevector(__s0_241, __s0_241, __lane_reverse_64_32); \
	44655	int8x8_t __rev1_241; __rev1_241 = __builtin_shufflevector(__s1_241, __s1_241, __lane_reverse_64_8); \
	44656	int8x16_t __rev2_241; __rev2_241 = __builtin_shufflevector(__s2_241, __s2_241, __lane_reverse_128_8); \
	44657	__ret_241 = __noswap_vdot_s32(__rev0_241, __rev1_241, __builtin_bit_cast(int8x8_t, __noswap_splat_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_241), __p3_241))); \
	44658	__ret_241 = __builtin_shufflevector(__ret_241, __ret_241, __lane_reverse_64_32); \
	44659	__ret_241; \
44866	44660	})
44867	44661	#endif
44868	44662
...	...	@@ -45317,533 +45111,533 @@ __ai __attribute__((target("fullfp16,neon"))) float16x4_t vdiv_f16(float16x4_t _
45317	45111	#endif
45318	45112
45319	45113	#ifdef __LITTLE_ENDIAN__
45320		#define vfmsh_lane_f16(__p0_250, __p1_250, __p2_250, __p3_250) __extension__ ({ \
45321		float16_t __ret_250; \
45322		float16_t __s0_250 = __p0_250; \
45323		float16_t __s1_250 = __p1_250; \
45324		float16x4_t __s2_250 = __p2_250; \
45325		__ret_250 = vfmah_lane_f16(__s0_250, -__s1_250, __s2_250, __p3_250); \
	45114	#define vfmsh_lane_f16(__p0_242, __p1_242, __p2_242, __p3_242) __extension__ ({ \
	45115	float16_t __ret_242; \
	45116	float16_t __s0_242 = __p0_242; \
	45117	float16_t __s1_242 = __p1_242; \
	45118	float16x4_t __s2_242 = __p2_242; \
	45119	__ret_242 = vfmah_lane_f16(__s0_242, -__s1_242, __s2_242, __p3_242); \
	45120	__ret_242; \
	45121	})
	45122	#else
	45123	#define vfmsh_lane_f16(__p0_243, __p1_243, __p2_243, __p3_243) __extension__ ({ \
	45124	float16_t __ret_243; \
	45125	float16_t __s0_243 = __p0_243; \
	45126	float16_t __s1_243 = __p1_243; \
	45127	float16x4_t __s2_243 = __p2_243; \
	45128	float16x4_t __rev2_243; __rev2_243 = __builtin_shufflevector(__s2_243, __s2_243, __lane_reverse_64_16); \
	45129	__ret_243 = __noswap_vfmah_lane_f16(__s0_243, -__s1_243, __rev2_243, __p3_243); \
	45130	__ret_243; \
	45131	})
	45132	#endif
	45133
	45134	#ifdef __LITTLE_ENDIAN__
	45135	#define vfmsq_lane_f16(__p0_244, __p1_244, __p2_244, __p3_244) __extension__ ({ \
	45136	float16x8_t __ret_244; \
	45137	float16x8_t __s0_244 = __p0_244; \
	45138	float16x8_t __s1_244 = __p1_244; \
	45139	float16x4_t __s2_244 = __p2_244; \
	45140	__ret_244 = vfmaq_lane_f16(__s0_244, -__s1_244, __s2_244, __p3_244); \
	45141	__ret_244; \
	45142	})
	45143	#else
	45144	#define vfmsq_lane_f16(__p0_245, __p1_245, __p2_245, __p3_245) __extension__ ({ \
	45145	float16x8_t __ret_245; \
	45146	float16x8_t __s0_245 = __p0_245; \
	45147	float16x8_t __s1_245 = __p1_245; \
	45148	float16x4_t __s2_245 = __p2_245; \
	45149	float16x8_t __rev0_245; __rev0_245 = __builtin_shufflevector(__s0_245, __s0_245, __lane_reverse_128_16); \
	45150	float16x8_t __rev1_245; __rev1_245 = __builtin_shufflevector(__s1_245, __s1_245, __lane_reverse_128_16); \
	45151	float16x4_t __rev2_245; __rev2_245 = __builtin_shufflevector(__s2_245, __s2_245, __lane_reverse_64_16); \
	45152	__ret_245 = __noswap_vfmaq_lane_f16(__rev0_245, -__rev1_245, __rev2_245, __p3_245); \
	45153	__ret_245 = __builtin_shufflevector(__ret_245, __ret_245, __lane_reverse_128_16); \
	45154	__ret_245; \
	45155	})
	45156	#endif
	45157
	45158	#ifdef __LITTLE_ENDIAN__
	45159	#define vfms_lane_f16(__p0_246, __p1_246, __p2_246, __p3_246) __extension__ ({ \
	45160	float16x4_t __ret_246; \
	45161	float16x4_t __s0_246 = __p0_246; \
	45162	float16x4_t __s1_246 = __p1_246; \
	45163	float16x4_t __s2_246 = __p2_246; \
	45164	__ret_246 = vfma_lane_f16(__s0_246, -__s1_246, __s2_246, __p3_246); \
	45165	__ret_246; \
	45166	})
	45167	#else
	45168	#define vfms_lane_f16(__p0_247, __p1_247, __p2_247, __p3_247) __extension__ ({ \
	45169	float16x4_t __ret_247; \
	45170	float16x4_t __s0_247 = __p0_247; \
	45171	float16x4_t __s1_247 = __p1_247; \
	45172	float16x4_t __s2_247 = __p2_247; \
	45173	float16x4_t __rev0_247; __rev0_247 = __builtin_shufflevector(__s0_247, __s0_247, __lane_reverse_64_16); \
	45174	float16x4_t __rev1_247; __rev1_247 = __builtin_shufflevector(__s1_247, __s1_247, __lane_reverse_64_16); \
	45175	float16x4_t __rev2_247; __rev2_247 = __builtin_shufflevector(__s2_247, __s2_247, __lane_reverse_64_16); \
	45176	__ret_247 = __noswap_vfma_lane_f16(__rev0_247, -__rev1_247, __rev2_247, __p3_247); \
	45177	__ret_247 = __builtin_shufflevector(__ret_247, __ret_247, __lane_reverse_64_16); \
	45178	__ret_247; \
	45179	})
	45180	#endif
	45181
	45182	#ifdef __LITTLE_ENDIAN__
	45183	#define vfmsh_laneq_f16(__p0_248, __p1_248, __p2_248, __p3_248) __extension__ ({ \
	45184	float16_t __ret_248; \
	45185	float16_t __s0_248 = __p0_248; \
	45186	float16_t __s1_248 = __p1_248; \
	45187	float16x8_t __s2_248 = __p2_248; \
	45188	__ret_248 = vfmah_laneq_f16(__s0_248, -__s1_248, __s2_248, __p3_248); \
	45189	__ret_248; \
	45190	})
	45191	#else
	45192	#define vfmsh_laneq_f16(__p0_249, __p1_249, __p2_249, __p3_249) __extension__ ({ \
	45193	float16_t __ret_249; \
	45194	float16_t __s0_249 = __p0_249; \
	45195	float16_t __s1_249 = __p1_249; \
	45196	float16x8_t __s2_249 = __p2_249; \
	45197	float16x8_t __rev2_249; __rev2_249 = __builtin_shufflevector(__s2_249, __s2_249, __lane_reverse_128_16); \
	45198	__ret_249 = __noswap_vfmah_laneq_f16(__s0_249, -__s1_249, __rev2_249, __p3_249); \
	45199	__ret_249; \
	45200	})
	45201	#endif
	45202
	45203	#ifdef __LITTLE_ENDIAN__
	45204	#define vfmsq_laneq_f16(__p0_250, __p1_250, __p2_250, __p3_250) __extension__ ({ \
	45205	float16x8_t __ret_250; \
	45206	float16x8_t __s0_250 = __p0_250; \
	45207	float16x8_t __s1_250 = __p1_250; \
	45208	float16x8_t __s2_250 = __p2_250; \
	45209	__ret_250 = vfmaq_laneq_f16(__s0_250, -__s1_250, __s2_250, __p3_250); \
45326	45210	__ret_250; \
45327	45211	})
45328	45212	#else
45329		#define vfmsh_lane_f16(__p0_251, __p1_251, __p2_251, __p3_251) __extension__ ({ \
45330		float16_t __ret_251; \
45331		float16_t __s0_251 = __p0_251; \
45332		float16_t __s1_251 = __p1_251; \
45333		float16x4_t __s2_251 = __p2_251; \
45334		float16x4_t __rev2_251; __rev2_251 = __builtin_shufflevector(__s2_251, __s2_251, __lane_reverse_64_16); \
45335		__ret_251 = __noswap_vfmah_lane_f16(__s0_251, -__s1_251, __rev2_251, __p3_251); \
	45213	#define vfmsq_laneq_f16(__p0_251, __p1_251, __p2_251, __p3_251) __extension__ ({ \
	45214	float16x8_t __ret_251; \
	45215	float16x8_t __s0_251 = __p0_251; \
	45216	float16x8_t __s1_251 = __p1_251; \
	45217	float16x8_t __s2_251 = __p2_251; \
	45218	float16x8_t __rev0_251; __rev0_251 = __builtin_shufflevector(__s0_251, __s0_251, __lane_reverse_128_16); \
	45219	float16x8_t __rev1_251; __rev1_251 = __builtin_shufflevector(__s1_251, __s1_251, __lane_reverse_128_16); \
	45220	float16x8_t __rev2_251; __rev2_251 = __builtin_shufflevector(__s2_251, __s2_251, __lane_reverse_128_16); \
	45221	__ret_251 = __noswap_vfmaq_laneq_f16(__rev0_251, -__rev1_251, __rev2_251, __p3_251); \
	45222	__ret_251 = __builtin_shufflevector(__ret_251, __ret_251, __lane_reverse_128_16); \
45336	45223	__ret_251; \
45337	45224	})
45338	45225	#endif
45339	45226
45340	45227	#ifdef __LITTLE_ENDIAN__
45341		#define vfmsq_lane_f16(__p0_252, __p1_252, __p2_252, __p3_252) __extension__ ({ \
45342		float16x8_t __ret_252; \
45343		float16x8_t __s0_252 = __p0_252; \
45344		float16x8_t __s1_252 = __p1_252; \
45345		float16x4_t __s2_252 = __p2_252; \
45346		__ret_252 = vfmaq_lane_f16(__s0_252, -__s1_252, __s2_252, __p3_252); \
	45228	#define vfms_laneq_f16(__p0_252, __p1_252, __p2_252, __p3_252) __extension__ ({ \
	45229	float16x4_t __ret_252; \
	45230	float16x4_t __s0_252 = __p0_252; \
	45231	float16x4_t __s1_252 = __p1_252; \
	45232	float16x8_t __s2_252 = __p2_252; \
	45233	__ret_252 = vfma_laneq_f16(__s0_252, -__s1_252, __s2_252, __p3_252); \
45347	45234	__ret_252; \
45348	45235	})
45349	45236	#else
45350		#define vfmsq_lane_f16(__p0_253, __p1_253, __p2_253, __p3_253) __extension__ ({ \
45351		float16x8_t __ret_253; \
45352		float16x8_t __s0_253 = __p0_253; \
45353		float16x8_t __s1_253 = __p1_253; \
45354		float16x4_t __s2_253 = __p2_253; \
45355		float16x8_t __rev0_253; __rev0_253 = __builtin_shufflevector(__s0_253, __s0_253, __lane_reverse_128_16); \
45356		float16x8_t __rev1_253; __rev1_253 = __builtin_shufflevector(__s1_253, __s1_253, __lane_reverse_128_16); \
45357		float16x4_t __rev2_253; __rev2_253 = __builtin_shufflevector(__s2_253, __s2_253, __lane_reverse_64_16); \
45358		__ret_253 = __noswap_vfmaq_lane_f16(__rev0_253, -__rev1_253, __rev2_253, __p3_253); \
45359		__ret_253 = __builtin_shufflevector(__ret_253, __ret_253, __lane_reverse_128_16); \
	45237	#define vfms_laneq_f16(__p0_253, __p1_253, __p2_253, __p3_253) __extension__ ({ \
	45238	float16x4_t __ret_253; \
	45239	float16x4_t __s0_253 = __p0_253; \
	45240	float16x4_t __s1_253 = __p1_253; \
	45241	float16x8_t __s2_253 = __p2_253; \
	45242	float16x4_t __rev0_253; __rev0_253 = __builtin_shufflevector(__s0_253, __s0_253, __lane_reverse_64_16); \
	45243	float16x4_t __rev1_253; __rev1_253 = __builtin_shufflevector(__s1_253, __s1_253, __lane_reverse_64_16); \
	45244	float16x8_t __rev2_253; __rev2_253 = __builtin_shufflevector(__s2_253, __s2_253, __lane_reverse_128_16); \
	45245	__ret_253 = __noswap_vfma_laneq_f16(__rev0_253, -__rev1_253, __rev2_253, __p3_253); \
	45246	__ret_253 = __builtin_shufflevector(__ret_253, __ret_253, __lane_reverse_64_16); \
45360	45247	__ret_253; \
45361	45248	})
45362	45249	#endif
45363	45250
45364	45251	#ifdef __LITTLE_ENDIAN__
45365		#define vfms_lane_f16(__p0_254, __p1_254, __p2_254, __p3_254) __extension__ ({ \
45366		float16x4_t __ret_254; \
45367		float16x4_t __s0_254 = __p0_254; \
45368		float16x4_t __s1_254 = __p1_254; \
45369		float16x4_t __s2_254 = __p2_254; \
45370		__ret_254 = vfma_lane_f16(__s0_254, -__s1_254, __s2_254, __p3_254); \
	45252	#define vfmsq_n_f16(__p0, __p1, __p2) __extension__ ({ \
	45253	float16x8_t __ret; \
	45254	float16x8_t __s0 = __p0; \
	45255	float16x8_t __s1 = __p1; \
	45256	float16_t __s2 = __p2; \
	45257	__ret = vfmaq_f16(__s0, -__s1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	45258	__ret; \
	45259	})
	45260	#else
	45261	#define vfmsq_n_f16(__p0, __p1, __p2) __extension__ ({ \
	45262	float16x8_t __ret; \
	45263	float16x8_t __s0 = __p0; \
	45264	float16x8_t __s1 = __p1; \
	45265	float16_t __s2 = __p2; \
	45266	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	45267	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
	45268	__ret = __noswap_vfmaq_f16(__rev0, -__rev1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	45269	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
	45270	__ret; \
	45271	})
	45272	#endif
	45273
	45274	#ifdef __LITTLE_ENDIAN__
	45275	#define vfms_n_f16(__p0, __p1, __p2) __extension__ ({ \
	45276	float16x4_t __ret; \
	45277	float16x4_t __s0 = __p0; \
	45278	float16x4_t __s1 = __p1; \
	45279	float16_t __s2 = __p2; \
	45280	__ret = vfma_f16(__s0, -__s1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
	45281	__ret; \
	45282	})
	45283	#else
	45284	#define vfms_n_f16(__p0, __p1, __p2) __extension__ ({ \
	45285	float16x4_t __ret; \
	45286	float16x4_t __s0 = __p0; \
	45287	float16x4_t __s1 = __p1; \
	45288	float16_t __s2 = __p2; \
	45289	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	45290	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	45291	__ret = __noswap_vfma_f16(__rev0, -__rev1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
	45292	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
	45293	__ret; \
	45294	})
	45295	#endif
	45296
	45297	#ifdef __LITTLE_ENDIAN__
	45298	#define vmaxnmvq_f16(__p0) __extension__ ({ \
	45299	float16_t __ret; \
	45300	float16x8_t __s0 = __p0; \
	45301	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
	45302	__ret; \
	45303	})
	45304	#else
	45305	#define vmaxnmvq_f16(__p0) __extension__ ({ \
	45306	float16_t __ret; \
	45307	float16x8_t __s0 = __p0; \
	45308	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	45309	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
	45310	__ret; \
	45311	})
	45312	#endif
	45313
	45314	#ifdef __LITTLE_ENDIAN__
	45315	#define vmaxnmv_f16(__p0) __extension__ ({ \
	45316	float16_t __ret; \
	45317	float16x4_t __s0 = __p0; \
	45318	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
	45319	__ret; \
	45320	})
	45321	#else
	45322	#define vmaxnmv_f16(__p0) __extension__ ({ \
	45323	float16_t __ret; \
	45324	float16x4_t __s0 = __p0; \
	45325	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	45326	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
	45327	__ret; \
	45328	})
	45329	#endif
	45330
	45331	#ifdef __LITTLE_ENDIAN__
	45332	#define vmaxvq_f16(__p0) __extension__ ({ \
	45333	float16_t __ret; \
	45334	float16x8_t __s0 = __p0; \
	45335	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
	45336	__ret; \
	45337	})
	45338	#else
	45339	#define vmaxvq_f16(__p0) __extension__ ({ \
	45340	float16_t __ret; \
	45341	float16x8_t __s0 = __p0; \
	45342	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	45343	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
	45344	__ret; \
	45345	})
	45346	#endif
	45347
	45348	#ifdef __LITTLE_ENDIAN__
	45349	#define vmaxv_f16(__p0) __extension__ ({ \
	45350	float16_t __ret; \
	45351	float16x4_t __s0 = __p0; \
	45352	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
	45353	__ret; \
	45354	})
	45355	#else
	45356	#define vmaxv_f16(__p0) __extension__ ({ \
	45357	float16_t __ret; \
	45358	float16x4_t __s0 = __p0; \
	45359	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	45360	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
	45361	__ret; \
	45362	})
	45363	#endif
	45364
	45365	#ifdef __LITTLE_ENDIAN__
	45366	#define vminnmvq_f16(__p0) __extension__ ({ \
	45367	float16_t __ret; \
	45368	float16x8_t __s0 = __p0; \
	45369	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
	45370	__ret; \
	45371	})
	45372	#else
	45373	#define vminnmvq_f16(__p0) __extension__ ({ \
	45374	float16_t __ret; \
	45375	float16x8_t __s0 = __p0; \
	45376	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	45377	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
	45378	__ret; \
	45379	})
	45380	#endif
	45381
	45382	#ifdef __LITTLE_ENDIAN__
	45383	#define vminnmv_f16(__p0) __extension__ ({ \
	45384	float16_t __ret; \
	45385	float16x4_t __s0 = __p0; \
	45386	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
	45387	__ret; \
	45388	})
	45389	#else
	45390	#define vminnmv_f16(__p0) __extension__ ({ \
	45391	float16_t __ret; \
	45392	float16x4_t __s0 = __p0; \
	45393	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	45394	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
	45395	__ret; \
	45396	})
	45397	#endif
	45398
	45399	#ifdef __LITTLE_ENDIAN__
	45400	#define vminvq_f16(__p0) __extension__ ({ \
	45401	float16_t __ret; \
	45402	float16x8_t __s0 = __p0; \
	45403	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
	45404	__ret; \
	45405	})
	45406	#else
	45407	#define vminvq_f16(__p0) __extension__ ({ \
	45408	float16_t __ret; \
	45409	float16x8_t __s0 = __p0; \
	45410	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
	45411	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
	45412	__ret; \
	45413	})
	45414	#endif
	45415
	45416	#ifdef __LITTLE_ENDIAN__
	45417	#define vminv_f16(__p0) __extension__ ({ \
	45418	float16_t __ret; \
	45419	float16x4_t __s0 = __p0; \
	45420	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
	45421	__ret; \
	45422	})
	45423	#else
	45424	#define vminv_f16(__p0) __extension__ ({ \
	45425	float16_t __ret; \
	45426	float16x4_t __s0 = __p0; \
	45427	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
	45428	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
	45429	__ret; \
	45430	})
	45431	#endif
	45432
	45433	#ifdef __LITTLE_ENDIAN__
	45434	#define vmulq_laneq_f16(__p0_254, __p1_254, __p2_254) __extension__ ({ \
	45435	float16x8_t __ret_254; \
	45436	float16x8_t __s0_254 = __p0_254; \
	45437	float16x8_t __s1_254 = __p1_254; \
	45438	__ret_254 = __s0_254 * splatq_laneq_f16(__s1_254, __p2_254); \
45371	45439	__ret_254; \
45372	45440	})
45373	45441	#else
45374		#define vfms_lane_f16(__p0_255, __p1_255, __p2_255, __p3_255) __extension__ ({ \
45375		float16x4_t __ret_255; \
45376		float16x4_t __s0_255 = __p0_255; \
45377		float16x4_t __s1_255 = __p1_255; \
45378		float16x4_t __s2_255 = __p2_255; \
45379		float16x4_t __rev0_255; __rev0_255 = __builtin_shufflevector(__s0_255, __s0_255, __lane_reverse_64_16); \
45380		float16x4_t __rev1_255; __rev1_255 = __builtin_shufflevector(__s1_255, __s1_255, __lane_reverse_64_16); \
45381		float16x4_t __rev2_255; __rev2_255 = __builtin_shufflevector(__s2_255, __s2_255, __lane_reverse_64_16); \
45382		__ret_255 = __noswap_vfma_lane_f16(__rev0_255, -__rev1_255, __rev2_255, __p3_255); \
45383		__ret_255 = __builtin_shufflevector(__ret_255, __ret_255, __lane_reverse_64_16); \
	45442	#define vmulq_laneq_f16(__p0_255, __p1_255, __p2_255) __extension__ ({ \
	45443	float16x8_t __ret_255; \
	45444	float16x8_t __s0_255 = __p0_255; \
	45445	float16x8_t __s1_255 = __p1_255; \
	45446	float16x8_t __rev0_255; __rev0_255 = __builtin_shufflevector(__s0_255, __s0_255, __lane_reverse_128_16); \
	45447	float16x8_t __rev1_255; __rev1_255 = __builtin_shufflevector(__s1_255, __s1_255, __lane_reverse_128_16); \
	45448	__ret_255 = __rev0_255 * __noswap_splatq_laneq_f16(__rev1_255, __p2_255); \
	45449	__ret_255 = __builtin_shufflevector(__ret_255, __ret_255, __lane_reverse_128_16); \
45384	45450	__ret_255; \
45385	45451	})
45386	45452	#endif
45387	45453
45388	45454	#ifdef __LITTLE_ENDIAN__
45389		#define vfmsh_laneq_f16(__p0_256, __p1_256, __p2_256, __p3_256) __extension__ ({ \
45390		float16_t __ret_256; \
45391		float16_t __s0_256 = __p0_256; \
45392		float16_t __s1_256 = __p1_256; \
45393		float16x8_t __s2_256 = __p2_256; \
45394		__ret_256 = vfmah_laneq_f16(__s0_256, -__s1_256, __s2_256, __p3_256); \
	45455	#define vmul_laneq_f16(__p0_256, __p1_256, __p2_256) __extension__ ({ \
	45456	float16x4_t __ret_256; \
	45457	float16x4_t __s0_256 = __p0_256; \
	45458	float16x8_t __s1_256 = __p1_256; \
	45459	__ret_256 = __s0_256 * splat_laneq_f16(__s1_256, __p2_256); \
45395	45460	__ret_256; \
45396	45461	})
45397	45462	#else
45398		#define vfmsh_laneq_f16(__p0_257, __p1_257, __p2_257, __p3_257) __extension__ ({ \
45399		float16_t __ret_257; \
45400		float16_t __s0_257 = __p0_257; \
45401		float16_t __s1_257 = __p1_257; \
45402		float16x8_t __s2_257 = __p2_257; \
45403		float16x8_t __rev2_257; __rev2_257 = __builtin_shufflevector(__s2_257, __s2_257, __lane_reverse_128_16); \
45404		__ret_257 = __noswap_vfmah_laneq_f16(__s0_257, -__s1_257, __rev2_257, __p3_257); \
	45463	#define vmul_laneq_f16(__p0_257, __p1_257, __p2_257) __extension__ ({ \
	45464	float16x4_t __ret_257; \
	45465	float16x4_t __s0_257 = __p0_257; \
	45466	float16x8_t __s1_257 = __p1_257; \
	45467	float16x4_t __rev0_257; __rev0_257 = __builtin_shufflevector(__s0_257, __s0_257, __lane_reverse_64_16); \
	45468	float16x8_t __rev1_257; __rev1_257 = __builtin_shufflevector(__s1_257, __s1_257, __lane_reverse_128_16); \
	45469	__ret_257 = __rev0_257 * __noswap_splat_laneq_f16(__rev1_257, __p2_257); \
	45470	__ret_257 = __builtin_shufflevector(__ret_257, __ret_257, __lane_reverse_64_16); \
45405	45471	__ret_257; \
45406	45472	})
45407	45473	#endif
45408	45474
45409	45475	#ifdef __LITTLE_ENDIAN__
45410		#define vfmsq_laneq_f16(__p0_258, __p1_258, __p2_258, __p3_258) __extension__ ({ \
	45476	__ai __attribute__((target("fullfp16,neon"))) float16x8_t vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
	45477	float16x8_t __ret;
	45478	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmulxq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
	45479	return __ret;
	45480	}
	45481	#else
	45482	__ai __attribute__((target("fullfp16,neon"))) float16x8_t vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
	45483	float16x8_t __ret;
	45484	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
	45485	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
	45486	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmulxq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 40));
	45487	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
	45488	return __ret;
	45489	}
	45490	__ai __attribute__((target("fullfp16,neon"))) float16x8_t __noswap_vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
	45491	float16x8_t __ret;
	45492	__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmulxq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
	45493	return __ret;
	45494	}
	45495	#endif
	45496
	45497	#ifdef __LITTLE_ENDIAN__
	45498	__ai __attribute__((target("fullfp16,neon"))) float16x4_t vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
	45499	float16x4_t __ret;
	45500	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vmulx_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
	45501	return __ret;
	45502	}
	45503	#else
	45504	__ai __attribute__((target("fullfp16,neon"))) float16x4_t vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
	45505	float16x4_t __ret;
	45506	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
	45507	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
	45508	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vmulx_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 8));
	45509	__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
	45510	return __ret;
	45511	}
	45512	__ai __attribute__((target("fullfp16,neon"))) float16x4_t __noswap_vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
	45513	float16x4_t __ret;
	45514	__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vmulx_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
	45515	return __ret;
	45516	}
	45517	#endif
	45518
	45519	#ifdef __LITTLE_ENDIAN__
	45520	#define vmulxh_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	45521	float16_t __ret; \
	45522	float16_t __s0 = __p0; \
	45523	float16x4_t __s1 = __p1; \
	45524	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_lane_f16(__s0, __s1, __p2)); \
	45525	__ret; \
	45526	})
	45527	#else
	45528	#define vmulxh_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	45529	float16_t __ret; \
	45530	float16_t __s0 = __p0; \
	45531	float16x4_t __s1 = __p1; \
	45532	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
	45533	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_lane_f16(__s0, __rev1, __p2)); \
	45534	__ret; \
	45535	})
	45536	#endif
	45537
	45538	#ifdef __LITTLE_ENDIAN__
	45539	#define vmulxq_lane_f16(__p0_258, __p1_258, __p2_258) __extension__ ({ \
45411	45540	float16x8_t __ret_258; \
45412	45541	float16x8_t __s0_258 = __p0_258; \
45413		float16x8_t __s1_258 = __p1_258; \
45414		float16x8_t __s2_258 = __p2_258; \
45415		__ret_258 = vfmaq_laneq_f16(__s0_258, -__s1_258, __s2_258, __p3_258); \
	45542	float16x4_t __s1_258 = __p1_258; \
	45543	__ret_258 = vmulxq_f16(__s0_258, splatq_lane_f16(__s1_258, __p2_258)); \
45416	45544	__ret_258; \
45417	45545	})
45418	45546	#else
45419		#define vfmsq_laneq_f16(__p0_259, __p1_259, __p2_259, __p3_259) __extension__ ({ \
	45547	#define vmulxq_lane_f16(__p0_259, __p1_259, __p2_259) __extension__ ({ \
45420	45548	float16x8_t __ret_259; \
45421	45549	float16x8_t __s0_259 = __p0_259; \
45422		float16x8_t __s1_259 = __p1_259; \
45423		float16x8_t __s2_259 = __p2_259; \
	45550	float16x4_t __s1_259 = __p1_259; \
45424	45551	float16x8_t __rev0_259; __rev0_259 = __builtin_shufflevector(__s0_259, __s0_259, __lane_reverse_128_16); \
45425		float16x8_t __rev1_259; __rev1_259 = __builtin_shufflevector(__s1_259, __s1_259, __lane_reverse_128_16); \
45426		float16x8_t __rev2_259; __rev2_259 = __builtin_shufflevector(__s2_259, __s2_259, __lane_reverse_128_16); \
45427		__ret_259 = __noswap_vfmaq_laneq_f16(__rev0_259, -__rev1_259, __rev2_259, __p3_259); \
	45552	float16x4_t __rev1_259; __rev1_259 = __builtin_shufflevector(__s1_259, __s1_259, __lane_reverse_64_16); \
	45553	__ret_259 = __noswap_vmulxq_f16(__rev0_259, __noswap_splatq_lane_f16(__rev1_259, __p2_259)); \
45428	45554	__ret_259 = __builtin_shufflevector(__ret_259, __ret_259, __lane_reverse_128_16); \
45429	45555	__ret_259; \
45430	45556	})
45431	45557	#endif
45432	45558
45433	45559	#ifdef __LITTLE_ENDIAN__
45434		#define vfms_laneq_f16(__p0_260, __p1_260, __p2_260, __p3_260) __extension__ ({ \
	45560	#define vmulx_lane_f16(__p0_260, __p1_260, __p2_260) __extension__ ({ \
45435	45561	float16x4_t __ret_260; \
45436	45562	float16x4_t __s0_260 = __p0_260; \
45437	45563	float16x4_t __s1_260 = __p1_260; \
45438		float16x8_t __s2_260 = __p2_260; \
45439		__ret_260 = vfma_laneq_f16(__s0_260, -__s1_260, __s2_260, __p3_260); \
	45564	__ret_260 = vmulx_f16(__s0_260, splat_lane_f16(__s1_260, __p2_260)); \
45440	45565	__ret_260; \
45441	45566	})
45442	45567	#else
45443		#define vfms_laneq_f16(__p0_261, __p1_261, __p2_261, __p3_261) __extension__ ({ \
	45568	#define vmulx_lane_f16(__p0_261, __p1_261, __p2_261) __extension__ ({ \
45444	45569	float16x4_t __ret_261; \
45445	45570	float16x4_t __s0_261 = __p0_261; \
45446	45571	float16x4_t __s1_261 = __p1_261; \
45447		float16x8_t __s2_261 = __p2_261; \
45448	45572	float16x4_t __rev0_261; __rev0_261 = __builtin_shufflevector(__s0_261, __s0_261, __lane_reverse_64_16); \
45449	45573	float16x4_t __rev1_261; __rev1_261 = __builtin_shufflevector(__s1_261, __s1_261, __lane_reverse_64_16); \
45450		float16x8_t __rev2_261; __rev2_261 = __builtin_shufflevector(__s2_261, __s2_261, __lane_reverse_128_16); \
45451		__ret_261 = __noswap_vfma_laneq_f16(__rev0_261, -__rev1_261, __rev2_261, __p3_261); \
	45574	__ret_261 = __noswap_vmulx_f16(__rev0_261, __noswap_splat_lane_f16(__rev1_261, __p2_261)); \
45452	45575	__ret_261 = __builtin_shufflevector(__ret_261, __ret_261, __lane_reverse_64_16); \
45453	45576	__ret_261; \
45454	45577	})
45455	45578	#endif
45456	45579
45457	45580	#ifdef __LITTLE_ENDIAN__
45458		#define vfmsq_n_f16(__p0, __p1, __p2) __extension__ ({ \
45459		float16x8_t __ret; \
45460		float16x8_t __s0 = __p0; \
	45581	#define vmulxh_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	45582	float16_t __ret; \
	45583	float16_t __s0 = __p0; \
45461	45584	float16x8_t __s1 = __p1; \
45462		float16_t __s2 = __p2; \
45463		__ret = vfmaq_f16(__s0, -__s1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	45585	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_laneq_f16(__s0, __s1, __p2)); \
45464	45586	__ret; \
45465	45587	})
45466	45588	#else
45467		#define vfmsq_n_f16(__p0, __p1, __p2) __extension__ ({ \
45468		float16x8_t __ret; \
45469		float16x8_t __s0 = __p0; \
	45589	#define vmulxh_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	45590	float16_t __ret; \
	45591	float16_t __s0 = __p0; \
45470	45592	float16x8_t __s1 = __p1; \
45471		float16_t __s2 = __p2; \
45472		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
45473	45593	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
45474		__ret = __noswap_vfmaq_f16(__rev0, -__rev1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
45475		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16); \
45476		__ret; \
45477		})
45478		#endif
45479
45480		#ifdef __LITTLE_ENDIAN__
45481		#define vfms_n_f16(__p0, __p1, __p2) __extension__ ({ \
45482		float16x4_t __ret; \
45483		float16x4_t __s0 = __p0; \
45484		float16x4_t __s1 = __p1; \
45485		float16_t __s2 = __p2; \
45486		__ret = vfma_f16(__s0, -__s1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
45487		__ret; \
45488		})
45489		#else
45490		#define vfms_n_f16(__p0, __p1, __p2) __extension__ ({ \
45491		float16x4_t __ret; \
45492		float16x4_t __s0 = __p0; \
45493		float16x4_t __s1 = __p1; \
45494		float16_t __s2 = __p2; \
45495		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
45496		float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
45497		__ret = __noswap_vfma_f16(__rev0, -__rev1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
45498		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16); \
45499		__ret; \
45500		})
45501		#endif
45502
45503		#ifdef __LITTLE_ENDIAN__
45504		#define vmaxnmvq_f16(__p0) __extension__ ({ \
45505		float16_t __ret; \
45506		float16x8_t __s0 = __p0; \
45507		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
45508		__ret; \
45509		})
45510		#else
45511		#define vmaxnmvq_f16(__p0) __extension__ ({ \
45512		float16_t __ret; \
45513		float16x8_t __s0 = __p0; \
45514		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
45515		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
45516		__ret; \
45517		})
45518		#endif
45519
45520		#ifdef __LITTLE_ENDIAN__
45521		#define vmaxnmv_f16(__p0) __extension__ ({ \
45522		float16_t __ret; \
45523		float16x4_t __s0 = __p0; \
45524		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
45525		__ret; \
45526		})
45527		#else
45528		#define vmaxnmv_f16(__p0) __extension__ ({ \
45529		float16_t __ret; \
45530		float16x4_t __s0 = __p0; \
45531		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
45532		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxnmv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
45533		__ret; \
45534		})
45535		#endif
45536
45537		#ifdef __LITTLE_ENDIAN__
45538		#define vmaxvq_f16(__p0) __extension__ ({ \
45539		float16_t __ret; \
45540		float16x8_t __s0 = __p0; \
45541		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
45542		__ret; \
45543		})
45544		#else
45545		#define vmaxvq_f16(__p0) __extension__ ({ \
45546		float16_t __ret; \
45547		float16x8_t __s0 = __p0; \
45548		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
45549		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
45550		__ret; \
45551		})
45552		#endif
45553
45554		#ifdef __LITTLE_ENDIAN__
45555		#define vmaxv_f16(__p0) __extension__ ({ \
45556		float16_t __ret; \
45557		float16x4_t __s0 = __p0; \
45558		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
45559		__ret; \
45560		})
45561		#else
45562		#define vmaxv_f16(__p0) __extension__ ({ \
45563		float16_t __ret; \
45564		float16x4_t __s0 = __p0; \
45565		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
45566		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmaxv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
45567		__ret; \
45568		})
45569		#endif
45570
45571		#ifdef __LITTLE_ENDIAN__
45572		#define vminnmvq_f16(__p0) __extension__ ({ \
45573		float16_t __ret; \
45574		float16x8_t __s0 = __p0; \
45575		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
45576		__ret; \
45577		})
45578		#else
45579		#define vminnmvq_f16(__p0) __extension__ ({ \
45580		float16_t __ret; \
45581		float16x8_t __s0 = __p0; \
45582		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
45583		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
45584		__ret; \
45585		})
45586		#endif
45587
45588		#ifdef __LITTLE_ENDIAN__
45589		#define vminnmv_f16(__p0) __extension__ ({ \
45590		float16_t __ret; \
45591		float16x4_t __s0 = __p0; \
45592		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
45593		__ret; \
45594		})
45595		#else
45596		#define vminnmv_f16(__p0) __extension__ ({ \
45597		float16_t __ret; \
45598		float16x4_t __s0 = __p0; \
45599		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
45600		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminnmv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
45601		__ret; \
45602		})
45603		#endif
45604
45605		#ifdef __LITTLE_ENDIAN__
45606		#define vminvq_f16(__p0) __extension__ ({ \
45607		float16_t __ret; \
45608		float16x8_t __s0 = __p0; \
45609		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminvq_f16(__builtin_bit_cast(int8x16_t, __s0))); \
45610		__ret; \
45611		})
45612		#else
45613		#define vminvq_f16(__p0) __extension__ ({ \
45614		float16_t __ret; \
45615		float16x8_t __s0 = __p0; \
45616		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_128_16); \
45617		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminvq_f16(__builtin_bit_cast(int8x16_t, __rev0))); \
45618		__ret; \
45619		})
45620		#endif
45621
45622		#ifdef __LITTLE_ENDIAN__
45623		#define vminv_f16(__p0) __extension__ ({ \
45624		float16_t __ret; \
45625		float16x4_t __s0 = __p0; \
45626		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminv_f16(__builtin_bit_cast(int8x8_t, __s0))); \
45627		__ret; \
45628		})
45629		#else
45630		#define vminv_f16(__p0) __extension__ ({ \
45631		float16_t __ret; \
45632		float16x4_t __s0 = __p0; \
45633		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, __lane_reverse_64_16); \
45634		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vminv_f16(__builtin_bit_cast(int8x8_t, __rev0))); \
	45594	__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_laneq_f16(__s0, __rev1, __p2)); \
45635	45595	__ret; \
45636	45596	})
45637	45597	#endif
45638	45598
45639	45599	#ifdef __LITTLE_ENDIAN__
45640		#define vmulq_laneq_f16(__p0_262, __p1_262, __p2_262) __extension__ ({ \
	45600	#define vmulxq_laneq_f16(__p0_262, __p1_262, __p2_262) __extension__ ({ \
45641	45601	float16x8_t __ret_262; \
45642	45602	float16x8_t __s0_262 = __p0_262; \
45643	45603	float16x8_t __s1_262 = __p1_262; \
45644		__ret_262 = __s0_262 * splatq_laneq_f16(__s1_262, __p2_262); \
	45604	__ret_262 = vmulxq_f16(__s0_262, splatq_laneq_f16(__s1_262, __p2_262)); \
45645	45605	__ret_262; \
45646	45606	})
45647	45607	#else
45648		#define vmulq_laneq_f16(__p0_263, __p1_263, __p2_263) __extension__ ({ \
	45608	#define vmulxq_laneq_f16(__p0_263, __p1_263, __p2_263) __extension__ ({ \
45649	45609	float16x8_t __ret_263; \
45650	45610	float16x8_t __s0_263 = __p0_263; \
45651	45611	float16x8_t __s1_263 = __p1_263; \
45652	45612	float16x8_t __rev0_263; __rev0_263 = __builtin_shufflevector(__s0_263, __s0_263, __lane_reverse_128_16); \
45653	45613	float16x8_t __rev1_263; __rev1_263 = __builtin_shufflevector(__s1_263, __s1_263, __lane_reverse_128_16); \
45654		__ret_263 = __rev0_263 * __noswap_splatq_laneq_f16(__rev1_263, __p2_263); \
	45614	__ret_263 = __noswap_vmulxq_f16(__rev0_263, __noswap_splatq_laneq_f16(__rev1_263, __p2_263)); \
45655	45615	__ret_263 = __builtin_shufflevector(__ret_263, __ret_263, __lane_reverse_128_16); \
45656	45616	__ret_263; \
45657	45617	})
45658	45618	#endif
45659	45619
45660	45620	#ifdef __LITTLE_ENDIAN__
45661		#define vmul_laneq_f16(__p0_264, __p1_264, __p2_264) __extension__ ({ \
	45621	#define vmulx_laneq_f16(__p0_264, __p1_264, __p2_264) __extension__ ({ \
45662	45622	float16x4_t __ret_264; \
45663	45623	float16x4_t __s0_264 = __p0_264; \
45664	45624	float16x8_t __s1_264 = __p1_264; \
45665		__ret_264 = __s0_264 * splat_laneq_f16(__s1_264, __p2_264); \
	45625	__ret_264 = vmulx_f16(__s0_264, splat_laneq_f16(__s1_264, __p2_264)); \
45666	45626	__ret_264; \
45667	45627	})
45668	45628	#else
45669		#define vmul_laneq_f16(__p0_265, __p1_265, __p2_265) __extension__ ({ \
	45629	#define vmulx_laneq_f16(__p0_265, __p1_265, __p2_265) __extension__ ({ \
45670	45630	float16x4_t __ret_265; \
45671	45631	float16x4_t __s0_265 = __p0_265; \
45672	45632	float16x8_t __s1_265 = __p1_265; \
45673	45633	float16x4_t __rev0_265; __rev0_265 = __builtin_shufflevector(__s0_265, __s0_265, __lane_reverse_64_16); \
45674	45634	float16x8_t __rev1_265; __rev1_265 = __builtin_shufflevector(__s1_265, __s1_265, __lane_reverse_128_16); \
45675		__ret_265 = __rev0_265 * __noswap_splat_laneq_f16(__rev1_265, __p2_265); \
	45635	__ret_265 = __noswap_vmulx_f16(__rev0_265, __noswap_splat_laneq_f16(__rev1_265, __p2_265)); \
45676	45636	__ret_265 = __builtin_shufflevector(__ret_265, __ret_265, __lane_reverse_64_16); \
45677	45637	__ret_265; \
45678	45638	})
45679	45639	#endif
45680	45640
45681		#ifdef __LITTLE_ENDIAN__
45682		__ai __attribute__((target("fullfp16,neon"))) float16x8_t vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
45683		float16x8_t __ret;
45684		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmulxq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
45685		return __ret;
45686		}
45687		#else
45688		__ai __attribute__((target("fullfp16,neon"))) float16x8_t vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
45689		float16x8_t __ret;
45690		float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_128_16);
45691		float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_128_16);
45692		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmulxq_f16(__builtin_bit_cast(int8x16_t, __rev0), __builtin_bit_cast(int8x16_t, __rev1), 40));
45693		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_128_16);
45694		return __ret;
45695		}
45696		__ai __attribute__((target("fullfp16,neon"))) float16x8_t __noswap_vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
45697		float16x8_t __ret;
45698		__ret = __builtin_bit_cast(float16x8_t, __builtin_neon_vmulxq_f16(__builtin_bit_cast(int8x16_t, __p0), __builtin_bit_cast(int8x16_t, __p1), 40));
45699		return __ret;
45700		}
45701		#endif
45702
45703		#ifdef __LITTLE_ENDIAN__
45704		__ai __attribute__((target("fullfp16,neon"))) float16x4_t vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
45705		float16x4_t __ret;
45706		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vmulx_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
45707		return __ret;
45708		}
45709		#else
45710		__ai __attribute__((target("fullfp16,neon"))) float16x4_t vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
45711		float16x4_t __ret;
45712		float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, __lane_reverse_64_16);
45713		float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, __lane_reverse_64_16);
45714		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vmulx_f16(__builtin_bit_cast(int8x8_t, __rev0), __builtin_bit_cast(int8x8_t, __rev1), 8));
45715		__ret = __builtin_shufflevector(__ret, __ret, __lane_reverse_64_16);
45716		return __ret;
45717		}
45718		__ai __attribute__((target("fullfp16,neon"))) float16x4_t __noswap_vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
45719		float16x4_t __ret;
45720		__ret = __builtin_bit_cast(float16x4_t, __builtin_neon_vmulx_f16(__builtin_bit_cast(int8x8_t, __p0), __builtin_bit_cast(int8x8_t, __p1), 8));
45721		return __ret;
45722		}
45723		#endif
45724
45725		#ifdef __LITTLE_ENDIAN__
45726		#define vmulxh_lane_f16(__p0, __p1, __p2) __extension__ ({ \
45727		float16_t __ret; \
45728		float16_t __s0 = __p0; \
45729		float16x4_t __s1 = __p1; \
45730		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_lane_f16(__s0, __s1, __p2)); \
45731		__ret; \
45732		})
45733		#else
45734		#define vmulxh_lane_f16(__p0, __p1, __p2) __extension__ ({ \
45735		float16_t __ret; \
45736		float16_t __s0 = __p0; \
45737		float16x4_t __s1 = __p1; \
45738		float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_64_16); \
45739		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_lane_f16(__s0, __rev1, __p2)); \
45740		__ret; \
45741		})
45742		#endif
45743
45744		#ifdef __LITTLE_ENDIAN__
45745		#define vmulxq_lane_f16(__p0_266, __p1_266, __p2_266) __extension__ ({ \
45746		float16x8_t __ret_266; \
45747		float16x8_t __s0_266 = __p0_266; \
45748		float16x4_t __s1_266 = __p1_266; \
45749		__ret_266 = vmulxq_f16(__s0_266, splatq_lane_f16(__s1_266, __p2_266)); \
45750		__ret_266; \
45751		})
45752		#else
45753		#define vmulxq_lane_f16(__p0_267, __p1_267, __p2_267) __extension__ ({ \
45754		float16x8_t __ret_267; \
45755		float16x8_t __s0_267 = __p0_267; \
45756		float16x4_t __s1_267 = __p1_267; \
45757		float16x8_t __rev0_267; __rev0_267 = __builtin_shufflevector(__s0_267, __s0_267, __lane_reverse_128_16); \
45758		float16x4_t __rev1_267; __rev1_267 = __builtin_shufflevector(__s1_267, __s1_267, __lane_reverse_64_16); \
45759		__ret_267 = __noswap_vmulxq_f16(__rev0_267, __noswap_splatq_lane_f16(__rev1_267, __p2_267)); \
45760		__ret_267 = __builtin_shufflevector(__ret_267, __ret_267, __lane_reverse_128_16); \
45761		__ret_267; \
45762		})
45763		#endif
45764
45765		#ifdef __LITTLE_ENDIAN__
45766		#define vmulx_lane_f16(__p0_268, __p1_268, __p2_268) __extension__ ({ \
45767		float16x4_t __ret_268; \
45768		float16x4_t __s0_268 = __p0_268; \
45769		float16x4_t __s1_268 = __p1_268; \
45770		__ret_268 = vmulx_f16(__s0_268, splat_lane_f16(__s1_268, __p2_268)); \
45771		__ret_268; \
45772		})
45773		#else
45774		#define vmulx_lane_f16(__p0_269, __p1_269, __p2_269) __extension__ ({ \
45775		float16x4_t __ret_269; \
45776		float16x4_t __s0_269 = __p0_269; \
45777		float16x4_t __s1_269 = __p1_269; \
45778		float16x4_t __rev0_269; __rev0_269 = __builtin_shufflevector(__s0_269, __s0_269, __lane_reverse_64_16); \
45779		float16x4_t __rev1_269; __rev1_269 = __builtin_shufflevector(__s1_269, __s1_269, __lane_reverse_64_16); \
45780		__ret_269 = __noswap_vmulx_f16(__rev0_269, __noswap_splat_lane_f16(__rev1_269, __p2_269)); \
45781		__ret_269 = __builtin_shufflevector(__ret_269, __ret_269, __lane_reverse_64_16); \
45782		__ret_269; \
45783		})
45784		#endif
45785
45786		#ifdef __LITTLE_ENDIAN__
45787		#define vmulxh_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
45788		float16_t __ret; \
45789		float16_t __s0 = __p0; \
45790		float16x8_t __s1 = __p1; \
45791		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_laneq_f16(__s0, __s1, __p2)); \
45792		__ret; \
45793		})
45794		#else
45795		#define vmulxh_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
45796		float16_t __ret; \
45797		float16_t __s0 = __p0; \
45798		float16x8_t __s1 = __p1; \
45799		float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, __lane_reverse_128_16); \
45800		__ret = __builtin_bit_cast(float16_t, __builtin_neon_vmulxh_laneq_f16(__s0, __rev1, __p2)); \
45801		__ret; \
45802		})
45803		#endif
45804
45805		#ifdef __LITTLE_ENDIAN__
45806		#define vmulxq_laneq_f16(__p0_270, __p1_270, __p2_270) __extension__ ({ \
45807		float16x8_t __ret_270; \
45808		float16x8_t __s0_270 = __p0_270; \
45809		float16x8_t __s1_270 = __p1_270; \
45810		__ret_270 = vmulxq_f16(__s0_270, splatq_laneq_f16(__s1_270, __p2_270)); \
45811		__ret_270; \
45812		})
45813		#else
45814		#define vmulxq_laneq_f16(__p0_271, __p1_271, __p2_271) __extension__ ({ \
45815		float16x8_t __ret_271; \
45816		float16x8_t __s0_271 = __p0_271; \
45817		float16x8_t __s1_271 = __p1_271; \
45818		float16x8_t __rev0_271; __rev0_271 = __builtin_shufflevector(__s0_271, __s0_271, __lane_reverse_128_16); \
45819		float16x8_t __rev1_271; __rev1_271 = __builtin_shufflevector(__s1_271, __s1_271, __lane_reverse_128_16); \
45820		__ret_271 = __noswap_vmulxq_f16(__rev0_271, __noswap_splatq_laneq_f16(__rev1_271, __p2_271)); \
45821		__ret_271 = __builtin_shufflevector(__ret_271, __ret_271, __lane_reverse_128_16); \
45822		__ret_271; \
45823		})
45824		#endif
45825
45826		#ifdef __LITTLE_ENDIAN__
45827		#define vmulx_laneq_f16(__p0_272, __p1_272, __p2_272) __extension__ ({ \
45828		float16x4_t __ret_272; \
45829		float16x4_t __s0_272 = __p0_272; \
45830		float16x8_t __s1_272 = __p1_272; \
45831		__ret_272 = vmulx_f16(__s0_272, splat_laneq_f16(__s1_272, __p2_272)); \
45832		__ret_272; \
45833		})
45834		#else
45835		#define vmulx_laneq_f16(__p0_273, __p1_273, __p2_273) __extension__ ({ \
45836		float16x4_t __ret_273; \
45837		float16x4_t __s0_273 = __p0_273; \
45838		float16x8_t __s1_273 = __p1_273; \
45839		float16x4_t __rev0_273; __rev0_273 = __builtin_shufflevector(__s0_273, __s0_273, __lane_reverse_64_16); \
45840		float16x8_t __rev1_273; __rev1_273 = __builtin_shufflevector(__s1_273, __s1_273, __lane_reverse_128_16); \
45841		__ret_273 = __noswap_vmulx_f16(__rev0_273, __noswap_splat_laneq_f16(__rev1_273, __p2_273)); \
45842		__ret_273 = __builtin_shufflevector(__ret_273, __ret_273, __lane_reverse_64_16); \
45843		__ret_273; \
45844		})
45845		#endif
45846
45847	45641	#ifdef __LITTLE_ENDIAN__
45848	45642	#define vmulxq_n_f16(__p0, __p1) __extension__ ({ \
45849	45643	float16x8_t __ret; \
...	...	@@ -46068,98 +45862,98 @@ __ai __attribute__((target("fullfp16,neon"))) float16x4_t vsqrt_f16(float16x4_t
46068	45862	#endif
46069	45863
46070	45864	#ifdef __LITTLE_ENDIAN__
46071		#define vsudotq_laneq_s32(__p0_274, __p1_274, __p2_274, __p3_274) __extension__ ({ \
46072		int32x4_t __ret_274; \
46073		int32x4_t __s0_274 = __p0_274; \
46074		int8x16_t __s1_274 = __p1_274; \
46075		uint8x16_t __s2_274 = __p2_274; \
46076		__ret_274 = vusdotq_s32(__s0_274, __builtin_bit_cast(uint8x16_t, splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_274), __p3_274)), __s1_274); \
46077		__ret_274; \
	45865	#define vsudotq_laneq_s32(__p0_266, __p1_266, __p2_266, __p3_266) __extension__ ({ \
	45866	int32x4_t __ret_266; \
	45867	int32x4_t __s0_266 = __p0_266; \
	45868	int8x16_t __s1_266 = __p1_266; \
	45869	uint8x16_t __s2_266 = __p2_266; \
	45870	__ret_266 = vusdotq_s32(__s0_266, __builtin_bit_cast(uint8x16_t, splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_266), __p3_266)), __s1_266); \
	45871	__ret_266; \
46078	45872	})
46079	45873	#else
46080		#define vsudotq_laneq_s32(__p0_275, __p1_275, __p2_275, __p3_275) __extension__ ({ \
46081		int32x4_t __ret_275; \
46082		int32x4_t __s0_275 = __p0_275; \
46083		int8x16_t __s1_275 = __p1_275; \
46084		uint8x16_t __s2_275 = __p2_275; \
46085		int32x4_t __rev0_275; __rev0_275 = __builtin_shufflevector(__s0_275, __s0_275, __lane_reverse_128_32); \
46086		int8x16_t __rev1_275; __rev1_275 = __builtin_shufflevector(__s1_275, __s1_275, __lane_reverse_128_8); \
46087		uint8x16_t __rev2_275; __rev2_275 = __builtin_shufflevector(__s2_275, __s2_275, __lane_reverse_128_8); \
46088		__ret_275 = __noswap_vusdotq_s32(__rev0_275, __builtin_bit_cast(uint8x16_t, __noswap_splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_275), __p3_275)), __rev1_275); \
46089		__ret_275 = __builtin_shufflevector(__ret_275, __ret_275, __lane_reverse_128_32); \
46090		__ret_275; \
	45874	#define vsudotq_laneq_s32(__p0_267, __p1_267, __p2_267, __p3_267) __extension__ ({ \
	45875	int32x4_t __ret_267; \
	45876	int32x4_t __s0_267 = __p0_267; \
	45877	int8x16_t __s1_267 = __p1_267; \
	45878	uint8x16_t __s2_267 = __p2_267; \
	45879	int32x4_t __rev0_267; __rev0_267 = __builtin_shufflevector(__s0_267, __s0_267, __lane_reverse_128_32); \
	45880	int8x16_t __rev1_267; __rev1_267 = __builtin_shufflevector(__s1_267, __s1_267, __lane_reverse_128_8); \
	45881	uint8x16_t __rev2_267; __rev2_267 = __builtin_shufflevector(__s2_267, __s2_267, __lane_reverse_128_8); \
	45882	__ret_267 = __noswap_vusdotq_s32(__rev0_267, __builtin_bit_cast(uint8x16_t, __noswap_splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_267), __p3_267)), __rev1_267); \
	45883	__ret_267 = __builtin_shufflevector(__ret_267, __ret_267, __lane_reverse_128_32); \
	45884	__ret_267; \
46091	45885	})
46092	45886	#endif
46093	45887
46094	45888	#ifdef __LITTLE_ENDIAN__
46095		#define vsudot_laneq_s32(__p0_276, __p1_276, __p2_276, __p3_276) __extension__ ({ \
46096		int32x2_t __ret_276; \
46097		int32x2_t __s0_276 = __p0_276; \
46098		int8x8_t __s1_276 = __p1_276; \
46099		uint8x16_t __s2_276 = __p2_276; \
46100		__ret_276 = vusdot_s32(__s0_276, __builtin_bit_cast(uint8x8_t, splat_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_276), __p3_276)), __s1_276); \
46101		__ret_276; \
	45889	#define vsudot_laneq_s32(__p0_268, __p1_268, __p2_268, __p3_268) __extension__ ({ \
	45890	int32x2_t __ret_268; \
	45891	int32x2_t __s0_268 = __p0_268; \
	45892	int8x8_t __s1_268 = __p1_268; \
	45893	uint8x16_t __s2_268 = __p2_268; \
	45894	__ret_268 = vusdot_s32(__s0_268, __builtin_bit_cast(uint8x8_t, splat_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_268), __p3_268)), __s1_268); \
	45895	__ret_268; \
46102	45896	})
46103	45897	#else
46104		#define vsudot_laneq_s32(__p0_277, __p1_277, __p2_277, __p3_277) __extension__ ({ \
46105		int32x2_t __ret_277; \
46106		int32x2_t __s0_277 = __p0_277; \
46107		int8x8_t __s1_277 = __p1_277; \
46108		uint8x16_t __s2_277 = __p2_277; \
46109		int32x2_t __rev0_277; __rev0_277 = __builtin_shufflevector(__s0_277, __s0_277, __lane_reverse_64_32); \
46110		int8x8_t __rev1_277; __rev1_277 = __builtin_shufflevector(__s1_277, __s1_277, __lane_reverse_64_8); \
46111		uint8x16_t __rev2_277; __rev2_277 = __builtin_shufflevector(__s2_277, __s2_277, __lane_reverse_128_8); \
46112		__ret_277 = __noswap_vusdot_s32(__rev0_277, __builtin_bit_cast(uint8x8_t, __noswap_splat_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_277), __p3_277)), __rev1_277); \
46113		__ret_277 = __builtin_shufflevector(__ret_277, __ret_277, __lane_reverse_64_32); \
46114		__ret_277; \
	45898	#define vsudot_laneq_s32(__p0_269, __p1_269, __p2_269, __p3_269) __extension__ ({ \
	45899	int32x2_t __ret_269; \
	45900	int32x2_t __s0_269 = __p0_269; \
	45901	int8x8_t __s1_269 = __p1_269; \
	45902	uint8x16_t __s2_269 = __p2_269; \
	45903	int32x2_t __rev0_269; __rev0_269 = __builtin_shufflevector(__s0_269, __s0_269, __lane_reverse_64_32); \
	45904	int8x8_t __rev1_269; __rev1_269 = __builtin_shufflevector(__s1_269, __s1_269, __lane_reverse_64_8); \
	45905	uint8x16_t __rev2_269; __rev2_269 = __builtin_shufflevector(__s2_269, __s2_269, __lane_reverse_128_8); \
	45906	__ret_269 = __noswap_vusdot_s32(__rev0_269, __builtin_bit_cast(uint8x8_t, __noswap_splat_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_269), __p3_269)), __rev1_269); \
	45907	__ret_269 = __builtin_shufflevector(__ret_269, __ret_269, __lane_reverse_64_32); \
	45908	__ret_269; \
46115	45909	})
46116	45910	#endif
46117	45911
46118	45912	#ifdef __LITTLE_ENDIAN__
46119		#define vusdotq_laneq_s32(__p0_278, __p1_278, __p2_278, __p3_278) __extension__ ({ \
46120		int32x4_t __ret_278; \
46121		int32x4_t __s0_278 = __p0_278; \
46122		uint8x16_t __s1_278 = __p1_278; \
46123		int8x16_t __s2_278 = __p2_278; \
46124		__ret_278 = vusdotq_s32(__s0_278, __s1_278, __builtin_bit_cast(int8x16_t, splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_278), __p3_278))); \
46125		__ret_278; \
	45913	#define vusdotq_laneq_s32(__p0_270, __p1_270, __p2_270, __p3_270) __extension__ ({ \
	45914	int32x4_t __ret_270; \
	45915	int32x4_t __s0_270 = __p0_270; \
	45916	uint8x16_t __s1_270 = __p1_270; \
	45917	int8x16_t __s2_270 = __p2_270; \
	45918	__ret_270 = vusdotq_s32(__s0_270, __s1_270, __builtin_bit_cast(int8x16_t, splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_270), __p3_270))); \
	45919	__ret_270; \
46126	45920	})
46127	45921	#else
46128		#define vusdotq_laneq_s32(__p0_279, __p1_279, __p2_279, __p3_279) __extension__ ({ \
46129		int32x4_t __ret_279; \
46130		int32x4_t __s0_279 = __p0_279; \
46131		uint8x16_t __s1_279 = __p1_279; \
46132		int8x16_t __s2_279 = __p2_279; \
46133		int32x4_t __rev0_279; __rev0_279 = __builtin_shufflevector(__s0_279, __s0_279, __lane_reverse_128_32); \
46134		uint8x16_t __rev1_279; __rev1_279 = __builtin_shufflevector(__s1_279, __s1_279, __lane_reverse_128_8); \
46135		int8x16_t __rev2_279; __rev2_279 = __builtin_shufflevector(__s2_279, __s2_279, __lane_reverse_128_8); \
46136		__ret_279 = __noswap_vusdotq_s32(__rev0_279, __rev1_279, __builtin_bit_cast(int8x16_t, __noswap_splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_279), __p3_279))); \
46137		__ret_279 = __builtin_shufflevector(__ret_279, __ret_279, __lane_reverse_128_32); \
46138		__ret_279; \
	45922	#define vusdotq_laneq_s32(__p0_271, __p1_271, __p2_271, __p3_271) __extension__ ({ \
	45923	int32x4_t __ret_271; \
	45924	int32x4_t __s0_271 = __p0_271; \
	45925	uint8x16_t __s1_271 = __p1_271; \
	45926	int8x16_t __s2_271 = __p2_271; \
	45927	int32x4_t __rev0_271; __rev0_271 = __builtin_shufflevector(__s0_271, __s0_271, __lane_reverse_128_32); \
	45928	uint8x16_t __rev1_271; __rev1_271 = __builtin_shufflevector(__s1_271, __s1_271, __lane_reverse_128_8); \
	45929	int8x16_t __rev2_271; __rev2_271 = __builtin_shufflevector(__s2_271, __s2_271, __lane_reverse_128_8); \
	45930	__ret_271 = __noswap_vusdotq_s32(__rev0_271, __rev1_271, __builtin_bit_cast(int8x16_t, __noswap_splatq_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_271), __p3_271))); \
	45931	__ret_271 = __builtin_shufflevector(__ret_271, __ret_271, __lane_reverse_128_32); \
	45932	__ret_271; \
46139	45933	})
46140	45934	#endif
46141	45935
46142	45936	#ifdef __LITTLE_ENDIAN__
46143		#define vusdot_laneq_s32(__p0_280, __p1_280, __p2_280, __p3_280) __extension__ ({ \
46144		int32x2_t __ret_280; \
46145		int32x2_t __s0_280 = __p0_280; \
46146		uint8x8_t __s1_280 = __p1_280; \
46147		int8x16_t __s2_280 = __p2_280; \
46148		__ret_280 = vusdot_s32(__s0_280, __s1_280, __builtin_bit_cast(int8x8_t, splat_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_280), __p3_280))); \
46149		__ret_280; \
	45937	#define vusdot_laneq_s32(__p0_272, __p1_272, __p2_272, __p3_272) __extension__ ({ \
	45938	int32x2_t __ret_272; \
	45939	int32x2_t __s0_272 = __p0_272; \
	45940	uint8x8_t __s1_272 = __p1_272; \
	45941	int8x16_t __s2_272 = __p2_272; \
	45942	__ret_272 = vusdot_s32(__s0_272, __s1_272, __builtin_bit_cast(int8x8_t, splat_laneq_s32(__builtin_bit_cast(int32x4_t, __s2_272), __p3_272))); \
	45943	__ret_272; \
46150	45944	})
46151	45945	#else
46152		#define vusdot_laneq_s32(__p0_281, __p1_281, __p2_281, __p3_281) __extension__ ({ \
46153		int32x2_t __ret_281; \
46154		int32x2_t __s0_281 = __p0_281; \
46155		uint8x8_t __s1_281 = __p1_281; \
46156		int8x16_t __s2_281 = __p2_281; \
46157		int32x2_t __rev0_281; __rev0_281 = __builtin_shufflevector(__s0_281, __s0_281, __lane_reverse_64_32); \
46158		uint8x8_t __rev1_281; __rev1_281 = __builtin_shufflevector(__s1_281, __s1_281, __lane_reverse_64_8); \
46159		int8x16_t __rev2_281; __rev2_281 = __builtin_shufflevector(__s2_281, __s2_281, __lane_reverse_128_8); \
46160		__ret_281 = __noswap_vusdot_s32(__rev0_281, __rev1_281, __builtin_bit_cast(int8x8_t, __noswap_splat_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_281), __p3_281))); \
46161		__ret_281 = __builtin_shufflevector(__ret_281, __ret_281, __lane_reverse_64_32); \
46162		__ret_281; \
	45946	#define vusdot_laneq_s32(__p0_273, __p1_273, __p2_273, __p3_273) __extension__ ({ \
	45947	int32x2_t __ret_273; \
	45948	int32x2_t __s0_273 = __p0_273; \
	45949	uint8x8_t __s1_273 = __p1_273; \
	45950	int8x16_t __s2_273 = __p2_273; \
	45951	int32x2_t __rev0_273; __rev0_273 = __builtin_shufflevector(__s0_273, __s0_273, __lane_reverse_64_32); \
	45952	uint8x8_t __rev1_273; __rev1_273 = __builtin_shufflevector(__s1_273, __s1_273, __lane_reverse_64_8); \
	45953	int8x16_t __rev2_273; __rev2_273 = __builtin_shufflevector(__s2_273, __s2_273, __lane_reverse_128_8); \
	45954	__ret_273 = __noswap_vusdot_s32(__rev0_273, __rev1_273, __builtin_bit_cast(int8x8_t, __noswap_splat_laneq_s32(__builtin_bit_cast(int32x4_t, __rev2_273), __p3_273))); \
	45955	__ret_273 = __builtin_shufflevector(__ret_273, __ret_273, __lane_reverse_64_32); \
	45956	__ret_273; \
46163	45957	})
46164	45958	#endif
46165	45959
...	...	@@ -48579,974 +48373,1058 @@ __ai __attribute__((target("neon"))) float64x2_t vcombine_f64(float64x1_t __p0,
48579	48373	#endif
48580	48374
48581	48375	#ifdef __LITTLE_ENDIAN__
48582		#define vcopyq_lane_p8(__p0_282, __p1_282, __p2_282, __p3_282) __extension__ ({ \
48583		poly8x16_t __ret_282; \
48584		poly8x16_t __s0_282 = __p0_282; \
48585		poly8x8_t __s2_282 = __p2_282; \
48586		__ret_282 = vsetq_lane_p8(vget_lane_p8(__s2_282, __p3_282), __s0_282, __p1_282); \
	48376	#define vcopyq_lane_p8(__p0_274, __p1_274, __p2_274, __p3_274) __extension__ ({ \
	48377	poly8x16_t __ret_274; \
	48378	poly8x16_t __s0_274 = __p0_274; \
	48379	poly8x8_t __s2_274 = __p2_274; \
	48380	__ret_274 = vsetq_lane_p8(vget_lane_p8(__s2_274, __p3_274), __s0_274, __p1_274); \
	48381	__ret_274; \
	48382	})
	48383	#else
	48384	#define vcopyq_lane_p8(__p0_275, __p1_275, __p2_275, __p3_275) __extension__ ({ \
	48385	poly8x16_t __ret_275; \
	48386	poly8x16_t __s0_275 = __p0_275; \
	48387	poly8x8_t __s2_275 = __p2_275; \
	48388	poly8x16_t __rev0_275; __rev0_275 = __builtin_shufflevector(__s0_275, __s0_275, __lane_reverse_128_8); \
	48389	poly8x8_t __rev2_275; __rev2_275 = __builtin_shufflevector(__s2_275, __s2_275, __lane_reverse_64_8); \
	48390	__ret_275 = __noswap_vsetq_lane_p8(__noswap_vget_lane_p8(__rev2_275, __p3_275), __rev0_275, __p1_275); \
	48391	__ret_275 = __builtin_shufflevector(__ret_275, __ret_275, __lane_reverse_128_8); \
	48392	__ret_275; \
	48393	})
	48394	#endif
	48395
	48396	#ifdef __LITTLE_ENDIAN__
	48397	#define vcopyq_lane_p16(__p0_276, __p1_276, __p2_276, __p3_276) __extension__ ({ \
	48398	poly16x8_t __ret_276; \
	48399	poly16x8_t __s0_276 = __p0_276; \
	48400	poly16x4_t __s2_276 = __p2_276; \
	48401	__ret_276 = vsetq_lane_p16(vget_lane_p16(__s2_276, __p3_276), __s0_276, __p1_276); \
	48402	__ret_276; \
	48403	})
	48404	#else
	48405	#define vcopyq_lane_p16(__p0_277, __p1_277, __p2_277, __p3_277) __extension__ ({ \
	48406	poly16x8_t __ret_277; \
	48407	poly16x8_t __s0_277 = __p0_277; \
	48408	poly16x4_t __s2_277 = __p2_277; \
	48409	poly16x8_t __rev0_277; __rev0_277 = __builtin_shufflevector(__s0_277, __s0_277, __lane_reverse_128_16); \
	48410	poly16x4_t __rev2_277; __rev2_277 = __builtin_shufflevector(__s2_277, __s2_277, __lane_reverse_64_16); \
	48411	__ret_277 = __noswap_vsetq_lane_p16(__noswap_vget_lane_p16(__rev2_277, __p3_277), __rev0_277, __p1_277); \
	48412	__ret_277 = __builtin_shufflevector(__ret_277, __ret_277, __lane_reverse_128_16); \
	48413	__ret_277; \
	48414	})
	48415	#endif
	48416
	48417	#ifdef __LITTLE_ENDIAN__
	48418	#define vcopyq_lane_u8(__p0_278, __p1_278, __p2_278, __p3_278) __extension__ ({ \
	48419	uint8x16_t __ret_278; \
	48420	uint8x16_t __s0_278 = __p0_278; \
	48421	uint8x8_t __s2_278 = __p2_278; \
	48422	__ret_278 = vsetq_lane_u8(vget_lane_u8(__s2_278, __p3_278), __s0_278, __p1_278); \
	48423	__ret_278; \
	48424	})
	48425	#else
	48426	#define vcopyq_lane_u8(__p0_279, __p1_279, __p2_279, __p3_279) __extension__ ({ \
	48427	uint8x16_t __ret_279; \
	48428	uint8x16_t __s0_279 = __p0_279; \
	48429	uint8x8_t __s2_279 = __p2_279; \
	48430	uint8x16_t __rev0_279; __rev0_279 = __builtin_shufflevector(__s0_279, __s0_279, __lane_reverse_128_8); \
	48431	uint8x8_t __rev2_279; __rev2_279 = __builtin_shufflevector(__s2_279, __s2_279, __lane_reverse_64_8); \
	48432	__ret_279 = __noswap_vsetq_lane_u8(__noswap_vget_lane_u8(__rev2_279, __p3_279), __rev0_279, __p1_279); \
	48433	__ret_279 = __builtin_shufflevector(__ret_279, __ret_279, __lane_reverse_128_8); \
	48434	__ret_279; \
	48435	})
	48436	#endif
	48437
	48438	#ifdef __LITTLE_ENDIAN__
	48439	#define vcopyq_lane_u32(__p0_280, __p1_280, __p2_280, __p3_280) __extension__ ({ \
	48440	uint32x4_t __ret_280; \
	48441	uint32x4_t __s0_280 = __p0_280; \
	48442	uint32x2_t __s2_280 = __p2_280; \
	48443	__ret_280 = vsetq_lane_u32(vget_lane_u32(__s2_280, __p3_280), __s0_280, __p1_280); \
	48444	__ret_280; \
	48445	})
	48446	#else
	48447	#define vcopyq_lane_u32(__p0_281, __p1_281, __p2_281, __p3_281) __extension__ ({ \
	48448	uint32x4_t __ret_281; \
	48449	uint32x4_t __s0_281 = __p0_281; \
	48450	uint32x2_t __s2_281 = __p2_281; \
	48451	uint32x4_t __rev0_281; __rev0_281 = __builtin_shufflevector(__s0_281, __s0_281, __lane_reverse_128_32); \
	48452	uint32x2_t __rev2_281; __rev2_281 = __builtin_shufflevector(__s2_281, __s2_281, __lane_reverse_64_32); \
	48453	__ret_281 = __noswap_vsetq_lane_u32(__noswap_vget_lane_u32(__rev2_281, __p3_281), __rev0_281, __p1_281); \
	48454	__ret_281 = __builtin_shufflevector(__ret_281, __ret_281, __lane_reverse_128_32); \
	48455	__ret_281; \
	48456	})
	48457	#endif
	48458
	48459	#ifdef __LITTLE_ENDIAN__
	48460	#define vcopyq_lane_u64(__p0_282, __p1_282, __p2_282, __p3_282) __extension__ ({ \
	48461	uint64x2_t __ret_282; \
	48462	uint64x2_t __s0_282 = __p0_282; \
	48463	uint64x1_t __s2_282 = __p2_282; \
	48464	__ret_282 = vsetq_lane_u64(vget_lane_u64(__s2_282, __p3_282), __s0_282, __p1_282); \
48587	48465	__ret_282; \
48588	48466	})
48589	48467	#else
48590		#define vcopyq_lane_p8(__p0_283, __p1_283, __p2_283, __p3_283) __extension__ ({ \
48591		poly8x16_t __ret_283; \
48592		poly8x16_t __s0_283 = __p0_283; \
48593		poly8x8_t __s2_283 = __p2_283; \
48594		poly8x16_t __rev0_283; __rev0_283 = __builtin_shufflevector(__s0_283, __s0_283, __lane_reverse_128_8); \
48595		poly8x8_t __rev2_283; __rev2_283 = __builtin_shufflevector(__s2_283, __s2_283, __lane_reverse_64_8); \
48596		__ret_283 = __noswap_vsetq_lane_p8(__noswap_vget_lane_p8(__rev2_283, __p3_283), __rev0_283, __p1_283); \
48597		__ret_283 = __builtin_shufflevector(__ret_283, __ret_283, __lane_reverse_128_8); \
	48468	#define vcopyq_lane_u64(__p0_283, __p1_283, __p2_283, __p3_283) __extension__ ({ \
	48469	uint64x2_t __ret_283; \
	48470	uint64x2_t __s0_283 = __p0_283; \
	48471	uint64x1_t __s2_283 = __p2_283; \
	48472	uint64x2_t __rev0_283; __rev0_283 = __builtin_shufflevector(__s0_283, __s0_283, __lane_reverse_128_64); \
	48473	__ret_283 = __noswap_vsetq_lane_u64(vget_lane_u64(__s2_283, __p3_283), __rev0_283, __p1_283); \
	48474	__ret_283 = __builtin_shufflevector(__ret_283, __ret_283, __lane_reverse_128_64); \
48598	48475	__ret_283; \
48599	48476	})
48600	48477	#endif
48601	48478
48602	48479	#ifdef __LITTLE_ENDIAN__
48603		#define vcopyq_lane_p16(__p0_284, __p1_284, __p2_284, __p3_284) __extension__ ({ \
48604		poly16x8_t __ret_284; \
48605		poly16x8_t __s0_284 = __p0_284; \
48606		poly16x4_t __s2_284 = __p2_284; \
48607		__ret_284 = vsetq_lane_p16(vget_lane_p16(__s2_284, __p3_284), __s0_284, __p1_284); \
	48480	#define vcopyq_lane_u16(__p0_284, __p1_284, __p2_284, __p3_284) __extension__ ({ \
	48481	uint16x8_t __ret_284; \
	48482	uint16x8_t __s0_284 = __p0_284; \
	48483	uint16x4_t __s2_284 = __p2_284; \
	48484	__ret_284 = vsetq_lane_u16(vget_lane_u16(__s2_284, __p3_284), __s0_284, __p1_284); \
48608	48485	__ret_284; \
48609	48486	})
48610	48487	#else
48611		#define vcopyq_lane_p16(__p0_285, __p1_285, __p2_285, __p3_285) __extension__ ({ \
48612		poly16x8_t __ret_285; \
48613		poly16x8_t __s0_285 = __p0_285; \
48614		poly16x4_t __s2_285 = __p2_285; \
48615		poly16x8_t __rev0_285; __rev0_285 = __builtin_shufflevector(__s0_285, __s0_285, __lane_reverse_128_16); \
48616		poly16x4_t __rev2_285; __rev2_285 = __builtin_shufflevector(__s2_285, __s2_285, __lane_reverse_64_16); \
48617		__ret_285 = __noswap_vsetq_lane_p16(__noswap_vget_lane_p16(__rev2_285, __p3_285), __rev0_285, __p1_285); \
	48488	#define vcopyq_lane_u16(__p0_285, __p1_285, __p2_285, __p3_285) __extension__ ({ \
	48489	uint16x8_t __ret_285; \
	48490	uint16x8_t __s0_285 = __p0_285; \
	48491	uint16x4_t __s2_285 = __p2_285; \
	48492	uint16x8_t __rev0_285; __rev0_285 = __builtin_shufflevector(__s0_285, __s0_285, __lane_reverse_128_16); \
	48493	uint16x4_t __rev2_285; __rev2_285 = __builtin_shufflevector(__s2_285, __s2_285, __lane_reverse_64_16); \
	48494	__ret_285 = __noswap_vsetq_lane_u16(__noswap_vget_lane_u16(__rev2_285, __p3_285), __rev0_285, __p1_285); \
48618	48495	__ret_285 = __builtin_shufflevector(__ret_285, __ret_285, __lane_reverse_128_16); \
48619	48496	__ret_285; \
48620	48497	})
48621	48498	#endif
48622	48499
48623	48500	#ifdef __LITTLE_ENDIAN__
48624		#define vcopyq_lane_u8(__p0_286, __p1_286, __p2_286, __p3_286) __extension__ ({ \
48625		uint8x16_t __ret_286; \
48626		uint8x16_t __s0_286 = __p0_286; \
48627		uint8x8_t __s2_286 = __p2_286; \
48628		__ret_286 = vsetq_lane_u8(vget_lane_u8(__s2_286, __p3_286), __s0_286, __p1_286); \
	48501	#define vcopyq_lane_s8(__p0_286, __p1_286, __p2_286, __p3_286) __extension__ ({ \
	48502	int8x16_t __ret_286; \
	48503	int8x16_t __s0_286 = __p0_286; \
	48504	int8x8_t __s2_286 = __p2_286; \
	48505	__ret_286 = vsetq_lane_s8(vget_lane_s8(__s2_286, __p3_286), __s0_286, __p1_286); \
48629	48506	__ret_286; \
48630	48507	})
48631	48508	#else
48632		#define vcopyq_lane_u8(__p0_287, __p1_287, __p2_287, __p3_287) __extension__ ({ \
48633		uint8x16_t __ret_287; \
48634		uint8x16_t __s0_287 = __p0_287; \
48635		uint8x8_t __s2_287 = __p2_287; \
48636		uint8x16_t __rev0_287; __rev0_287 = __builtin_shufflevector(__s0_287, __s0_287, __lane_reverse_128_8); \
48637		uint8x8_t __rev2_287; __rev2_287 = __builtin_shufflevector(__s2_287, __s2_287, __lane_reverse_64_8); \
48638		__ret_287 = __noswap_vsetq_lane_u8(__noswap_vget_lane_u8(__rev2_287, __p3_287), __rev0_287, __p1_287); \
	48509	#define vcopyq_lane_s8(__p0_287, __p1_287, __p2_287, __p3_287) __extension__ ({ \
	48510	int8x16_t __ret_287; \
	48511	int8x16_t __s0_287 = __p0_287; \
	48512	int8x8_t __s2_287 = __p2_287; \
	48513	int8x16_t __rev0_287; __rev0_287 = __builtin_shufflevector(__s0_287, __s0_287, __lane_reverse_128_8); \
	48514	int8x8_t __rev2_287; __rev2_287 = __builtin_shufflevector(__s2_287, __s2_287, __lane_reverse_64_8); \
	48515	__ret_287 = __noswap_vsetq_lane_s8(__noswap_vget_lane_s8(__rev2_287, __p3_287), __rev0_287, __p1_287); \
48639	48516	__ret_287 = __builtin_shufflevector(__ret_287, __ret_287, __lane_reverse_128_8); \
48640	48517	__ret_287; \
48641	48518	})
48642	48519	#endif
48643	48520
48644	48521	#ifdef __LITTLE_ENDIAN__
48645		#define vcopyq_lane_u32(__p0_288, __p1_288, __p2_288, __p3_288) __extension__ ({ \
48646		uint32x4_t __ret_288; \
48647		uint32x4_t __s0_288 = __p0_288; \
48648		uint32x2_t __s2_288 = __p2_288; \
48649		__ret_288 = vsetq_lane_u32(vget_lane_u32(__s2_288, __p3_288), __s0_288, __p1_288); \
	48522	#define vcopyq_lane_f32(__p0_288, __p1_288, __p2_288, __p3_288) __extension__ ({ \
	48523	float32x4_t __ret_288; \
	48524	float32x4_t __s0_288 = __p0_288; \
	48525	float32x2_t __s2_288 = __p2_288; \
	48526	__ret_288 = vsetq_lane_f32(vget_lane_f32(__s2_288, __p3_288), __s0_288, __p1_288); \
48650	48527	__ret_288; \
48651	48528	})
48652	48529	#else
48653		#define vcopyq_lane_u32(__p0_289, __p1_289, __p2_289, __p3_289) __extension__ ({ \
48654		uint32x4_t __ret_289; \
48655		uint32x4_t __s0_289 = __p0_289; \
48656		uint32x2_t __s2_289 = __p2_289; \
48657		uint32x4_t __rev0_289; __rev0_289 = __builtin_shufflevector(__s0_289, __s0_289, __lane_reverse_128_32); \
48658		uint32x2_t __rev2_289; __rev2_289 = __builtin_shufflevector(__s2_289, __s2_289, __lane_reverse_64_32); \
48659		__ret_289 = __noswap_vsetq_lane_u32(__noswap_vget_lane_u32(__rev2_289, __p3_289), __rev0_289, __p1_289); \
	48530	#define vcopyq_lane_f32(__p0_289, __p1_289, __p2_289, __p3_289) __extension__ ({ \
	48531	float32x4_t __ret_289; \
	48532	float32x4_t __s0_289 = __p0_289; \
	48533	float32x2_t __s2_289 = __p2_289; \
	48534	float32x4_t __rev0_289; __rev0_289 = __builtin_shufflevector(__s0_289, __s0_289, __lane_reverse_128_32); \
	48535	float32x2_t __rev2_289; __rev2_289 = __builtin_shufflevector(__s2_289, __s2_289, __lane_reverse_64_32); \
	48536	__ret_289 = __noswap_vsetq_lane_f32(__noswap_vget_lane_f32(__rev2_289, __p3_289), __rev0_289, __p1_289); \
48660	48537	__ret_289 = __builtin_shufflevector(__ret_289, __ret_289, __lane_reverse_128_32); \
48661	48538	__ret_289; \
48662	48539	})
48663	48540	#endif
48664	48541
48665	48542	#ifdef __LITTLE_ENDIAN__
48666		#define vcopyq_lane_u64(__p0_290, __p1_290, __p2_290, __p3_290) __extension__ ({ \
48667		uint64x2_t __ret_290; \
48668		uint64x2_t __s0_290 = __p0_290; \
48669		uint64x1_t __s2_290 = __p2_290; \
48670		__ret_290 = vsetq_lane_u64(vget_lane_u64(__s2_290, __p3_290), __s0_290, __p1_290); \
	48543	#define vcopyq_lane_s32(__p0_290, __p1_290, __p2_290, __p3_290) __extension__ ({ \
	48544	int32x4_t __ret_290; \
	48545	int32x4_t __s0_290 = __p0_290; \
	48546	int32x2_t __s2_290 = __p2_290; \
	48547	__ret_290 = vsetq_lane_s32(vget_lane_s32(__s2_290, __p3_290), __s0_290, __p1_290); \
48671	48548	__ret_290; \
48672	48549	})
48673	48550	#else
48674		#define vcopyq_lane_u64(__p0_291, __p1_291, __p2_291, __p3_291) __extension__ ({ \
48675		uint64x2_t __ret_291; \
48676		uint64x2_t __s0_291 = __p0_291; \
48677		uint64x1_t __s2_291 = __p2_291; \
48678		uint64x2_t __rev0_291; __rev0_291 = __builtin_shufflevector(__s0_291, __s0_291, __lane_reverse_128_64); \
48679		__ret_291 = __noswap_vsetq_lane_u64(vget_lane_u64(__s2_291, __p3_291), __rev0_291, __p1_291); \
48680		__ret_291 = __builtin_shufflevector(__ret_291, __ret_291, __lane_reverse_128_64); \
	48551	#define vcopyq_lane_s32(__p0_291, __p1_291, __p2_291, __p3_291) __extension__ ({ \
	48552	int32x4_t __ret_291; \
	48553	int32x4_t __s0_291 = __p0_291; \
	48554	int32x2_t __s2_291 = __p2_291; \
	48555	int32x4_t __rev0_291; __rev0_291 = __builtin_shufflevector(__s0_291, __s0_291, __lane_reverse_128_32); \
	48556	int32x2_t __rev2_291; __rev2_291 = __builtin_shufflevector(__s2_291, __s2_291, __lane_reverse_64_32); \
	48557	__ret_291 = __noswap_vsetq_lane_s32(__noswap_vget_lane_s32(__rev2_291, __p3_291), __rev0_291, __p1_291); \
	48558	__ret_291 = __builtin_shufflevector(__ret_291, __ret_291, __lane_reverse_128_32); \
48681	48559	__ret_291; \
48682	48560	})
48683	48561	#endif
48684	48562
48685	48563	#ifdef __LITTLE_ENDIAN__
48686		#define vcopyq_lane_u16(__p0_292, __p1_292, __p2_292, __p3_292) __extension__ ({ \
48687		uint16x8_t __ret_292; \
48688		uint16x8_t __s0_292 = __p0_292; \
48689		uint16x4_t __s2_292 = __p2_292; \
48690		__ret_292 = vsetq_lane_u16(vget_lane_u16(__s2_292, __p3_292), __s0_292, __p1_292); \
	48564	#define vcopyq_lane_s64(__p0_292, __p1_292, __p2_292, __p3_292) __extension__ ({ \
	48565	int64x2_t __ret_292; \
	48566	int64x2_t __s0_292 = __p0_292; \
	48567	int64x1_t __s2_292 = __p2_292; \
	48568	__ret_292 = vsetq_lane_s64(vget_lane_s64(__s2_292, __p3_292), __s0_292, __p1_292); \
48691	48569	__ret_292; \
48692	48570	})
48693	48571	#else
48694		#define vcopyq_lane_u16(__p0_293, __p1_293, __p2_293, __p3_293) __extension__ ({ \
48695		uint16x8_t __ret_293; \
48696		uint16x8_t __s0_293 = __p0_293; \
48697		uint16x4_t __s2_293 = __p2_293; \
48698		uint16x8_t __rev0_293; __rev0_293 = __builtin_shufflevector(__s0_293, __s0_293, __lane_reverse_128_16); \
48699		uint16x4_t __rev2_293; __rev2_293 = __builtin_shufflevector(__s2_293, __s2_293, __lane_reverse_64_16); \
48700		__ret_293 = __noswap_vsetq_lane_u16(__noswap_vget_lane_u16(__rev2_293, __p3_293), __rev0_293, __p1_293); \
48701		__ret_293 = __builtin_shufflevector(__ret_293, __ret_293, __lane_reverse_128_16); \
	48572	#define vcopyq_lane_s64(__p0_293, __p1_293, __p2_293, __p3_293) __extension__ ({ \
	48573	int64x2_t __ret_293; \
	48574	int64x2_t __s0_293 = __p0_293; \
	48575	int64x1_t __s2_293 = __p2_293; \
	48576	int64x2_t __rev0_293; __rev0_293 = __builtin_shufflevector(__s0_293, __s0_293, __lane_reverse_128_64); \
	48577	__ret_293 = __noswap_vsetq_lane_s64(vget_lane_s64(__s2_293, __p3_293), __rev0_293, __p1_293); \
	48578	__ret_293 = __builtin_shufflevector(__ret_293, __ret_293, __lane_reverse_128_64); \
48702	48579	__ret_293; \
48703	48580	})
48704	48581	#endif
48705	48582
48706	48583	#ifdef __LITTLE_ENDIAN__
48707		#define vcopyq_lane_s8(__p0_294, __p1_294, __p2_294, __p3_294) __extension__ ({ \
48708		int8x16_t __ret_294; \
48709		int8x16_t __s0_294 = __p0_294; \
48710		int8x8_t __s2_294 = __p2_294; \
48711		__ret_294 = vsetq_lane_s8(vget_lane_s8(__s2_294, __p3_294), __s0_294, __p1_294); \
	48584	#define vcopyq_lane_mf8(__p0_294, __p1_294, __p2_294, __p3_294) __extension__ ({ \
	48585	mfloat8x16_t __ret_294; \
	48586	mfloat8x16_t __s0_294 = __p0_294; \
	48587	mfloat8x8_t __s2_294 = __p2_294; \
	48588	__ret_294 = vsetq_lane_mf8(vget_lane_mf8(__s2_294, __p3_294), __s0_294, __p1_294); \
48712	48589	__ret_294; \
48713	48590	})
48714	48591	#else
48715		#define vcopyq_lane_s8(__p0_295, __p1_295, __p2_295, __p3_295) __extension__ ({ \
48716		int8x16_t __ret_295; \
48717		int8x16_t __s0_295 = __p0_295; \
48718		int8x8_t __s2_295 = __p2_295; \
48719		int8x16_t __rev0_295; __rev0_295 = __builtin_shufflevector(__s0_295, __s0_295, __lane_reverse_128_8); \
48720		int8x8_t __rev2_295; __rev2_295 = __builtin_shufflevector(__s2_295, __s2_295, __lane_reverse_64_8); \
48721		__ret_295 = __noswap_vsetq_lane_s8(__noswap_vget_lane_s8(__rev2_295, __p3_295), __rev0_295, __p1_295); \
	48592	#define vcopyq_lane_mf8(__p0_295, __p1_295, __p2_295, __p3_295) __extension__ ({ \
	48593	mfloat8x16_t __ret_295; \
	48594	mfloat8x16_t __s0_295 = __p0_295; \
	48595	mfloat8x8_t __s2_295 = __p2_295; \
	48596	mfloat8x16_t __rev0_295; __rev0_295 = __builtin_shufflevector(__s0_295, __s0_295, __lane_reverse_128_8); \
	48597	mfloat8x8_t __rev2_295; __rev2_295 = __builtin_shufflevector(__s2_295, __s2_295, __lane_reverse_64_8); \
	48598	__ret_295 = __noswap_vsetq_lane_mf8(__noswap_vget_lane_mf8(__rev2_295, __p3_295), __rev0_295, __p1_295); \
48722	48599	__ret_295 = __builtin_shufflevector(__ret_295, __ret_295, __lane_reverse_128_8); \
48723	48600	__ret_295; \
48724	48601	})
48725	48602	#endif
48726	48603
48727	48604	#ifdef __LITTLE_ENDIAN__
48728		#define vcopyq_lane_f32(__p0_296, __p1_296, __p2_296, __p3_296) __extension__ ({ \
48729		float32x4_t __ret_296; \
48730		float32x4_t __s0_296 = __p0_296; \
48731		float32x2_t __s2_296 = __p2_296; \
48732		__ret_296 = vsetq_lane_f32(vget_lane_f32(__s2_296, __p3_296), __s0_296, __p1_296); \
	48605	#define vcopyq_lane_s16(__p0_296, __p1_296, __p2_296, __p3_296) __extension__ ({ \
	48606	int16x8_t __ret_296; \
	48607	int16x8_t __s0_296 = __p0_296; \
	48608	int16x4_t __s2_296 = __p2_296; \
	48609	__ret_296 = vsetq_lane_s16(vget_lane_s16(__s2_296, __p3_296), __s0_296, __p1_296); \
48733	48610	__ret_296; \
48734	48611	})
48735	48612	#else
48736		#define vcopyq_lane_f32(__p0_297, __p1_297, __p2_297, __p3_297) __extension__ ({ \
48737		float32x4_t __ret_297; \
48738		float32x4_t __s0_297 = __p0_297; \
48739		float32x2_t __s2_297 = __p2_297; \
48740		float32x4_t __rev0_297; __rev0_297 = __builtin_shufflevector(__s0_297, __s0_297, __lane_reverse_128_32); \
48741		float32x2_t __rev2_297; __rev2_297 = __builtin_shufflevector(__s2_297, __s2_297, __lane_reverse_64_32); \
48742		__ret_297 = __noswap_vsetq_lane_f32(__noswap_vget_lane_f32(__rev2_297, __p3_297), __rev0_297, __p1_297); \
48743		__ret_297 = __builtin_shufflevector(__ret_297, __ret_297, __lane_reverse_128_32); \
	48613	#define vcopyq_lane_s16(__p0_297, __p1_297, __p2_297, __p3_297) __extension__ ({ \
	48614	int16x8_t __ret_297; \
	48615	int16x8_t __s0_297 = __p0_297; \
	48616	int16x4_t __s2_297 = __p2_297; \
	48617	int16x8_t __rev0_297; __rev0_297 = __builtin_shufflevector(__s0_297, __s0_297, __lane_reverse_128_16); \
	48618	int16x4_t __rev2_297; __rev2_297 = __builtin_shufflevector(__s2_297, __s2_297, __lane_reverse_64_16); \
	48619	__ret_297 = __noswap_vsetq_lane_s16(__noswap_vget_lane_s16(__rev2_297, __p3_297), __rev0_297, __p1_297); \
	48620	__ret_297 = __builtin_shufflevector(__ret_297, __ret_297, __lane_reverse_128_16); \
48744	48621	__ret_297; \
48745	48622	})
48746	48623	#endif
48747	48624
48748	48625	#ifdef __LITTLE_ENDIAN__
48749		#define vcopyq_lane_s32(__p0_298, __p1_298, __p2_298, __p3_298) __extension__ ({ \
48750		int32x4_t __ret_298; \
48751		int32x4_t __s0_298 = __p0_298; \
48752		int32x2_t __s2_298 = __p2_298; \
48753		__ret_298 = vsetq_lane_s32(vget_lane_s32(__s2_298, __p3_298), __s0_298, __p1_298); \
	48626	#define vcopyq_lane_bf16(__p0_298, __p1_298, __p2_298, __p3_298) __extension__ ({ \
	48627	bfloat16x8_t __ret_298; \
	48628	bfloat16x8_t __s0_298 = __p0_298; \
	48629	bfloat16x4_t __s2_298 = __p2_298; \
	48630	__ret_298 = vsetq_lane_bf16(vget_lane_bf16(__s2_298, __p3_298), __s0_298, __p1_298); \
48754	48631	__ret_298; \
48755	48632	})
48756	48633	#else
48757		#define vcopyq_lane_s32(__p0_299, __p1_299, __p2_299, __p3_299) __extension__ ({ \
48758		int32x4_t __ret_299; \
48759		int32x4_t __s0_299 = __p0_299; \
48760		int32x2_t __s2_299 = __p2_299; \
48761		int32x4_t __rev0_299; __rev0_299 = __builtin_shufflevector(__s0_299, __s0_299, __lane_reverse_128_32); \
48762		int32x2_t __rev2_299; __rev2_299 = __builtin_shufflevector(__s2_299, __s2_299, __lane_reverse_64_32); \
48763		__ret_299 = __noswap_vsetq_lane_s32(__noswap_vget_lane_s32(__rev2_299, __p3_299), __rev0_299, __p1_299); \
48764		__ret_299 = __builtin_shufflevector(__ret_299, __ret_299, __lane_reverse_128_32); \
	48634	#define vcopyq_lane_bf16(__p0_299, __p1_299, __p2_299, __p3_299) __extension__ ({ \
	48635	bfloat16x8_t __ret_299; \
	48636	bfloat16x8_t __s0_299 = __p0_299; \
	48637	bfloat16x4_t __s2_299 = __p2_299; \
	48638	bfloat16x8_t __rev0_299; __rev0_299 = __builtin_shufflevector(__s0_299, __s0_299, __lane_reverse_128_16); \
	48639	bfloat16x4_t __rev2_299; __rev2_299 = __builtin_shufflevector(__s2_299, __s2_299, __lane_reverse_64_16); \
	48640	__ret_299 = __noswap_vsetq_lane_bf16(__noswap_vget_lane_bf16(__rev2_299, __p3_299), __rev0_299, __p1_299); \
	48641	__ret_299 = __builtin_shufflevector(__ret_299, __ret_299, __lane_reverse_128_16); \
48765	48642	__ret_299; \
48766	48643	})
48767	48644	#endif
48768	48645
48769	48646	#ifdef __LITTLE_ENDIAN__
48770		#define vcopyq_lane_s64(__p0_300, __p1_300, __p2_300, __p3_300) __extension__ ({ \
48771		int64x2_t __ret_300; \
48772		int64x2_t __s0_300 = __p0_300; \
48773		int64x1_t __s2_300 = __p2_300; \
48774		__ret_300 = vsetq_lane_s64(vget_lane_s64(__s2_300, __p3_300), __s0_300, __p1_300); \
	48647	#define vcopy_lane_p8(__p0_300, __p1_300, __p2_300, __p3_300) __extension__ ({ \
	48648	poly8x8_t __ret_300; \
	48649	poly8x8_t __s0_300 = __p0_300; \
	48650	poly8x8_t __s2_300 = __p2_300; \
	48651	__ret_300 = vset_lane_p8(vget_lane_p8(__s2_300, __p3_300), __s0_300, __p1_300); \
48775	48652	__ret_300; \
48776	48653	})
48777	48654	#else
48778		#define vcopyq_lane_s64(__p0_301, __p1_301, __p2_301, __p3_301) __extension__ ({ \
48779		int64x2_t __ret_301; \
48780		int64x2_t __s0_301 = __p0_301; \
48781		int64x1_t __s2_301 = __p2_301; \
48782		int64x2_t __rev0_301; __rev0_301 = __builtin_shufflevector(__s0_301, __s0_301, __lane_reverse_128_64); \
48783		__ret_301 = __noswap_vsetq_lane_s64(vget_lane_s64(__s2_301, __p3_301), __rev0_301, __p1_301); \
48784		__ret_301 = __builtin_shufflevector(__ret_301, __ret_301, __lane_reverse_128_64); \
	48655	#define vcopy_lane_p8(__p0_301, __p1_301, __p2_301, __p3_301) __extension__ ({ \
	48656	poly8x8_t __ret_301; \
	48657	poly8x8_t __s0_301 = __p0_301; \
	48658	poly8x8_t __s2_301 = __p2_301; \
	48659	poly8x8_t __rev0_301; __rev0_301 = __builtin_shufflevector(__s0_301, __s0_301, __lane_reverse_64_8); \
	48660	poly8x8_t __rev2_301; __rev2_301 = __builtin_shufflevector(__s2_301, __s2_301, __lane_reverse_64_8); \
	48661	__ret_301 = __noswap_vset_lane_p8(__noswap_vget_lane_p8(__rev2_301, __p3_301), __rev0_301, __p1_301); \
	48662	__ret_301 = __builtin_shufflevector(__ret_301, __ret_301, __lane_reverse_64_8); \
48785	48663	__ret_301; \
48786	48664	})
48787	48665	#endif
48788	48666
48789	48667	#ifdef __LITTLE_ENDIAN__
48790		#define vcopyq_lane_mf8(__p0_302, __p1_302, __p2_302, __p3_302) __extension__ ({ \
48791		mfloat8x16_t __ret_302; \
48792		mfloat8x16_t __s0_302 = __p0_302; \
48793		mfloat8x8_t __s2_302 = __p2_302; \
48794		__ret_302 = vsetq_lane_mf8(vget_lane_mf8(__s2_302, __p3_302), __s0_302, __p1_302); \
	48668	#define vcopy_lane_p16(__p0_302, __p1_302, __p2_302, __p3_302) __extension__ ({ \
	48669	poly16x4_t __ret_302; \
	48670	poly16x4_t __s0_302 = __p0_302; \
	48671	poly16x4_t __s2_302 = __p2_302; \
	48672	__ret_302 = vset_lane_p16(vget_lane_p16(__s2_302, __p3_302), __s0_302, __p1_302); \
48795	48673	__ret_302; \
48796	48674	})
48797	48675	#else
48798		#define vcopyq_lane_mf8(__p0_303, __p1_303, __p2_303, __p3_303) __extension__ ({ \
48799		mfloat8x16_t __ret_303; \
48800		mfloat8x16_t __s0_303 = __p0_303; \
48801		mfloat8x8_t __s2_303 = __p2_303; \
48802		mfloat8x16_t __rev0_303; __rev0_303 = __builtin_shufflevector(__s0_303, __s0_303, __lane_reverse_128_8); \
48803		mfloat8x8_t __rev2_303; __rev2_303 = __builtin_shufflevector(__s2_303, __s2_303, __lane_reverse_64_8); \
48804		__ret_303 = __noswap_vsetq_lane_mf8(__noswap_vget_lane_mf8(__rev2_303, __p3_303), __rev0_303, __p1_303); \
48805		__ret_303 = __builtin_shufflevector(__ret_303, __ret_303, __lane_reverse_128_8); \
	48676	#define vcopy_lane_p16(__p0_303, __p1_303, __p2_303, __p3_303) __extension__ ({ \
	48677	poly16x4_t __ret_303; \
	48678	poly16x4_t __s0_303 = __p0_303; \
	48679	poly16x4_t __s2_303 = __p2_303; \
	48680	poly16x4_t __rev0_303; __rev0_303 = __builtin_shufflevector(__s0_303, __s0_303, __lane_reverse_64_16); \
	48681	poly16x4_t __rev2_303; __rev2_303 = __builtin_shufflevector(__s2_303, __s2_303, __lane_reverse_64_16); \
	48682	__ret_303 = __noswap_vset_lane_p16(__noswap_vget_lane_p16(__rev2_303, __p3_303), __rev0_303, __p1_303); \
	48683	__ret_303 = __builtin_shufflevector(__ret_303, __ret_303, __lane_reverse_64_16); \
48806	48684	__ret_303; \
48807	48685	})
48808	48686	#endif
48809	48687
48810	48688	#ifdef __LITTLE_ENDIAN__
48811		#define vcopyq_lane_s16(__p0_304, __p1_304, __p2_304, __p3_304) __extension__ ({ \
48812		int16x8_t __ret_304; \
48813		int16x8_t __s0_304 = __p0_304; \
48814		int16x4_t __s2_304 = __p2_304; \
48815		__ret_304 = vsetq_lane_s16(vget_lane_s16(__s2_304, __p3_304), __s0_304, __p1_304); \
	48689	#define vcopy_lane_u8(__p0_304, __p1_304, __p2_304, __p3_304) __extension__ ({ \
	48690	uint8x8_t __ret_304; \
	48691	uint8x8_t __s0_304 = __p0_304; \
	48692	uint8x8_t __s2_304 = __p2_304; \
	48693	__ret_304 = vset_lane_u8(vget_lane_u8(__s2_304, __p3_304), __s0_304, __p1_304); \
48816	48694	__ret_304; \
48817	48695	})
48818	48696	#else
48819		#define vcopyq_lane_s16(__p0_305, __p1_305, __p2_305, __p3_305) __extension__ ({ \
48820		int16x8_t __ret_305; \
48821		int16x8_t __s0_305 = __p0_305; \
48822		int16x4_t __s2_305 = __p2_305; \
48823		int16x8_t __rev0_305; __rev0_305 = __builtin_shufflevector(__s0_305, __s0_305, __lane_reverse_128_16); \
48824		int16x4_t __rev2_305; __rev2_305 = __builtin_shufflevector(__s2_305, __s2_305, __lane_reverse_64_16); \
48825		__ret_305 = __noswap_vsetq_lane_s16(__noswap_vget_lane_s16(__rev2_305, __p3_305), __rev0_305, __p1_305); \
48826		__ret_305 = __builtin_shufflevector(__ret_305, __ret_305, __lane_reverse_128_16); \
	48697	#define vcopy_lane_u8(__p0_305, __p1_305, __p2_305, __p3_305) __extension__ ({ \
	48698	uint8x8_t __ret_305; \
	48699	uint8x8_t __s0_305 = __p0_305; \
	48700	uint8x8_t __s2_305 = __p2_305; \
	48701	uint8x8_t __rev0_305; __rev0_305 = __builtin_shufflevector(__s0_305, __s0_305, __lane_reverse_64_8); \
	48702	uint8x8_t __rev2_305; __rev2_305 = __builtin_shufflevector(__s2_305, __s2_305, __lane_reverse_64_8); \
	48703	__ret_305 = __noswap_vset_lane_u8(__noswap_vget_lane_u8(__rev2_305, __p3_305), __rev0_305, __p1_305); \
	48704	__ret_305 = __builtin_shufflevector(__ret_305, __ret_305, __lane_reverse_64_8); \
48827	48705	__ret_305; \
48828	48706	})
48829	48707	#endif
48830	48708
48831	48709	#ifdef __LITTLE_ENDIAN__
48832		#define vcopy_lane_p8(__p0_306, __p1_306, __p2_306, __p3_306) __extension__ ({ \
48833		poly8x8_t __ret_306; \
48834		poly8x8_t __s0_306 = __p0_306; \
48835		poly8x8_t __s2_306 = __p2_306; \
48836		__ret_306 = vset_lane_p8(vget_lane_p8(__s2_306, __p3_306), __s0_306, __p1_306); \
	48710	#define vcopy_lane_u32(__p0_306, __p1_306, __p2_306, __p3_306) __extension__ ({ \
	48711	uint32x2_t __ret_306; \
	48712	uint32x2_t __s0_306 = __p0_306; \
	48713	uint32x2_t __s2_306 = __p2_306; \
	48714	__ret_306 = vset_lane_u32(vget_lane_u32(__s2_306, __p3_306), __s0_306, __p1_306); \
48837	48715	__ret_306; \
48838	48716	})
48839	48717	#else
48840		#define vcopy_lane_p8(__p0_307, __p1_307, __p2_307, __p3_307) __extension__ ({ \
48841		poly8x8_t __ret_307; \
48842		poly8x8_t __s0_307 = __p0_307; \
48843		poly8x8_t __s2_307 = __p2_307; \
48844		poly8x8_t __rev0_307; __rev0_307 = __builtin_shufflevector(__s0_307, __s0_307, __lane_reverse_64_8); \
48845		poly8x8_t __rev2_307; __rev2_307 = __builtin_shufflevector(__s2_307, __s2_307, __lane_reverse_64_8); \
48846		__ret_307 = __noswap_vset_lane_p8(__noswap_vget_lane_p8(__rev2_307, __p3_307), __rev0_307, __p1_307); \
48847		__ret_307 = __builtin_shufflevector(__ret_307, __ret_307, __lane_reverse_64_8); \
	48718	#define vcopy_lane_u32(__p0_307, __p1_307, __p2_307, __p3_307) __extension__ ({ \
	48719	uint32x2_t __ret_307; \
	48720	uint32x2_t __s0_307 = __p0_307; \
	48721	uint32x2_t __s2_307 = __p2_307; \
	48722	uint32x2_t __rev0_307; __rev0_307 = __builtin_shufflevector(__s0_307, __s0_307, __lane_reverse_64_32); \
	48723	uint32x2_t __rev2_307; __rev2_307 = __builtin_shufflevector(__s2_307, __s2_307, __lane_reverse_64_32); \
	48724	__ret_307 = __noswap_vset_lane_u32(__noswap_vget_lane_u32(__rev2_307, __p3_307), __rev0_307, __p1_307); \
	48725	__ret_307 = __builtin_shufflevector(__ret_307, __ret_307, __lane_reverse_64_32); \
48848	48726	__ret_307; \
48849	48727	})
48850	48728	#endif
48851	48729
48852		#ifdef __LITTLE_ENDIAN__
48853		#define vcopy_lane_p16(__p0_308, __p1_308, __p2_308, __p3_308) __extension__ ({ \
48854		poly16x4_t __ret_308; \
48855		poly16x4_t __s0_308 = __p0_308; \
48856		poly16x4_t __s2_308 = __p2_308; \
48857		__ret_308 = vset_lane_p16(vget_lane_p16(__s2_308, __p3_308), __s0_308, __p1_308); \
	48730	#define vcopy_lane_u64(__p0_308, __p1_308, __p2_308, __p3_308) __extension__ ({ \
	48731	uint64x1_t __ret_308; \
	48732	uint64x1_t __s0_308 = __p0_308; \
	48733	uint64x1_t __s2_308 = __p2_308; \
	48734	__ret_308 = vset_lane_u64(vget_lane_u64(__s2_308, __p3_308), __s0_308, __p1_308); \
48858	48735	__ret_308; \
48859	48736	})
48860		#else
48861		#define vcopy_lane_p16(__p0_309, __p1_309, __p2_309, __p3_309) __extension__ ({ \
48862		poly16x4_t __ret_309; \
48863		poly16x4_t __s0_309 = __p0_309; \
48864		poly16x4_t __s2_309 = __p2_309; \
48865		poly16x4_t __rev0_309; __rev0_309 = __builtin_shufflevector(__s0_309, __s0_309, __lane_reverse_64_16); \
48866		poly16x4_t __rev2_309; __rev2_309 = __builtin_shufflevector(__s2_309, __s2_309, __lane_reverse_64_16); \
48867		__ret_309 = __noswap_vset_lane_p16(__noswap_vget_lane_p16(__rev2_309, __p3_309), __rev0_309, __p1_309); \
48868		__ret_309 = __builtin_shufflevector(__ret_309, __ret_309, __lane_reverse_64_16); \
	48737	#ifdef __LITTLE_ENDIAN__
	48738	#define vcopy_lane_u16(__p0_309, __p1_309, __p2_309, __p3_309) __extension__ ({ \
	48739	uint16x4_t __ret_309; \
	48740	uint16x4_t __s0_309 = __p0_309; \
	48741	uint16x4_t __s2_309 = __p2_309; \
	48742	__ret_309 = vset_lane_u16(vget_lane_u16(__s2_309, __p3_309), __s0_309, __p1_309); \
48869	48743	__ret_309; \
48870	48744	})
	48745	#else
	48746	#define vcopy_lane_u16(__p0_310, __p1_310, __p2_310, __p3_310) __extension__ ({ \
	48747	uint16x4_t __ret_310; \
	48748	uint16x4_t __s0_310 = __p0_310; \
	48749	uint16x4_t __s2_310 = __p2_310; \
	48750	uint16x4_t __rev0_310; __rev0_310 = __builtin_shufflevector(__s0_310, __s0_310, __lane_reverse_64_16); \
	48751	uint16x4_t __rev2_310; __rev2_310 = __builtin_shufflevector(__s2_310, __s2_310, __lane_reverse_64_16); \
	48752	__ret_310 = __noswap_vset_lane_u16(__noswap_vget_lane_u16(__rev2_310, __p3_310), __rev0_310, __p1_310); \
	48753	__ret_310 = __builtin_shufflevector(__ret_310, __ret_310, __lane_reverse_64_16); \
	48754	__ret_310; \
	48755	})
48871	48756	#endif
48872	48757
48873	48758	#ifdef __LITTLE_ENDIAN__
48874		#define vcopy_lane_u8(__p0_310, __p1_310, __p2_310, __p3_310) __extension__ ({ \
48875		uint8x8_t __ret_310; \
48876		uint8x8_t __s0_310 = __p0_310; \
48877		uint8x8_t __s2_310 = __p2_310; \
48878		__ret_310 = vset_lane_u8(vget_lane_u8(__s2_310, __p3_310), __s0_310, __p1_310); \
48879		__ret_310; \
	48759	#define vcopy_lane_s8(__p0_311, __p1_311, __p2_311, __p3_311) __extension__ ({ \
	48760	int8x8_t __ret_311; \
	48761	int8x8_t __s0_311 = __p0_311; \
	48762	int8x8_t __s2_311 = __p2_311; \
	48763	__ret_311 = vset_lane_s8(vget_lane_s8(__s2_311, __p3_311), __s0_311, __p1_311); \
	48764	__ret_311; \
48880	48765	})
48881	48766	#else
48882		#define vcopy_lane_u8(__p0_311, __p1_311, __p2_311, __p3_311) __extension__ ({ \
48883		uint8x8_t __ret_311; \
48884		uint8x8_t __s0_311 = __p0_311; \
48885		uint8x8_t __s2_311 = __p2_311; \
48886		uint8x8_t __rev0_311; __rev0_311 = __builtin_shufflevector(__s0_311, __s0_311, __lane_reverse_64_8); \
48887		uint8x8_t __rev2_311; __rev2_311 = __builtin_shufflevector(__s2_311, __s2_311, __lane_reverse_64_8); \
48888		__ret_311 = __noswap_vset_lane_u8(__noswap_vget_lane_u8(__rev2_311, __p3_311), __rev0_311, __p1_311); \
48889		__ret_311 = __builtin_shufflevector(__ret_311, __ret_311, __lane_reverse_64_8); \
48890		__ret_311; \
	48767	#define vcopy_lane_s8(__p0_312, __p1_312, __p2_312, __p3_312) __extension__ ({ \
	48768	int8x8_t __ret_312; \
	48769	int8x8_t __s0_312 = __p0_312; \
	48770	int8x8_t __s2_312 = __p2_312; \
	48771	int8x8_t __rev0_312; __rev0_312 = __builtin_shufflevector(__s0_312, __s0_312, __lane_reverse_64_8); \
	48772	int8x8_t __rev2_312; __rev2_312 = __builtin_shufflevector(__s2_312, __s2_312, __lane_reverse_64_8); \
	48773	__ret_312 = __noswap_vset_lane_s8(__noswap_vget_lane_s8(__rev2_312, __p3_312), __rev0_312, __p1_312); \
	48774	__ret_312 = __builtin_shufflevector(__ret_312, __ret_312, __lane_reverse_64_8); \
	48775	__ret_312; \
48891	48776	})
48892	48777	#endif
48893	48778
48894	48779	#ifdef __LITTLE_ENDIAN__
48895		#define vcopy_lane_u32(__p0_312, __p1_312, __p2_312, __p3_312) __extension__ ({ \
48896		uint32x2_t __ret_312; \
48897		uint32x2_t __s0_312 = __p0_312; \
48898		uint32x2_t __s2_312 = __p2_312; \
48899		__ret_312 = vset_lane_u32(vget_lane_u32(__s2_312, __p3_312), __s0_312, __p1_312); \
48900		__ret_312; \
	48780	#define vcopy_lane_f32(__p0_313, __p1_313, __p2_313, __p3_313) __extension__ ({ \
	48781	float32x2_t __ret_313; \
	48782	float32x2_t __s0_313 = __p0_313; \
	48783	float32x2_t __s2_313 = __p2_313; \
	48784	__ret_313 = vset_lane_f32(vget_lane_f32(__s2_313, __p3_313), __s0_313, __p1_313); \
	48785	__ret_313; \
48901	48786	})
48902	48787	#else
48903		#define vcopy_lane_u32(__p0_313, __p1_313, __p2_313, __p3_313) __extension__ ({ \
48904		uint32x2_t __ret_313; \
48905		uint32x2_t __s0_313 = __p0_313; \
48906		uint32x2_t __s2_313 = __p2_313; \
48907		uint32x2_t __rev0_313; __rev0_313 = __builtin_shufflevector(__s0_313, __s0_313, __lane_reverse_64_32); \
48908		uint32x2_t __rev2_313; __rev2_313 = __builtin_shufflevector(__s2_313, __s2_313, __lane_reverse_64_32); \
48909		__ret_313 = __noswap_vset_lane_u32(__noswap_vget_lane_u32(__rev2_313, __p3_313), __rev0_313, __p1_313); \
48910		__ret_313 = __builtin_shufflevector(__ret_313, __ret_313, __lane_reverse_64_32); \
48911		__ret_313; \
	48788	#define vcopy_lane_f32(__p0_314, __p1_314, __p2_314, __p3_314) __extension__ ({ \
	48789	float32x2_t __ret_314; \
	48790	float32x2_t __s0_314 = __p0_314; \
	48791	float32x2_t __s2_314 = __p2_314; \
	48792	float32x2_t __rev0_314; __rev0_314 = __builtin_shufflevector(__s0_314, __s0_314, __lane_reverse_64_32); \
	48793	float32x2_t __rev2_314; __rev2_314 = __builtin_shufflevector(__s2_314, __s2_314, __lane_reverse_64_32); \
	48794	__ret_314 = __noswap_vset_lane_f32(__noswap_vget_lane_f32(__rev2_314, __p3_314), __rev0_314, __p1_314); \
	48795	__ret_314 = __builtin_shufflevector(__ret_314, __ret_314, __lane_reverse_64_32); \
	48796	__ret_314; \
48912	48797	})
48913	48798	#endif
48914	48799
48915		#define vcopy_lane_u64(__p0_314, __p1_314, __p2_314, __p3_314) __extension__ ({ \
48916		uint64x1_t __ret_314; \
48917		uint64x1_t __s0_314 = __p0_314; \
48918		uint64x1_t __s2_314 = __p2_314; \
48919		__ret_314 = vset_lane_u64(vget_lane_u64(__s2_314, __p3_314), __s0_314, __p1_314); \
48920		__ret_314; \
48921		})
48922	48800	#ifdef __LITTLE_ENDIAN__
48923		#define vcopy_lane_u16(__p0_315, __p1_315, __p2_315, __p3_315) __extension__ ({ \
48924		uint16x4_t __ret_315; \
48925		uint16x4_t __s0_315 = __p0_315; \
48926		uint16x4_t __s2_315 = __p2_315; \
48927		__ret_315 = vset_lane_u16(vget_lane_u16(__s2_315, __p3_315), __s0_315, __p1_315); \
	48801	#define vcopy_lane_s32(__p0_315, __p1_315, __p2_315, __p3_315) __extension__ ({ \
	48802	int32x2_t __ret_315; \
	48803	int32x2_t __s0_315 = __p0_315; \
	48804	int32x2_t __s2_315 = __p2_315; \
	48805	__ret_315 = vset_lane_s32(vget_lane_s32(__s2_315, __p3_315), __s0_315, __p1_315); \
48928	48806	__ret_315; \
48929	48807	})
48930	48808	#else
48931		#define vcopy_lane_u16(__p0_316, __p1_316, __p2_316, __p3_316) __extension__ ({ \
48932		uint16x4_t __ret_316; \
48933		uint16x4_t __s0_316 = __p0_316; \
48934		uint16x4_t __s2_316 = __p2_316; \
48935		uint16x4_t __rev0_316; __rev0_316 = __builtin_shufflevector(__s0_316, __s0_316, __lane_reverse_64_16); \
48936		uint16x4_t __rev2_316; __rev2_316 = __builtin_shufflevector(__s2_316, __s2_316, __lane_reverse_64_16); \
48937		__ret_316 = __noswap_vset_lane_u16(__noswap_vget_lane_u16(__rev2_316, __p3_316), __rev0_316, __p1_316); \
48938		__ret_316 = __builtin_shufflevector(__ret_316, __ret_316, __lane_reverse_64_16); \
	48809	#define vcopy_lane_s32(__p0_316, __p1_316, __p2_316, __p3_316) __extension__ ({ \
	48810	int32x2_t __ret_316; \
	48811	int32x2_t __s0_316 = __p0_316; \
	48812	int32x2_t __s2_316 = __p2_316; \
	48813	int32x2_t __rev0_316; __rev0_316 = __builtin_shufflevector(__s0_316, __s0_316, __lane_reverse_64_32); \
	48814	int32x2_t __rev2_316; __rev2_316 = __builtin_shufflevector(__s2_316, __s2_316, __lane_reverse_64_32); \
	48815	__ret_316 = __noswap_vset_lane_s32(__noswap_vget_lane_s32(__rev2_316, __p3_316), __rev0_316, __p1_316); \
	48816	__ret_316 = __builtin_shufflevector(__ret_316, __ret_316, __lane_reverse_64_32); \
48939	48817	__ret_316; \
48940	48818	})
48941	48819	#endif
48942	48820
48943		#ifdef __LITTLE_ENDIAN__
48944		#define vcopy_lane_s8(__p0_317, __p1_317, __p2_317, __p3_317) __extension__ ({ \
48945		int8x8_t __ret_317; \
48946		int8x8_t __s0_317 = __p0_317; \
48947		int8x8_t __s2_317 = __p2_317; \
48948		__ret_317 = vset_lane_s8(vget_lane_s8(__s2_317, __p3_317), __s0_317, __p1_317); \
	48821	#define vcopy_lane_s64(__p0_317, __p1_317, __p2_317, __p3_317) __extension__ ({ \
	48822	int64x1_t __ret_317; \
	48823	int64x1_t __s0_317 = __p0_317; \
	48824	int64x1_t __s2_317 = __p2_317; \
	48825	__ret_317 = vset_lane_s64(vget_lane_s64(__s2_317, __p3_317), __s0_317, __p1_317); \
48949	48826	__ret_317; \
48950	48827	})
48951		#else
48952		#define vcopy_lane_s8(__p0_318, __p1_318, __p2_318, __p3_318) __extension__ ({ \
48953		int8x8_t __ret_318; \
48954		int8x8_t __s0_318 = __p0_318; \
48955		int8x8_t __s2_318 = __p2_318; \
48956		int8x8_t __rev0_318; __rev0_318 = __builtin_shufflevector(__s0_318, __s0_318, __lane_reverse_64_8); \
48957		int8x8_t __rev2_318; __rev2_318 = __builtin_shufflevector(__s2_318, __s2_318, __lane_reverse_64_8); \
48958		__ret_318 = __noswap_vset_lane_s8(__noswap_vget_lane_s8(__rev2_318, __p3_318), __rev0_318, __p1_318); \
48959		__ret_318 = __builtin_shufflevector(__ret_318, __ret_318, __lane_reverse_64_8); \
	48828	#ifdef __LITTLE_ENDIAN__
	48829	#define vcopy_lane_mf8(__p0_318, __p1_318, __p2_318, __p3_318) __extension__ ({ \
	48830	mfloat8x8_t __ret_318; \
	48831	mfloat8x8_t __s0_318 = __p0_318; \
	48832	mfloat8x8_t __s2_318 = __p2_318; \
	48833	__ret_318 = vset_lane_mf8(vget_lane_mf8(__s2_318, __p3_318), __s0_318, __p1_318); \
48960	48834	__ret_318; \
48961	48835	})
	48836	#else
	48837	#define vcopy_lane_mf8(__p0_319, __p1_319, __p2_319, __p3_319) __extension__ ({ \
	48838	mfloat8x8_t __ret_319; \
	48839	mfloat8x8_t __s0_319 = __p0_319; \
	48840	mfloat8x8_t __s2_319 = __p2_319; \
	48841	mfloat8x8_t __rev0_319; __rev0_319 = __builtin_shufflevector(__s0_319, __s0_319, __lane_reverse_64_8); \
	48842	mfloat8x8_t __rev2_319; __rev2_319 = __builtin_shufflevector(__s2_319, __s2_319, __lane_reverse_64_8); \
	48843	__ret_319 = __noswap_vset_lane_mf8(__noswap_vget_lane_mf8(__rev2_319, __p3_319), __rev0_319, __p1_319); \
	48844	__ret_319 = __builtin_shufflevector(__ret_319, __ret_319, __lane_reverse_64_8); \
	48845	__ret_319; \
	48846	})
48962	48847	#endif
48963	48848
48964	48849	#ifdef __LITTLE_ENDIAN__
48965		#define vcopy_lane_f32(__p0_319, __p1_319, __p2_319, __p3_319) __extension__ ({ \
48966		float32x2_t __ret_319; \
48967		float32x2_t __s0_319 = __p0_319; \
48968		float32x2_t __s2_319 = __p2_319; \
48969		__ret_319 = vset_lane_f32(vget_lane_f32(__s2_319, __p3_319), __s0_319, __p1_319); \
48970		__ret_319; \
	48850	#define vcopy_lane_s16(__p0_320, __p1_320, __p2_320, __p3_320) __extension__ ({ \
	48851	int16x4_t __ret_320; \
	48852	int16x4_t __s0_320 = __p0_320; \
	48853	int16x4_t __s2_320 = __p2_320; \
	48854	__ret_320 = vset_lane_s16(vget_lane_s16(__s2_320, __p3_320), __s0_320, __p1_320); \
	48855	__ret_320; \
48971	48856	})
48972	48857	#else
48973		#define vcopy_lane_f32(__p0_320, __p1_320, __p2_320, __p3_320) __extension__ ({ \
48974		float32x2_t __ret_320; \
48975		float32x2_t __s0_320 = __p0_320; \
48976		float32x2_t __s2_320 = __p2_320; \
48977		float32x2_t __rev0_320; __rev0_320 = __builtin_shufflevector(__s0_320, __s0_320, __lane_reverse_64_32); \
48978		float32x2_t __rev2_320; __rev2_320 = __builtin_shufflevector(__s2_320, __s2_320, __lane_reverse_64_32); \
48979		__ret_320 = __noswap_vset_lane_f32(__noswap_vget_lane_f32(__rev2_320, __p3_320), __rev0_320, __p1_320); \
48980		__ret_320 = __builtin_shufflevector(__ret_320, __ret_320, __lane_reverse_64_32); \
48981		__ret_320; \
	48858	#define vcopy_lane_s16(__p0_321, __p1_321, __p2_321, __p3_321) __extension__ ({ \
	48859	int16x4_t __ret_321; \
	48860	int16x4_t __s0_321 = __p0_321; \
	48861	int16x4_t __s2_321 = __p2_321; \
	48862	int16x4_t __rev0_321; __rev0_321 = __builtin_shufflevector(__s0_321, __s0_321, __lane_reverse_64_16); \
	48863	int16x4_t __rev2_321; __rev2_321 = __builtin_shufflevector(__s2_321, __s2_321, __lane_reverse_64_16); \
	48864	__ret_321 = __noswap_vset_lane_s16(__noswap_vget_lane_s16(__rev2_321, __p3_321), __rev0_321, __p1_321); \
	48865	__ret_321 = __builtin_shufflevector(__ret_321, __ret_321, __lane_reverse_64_16); \
	48866	__ret_321; \
48982	48867	})
48983	48868	#endif
48984	48869
48985	48870	#ifdef __LITTLE_ENDIAN__
48986		#define vcopy_lane_s32(__p0_321, __p1_321, __p2_321, __p3_321) __extension__ ({ \
48987		int32x2_t __ret_321; \
48988		int32x2_t __s0_321 = __p0_321; \
48989		int32x2_t __s2_321 = __p2_321; \
48990		__ret_321 = vset_lane_s32(vget_lane_s32(__s2_321, __p3_321), __s0_321, __p1_321); \
48991		__ret_321; \
	48871	#define vcopy_lane_bf16(__p0_322, __p1_322, __p2_322, __p3_322) __extension__ ({ \
	48872	bfloat16x4_t __ret_322; \
	48873	bfloat16x4_t __s0_322 = __p0_322; \
	48874	bfloat16x4_t __s2_322 = __p2_322; \
	48875	__ret_322 = vset_lane_bf16(vget_lane_bf16(__s2_322, __p3_322), __s0_322, __p1_322); \
	48876	__ret_322; \
48992	48877	})
48993	48878	#else
48994		#define vcopy_lane_s32(__p0_322, __p1_322, __p2_322, __p3_322) __extension__ ({ \
48995		int32x2_t __ret_322; \
48996		int32x2_t __s0_322 = __p0_322; \
48997		int32x2_t __s2_322 = __p2_322; \
48998		int32x2_t __rev0_322; __rev0_322 = __builtin_shufflevector(__s0_322, __s0_322, __lane_reverse_64_32); \
48999		int32x2_t __rev2_322; __rev2_322 = __builtin_shufflevector(__s2_322, __s2_322, __lane_reverse_64_32); \
49000		__ret_322 = __noswap_vset_lane_s32(__noswap_vget_lane_s32(__rev2_322, __p3_322), __rev0_322, __p1_322); \
49001		__ret_322 = __builtin_shufflevector(__ret_322, __ret_322, __lane_reverse_64_32); \
49002		__ret_322; \
	48879	#define vcopy_lane_bf16(__p0_323, __p1_323, __p2_323, __p3_323) __extension__ ({ \
	48880	bfloat16x4_t __ret_323; \
	48881	bfloat16x4_t __s0_323 = __p0_323; \
	48882	bfloat16x4_t __s2_323 = __p2_323; \
	48883	bfloat16x4_t __rev0_323; __rev0_323 = __builtin_shufflevector(__s0_323, __s0_323, __lane_reverse_64_16); \
	48884	bfloat16x4_t __rev2_323; __rev2_323 = __builtin_shufflevector(__s2_323, __s2_323, __lane_reverse_64_16); \
	48885	__ret_323 = __noswap_vset_lane_bf16(__noswap_vget_lane_bf16(__rev2_323, __p3_323), __rev0_323, __p1_323); \
	48886	__ret_323 = __builtin_shufflevector(__ret_323, __ret_323, __lane_reverse_64_16); \
	48887	__ret_323; \
49003	48888	})
49004	48889	#endif
49005	48890
49006		#define vcopy_lane_s64(__p0_323, __p1_323, __p2_323, __p3_323) __extension__ ({ \
49007		int64x1_t __ret_323; \
49008		int64x1_t __s0_323 = __p0_323; \
49009		int64x1_t __s2_323 = __p2_323; \
49010		__ret_323 = vset_lane_s64(vget_lane_s64(__s2_323, __p3_323), __s0_323, __p1_323); \
49011		__ret_323; \
49012		})
49013	48891	#ifdef __LITTLE_ENDIAN__
49014		#define vcopy_lane_mf8(__p0_324, __p1_324, __p2_324, __p3_324) __extension__ ({ \
49015		mfloat8x8_t __ret_324; \
49016		mfloat8x8_t __s0_324 = __p0_324; \
49017		mfloat8x8_t __s2_324 = __p2_324; \
49018		__ret_324 = vset_lane_mf8(vget_lane_mf8(__s2_324, __p3_324), __s0_324, __p1_324); \
	48892	#define vcopyq_laneq_p8(__p0_324, __p1_324, __p2_324, __p3_324) __extension__ ({ \
	48893	poly8x16_t __ret_324; \
	48894	poly8x16_t __s0_324 = __p0_324; \
	48895	poly8x16_t __s2_324 = __p2_324; \
	48896	__ret_324 = vsetq_lane_p8(vgetq_lane_p8(__s2_324, __p3_324), __s0_324, __p1_324); \
49019	48897	__ret_324; \
49020	48898	})
49021	48899	#else
49022		#define vcopy_lane_mf8(__p0_325, __p1_325, __p2_325, __p3_325) __extension__ ({ \
49023		mfloat8x8_t __ret_325; \
49024		mfloat8x8_t __s0_325 = __p0_325; \
49025		mfloat8x8_t __s2_325 = __p2_325; \
49026		mfloat8x8_t __rev0_325; __rev0_325 = __builtin_shufflevector(__s0_325, __s0_325, __lane_reverse_64_8); \
49027		mfloat8x8_t __rev2_325; __rev2_325 = __builtin_shufflevector(__s2_325, __s2_325, __lane_reverse_64_8); \
49028		__ret_325 = __noswap_vset_lane_mf8(__noswap_vget_lane_mf8(__rev2_325, __p3_325), __rev0_325, __p1_325); \
49029		__ret_325 = __builtin_shufflevector(__ret_325, __ret_325, __lane_reverse_64_8); \
	48900	#define vcopyq_laneq_p8(__p0_325, __p1_325, __p2_325, __p3_325) __extension__ ({ \
	48901	poly8x16_t __ret_325; \
	48902	poly8x16_t __s0_325 = __p0_325; \
	48903	poly8x16_t __s2_325 = __p2_325; \
	48904	poly8x16_t __rev0_325; __rev0_325 = __builtin_shufflevector(__s0_325, __s0_325, __lane_reverse_128_8); \
	48905	poly8x16_t __rev2_325; __rev2_325 = __builtin_shufflevector(__s2_325, __s2_325, __lane_reverse_128_8); \
	48906	__ret_325 = __noswap_vsetq_lane_p8(__noswap_vgetq_lane_p8(__rev2_325, __p3_325), __rev0_325, __p1_325); \
	48907	__ret_325 = __builtin_shufflevector(__ret_325, __ret_325, __lane_reverse_128_8); \
49030	48908	__ret_325; \
49031	48909	})
49032	48910	#endif
49033	48911
49034	48912	#ifdef __LITTLE_ENDIAN__
49035		#define vcopy_lane_s16(__p0_326, __p1_326, __p2_326, __p3_326) __extension__ ({ \
49036		int16x4_t __ret_326; \
49037		int16x4_t __s0_326 = __p0_326; \
49038		int16x4_t __s2_326 = __p2_326; \
49039		__ret_326 = vset_lane_s16(vget_lane_s16(__s2_326, __p3_326), __s0_326, __p1_326); \
	48913	#define vcopyq_laneq_p16(__p0_326, __p1_326, __p2_326, __p3_326) __extension__ ({ \
	48914	poly16x8_t __ret_326; \
	48915	poly16x8_t __s0_326 = __p0_326; \
	48916	poly16x8_t __s2_326 = __p2_326; \
	48917	__ret_326 = vsetq_lane_p16(vgetq_lane_p16(__s2_326, __p3_326), __s0_326, __p1_326); \
49040	48918	__ret_326; \
49041	48919	})
49042	48920	#else
49043		#define vcopy_lane_s16(__p0_327, __p1_327, __p2_327, __p3_327) __extension__ ({ \
49044		int16x4_t __ret_327; \
49045		int16x4_t __s0_327 = __p0_327; \
49046		int16x4_t __s2_327 = __p2_327; \
49047		int16x4_t __rev0_327; __rev0_327 = __builtin_shufflevector(__s0_327, __s0_327, __lane_reverse_64_16); \
49048		int16x4_t __rev2_327; __rev2_327 = __builtin_shufflevector(__s2_327, __s2_327, __lane_reverse_64_16); \
49049		__ret_327 = __noswap_vset_lane_s16(__noswap_vget_lane_s16(__rev2_327, __p3_327), __rev0_327, __p1_327); \
49050		__ret_327 = __builtin_shufflevector(__ret_327, __ret_327, __lane_reverse_64_16); \
	48921	#define vcopyq_laneq_p16(__p0_327, __p1_327, __p2_327, __p3_327) __extension__ ({ \
	48922	poly16x8_t __ret_327; \
	48923	poly16x8_t __s0_327 = __p0_327; \
	48924	poly16x8_t __s2_327 = __p2_327; \
	48925	poly16x8_t __rev0_327; __rev0_327 = __builtin_shufflevector(__s0_327, __s0_327, __lane_reverse_128_16); \
	48926	poly16x8_t __rev2_327; __rev2_327 = __builtin_shufflevector(__s2_327, __s2_327, __lane_reverse_128_16); \
	48927	__ret_327 = __noswap_vsetq_lane_p16(__noswap_vgetq_lane_p16(__rev2_327, __p3_327), __rev0_327, __p1_327); \
	48928	__ret_327 = __builtin_shufflevector(__ret_327, __ret_327, __lane_reverse_128_16); \
49051	48929	__ret_327; \
49052	48930	})
49053	48931	#endif
49054	48932
49055	48933	#ifdef __LITTLE_ENDIAN__
49056		#define vcopyq_laneq_p8(__p0_328, __p1_328, __p2_328, __p3_328) __extension__ ({ \
49057		poly8x16_t __ret_328; \
49058		poly8x16_t __s0_328 = __p0_328; \
49059		poly8x16_t __s2_328 = __p2_328; \
49060		__ret_328 = vsetq_lane_p8(vgetq_lane_p8(__s2_328, __p3_328), __s0_328, __p1_328); \
	48934	#define vcopyq_laneq_u8(__p0_328, __p1_328, __p2_328, __p3_328) __extension__ ({ \
	48935	uint8x16_t __ret_328; \
	48936	uint8x16_t __s0_328 = __p0_328; \
	48937	uint8x16_t __s2_328 = __p2_328; \
	48938	__ret_328 = vsetq_lane_u8(vgetq_lane_u8(__s2_328, __p3_328), __s0_328, __p1_328); \
49061	48939	__ret_328; \
49062	48940	})
49063	48941	#else
49064		#define vcopyq_laneq_p8(__p0_329, __p1_329, __p2_329, __p3_329) __extension__ ({ \
49065		poly8x16_t __ret_329; \
49066		poly8x16_t __s0_329 = __p0_329; \
49067		poly8x16_t __s2_329 = __p2_329; \
49068		poly8x16_t __rev0_329; __rev0_329 = __builtin_shufflevector(__s0_329, __s0_329, __lane_reverse_128_8); \
49069		poly8x16_t __rev2_329; __rev2_329 = __builtin_shufflevector(__s2_329, __s2_329, __lane_reverse_128_8); \
49070		__ret_329 = __noswap_vsetq_lane_p8(__noswap_vgetq_lane_p8(__rev2_329, __p3_329), __rev0_329, __p1_329); \
	48942	#define vcopyq_laneq_u8(__p0_329, __p1_329, __p2_329, __p3_329) __extension__ ({ \
	48943	uint8x16_t __ret_329; \
	48944	uint8x16_t __s0_329 = __p0_329; \
	48945	uint8x16_t __s2_329 = __p2_329; \
	48946	uint8x16_t __rev0_329; __rev0_329 = __builtin_shufflevector(__s0_329, __s0_329, __lane_reverse_128_8); \
	48947	uint8x16_t __rev2_329; __rev2_329 = __builtin_shufflevector(__s2_329, __s2_329, __lane_reverse_128_8); \
	48948	__ret_329 = __noswap_vsetq_lane_u8(__noswap_vgetq_lane_u8(__rev2_329, __p3_329), __rev0_329, __p1_329); \
49071	48949	__ret_329 = __builtin_shufflevector(__ret_329, __ret_329, __lane_reverse_128_8); \
49072	48950	__ret_329; \
49073	48951	})
49074	48952	#endif
49075	48953
49076	48954	#ifdef __LITTLE_ENDIAN__
49077		#define vcopyq_laneq_p16(__p0_330, __p1_330, __p2_330, __p3_330) __extension__ ({ \
49078		poly16x8_t __ret_330; \
49079		poly16x8_t __s0_330 = __p0_330; \
49080		poly16x8_t __s2_330 = __p2_330; \
49081		__ret_330 = vsetq_lane_p16(vgetq_lane_p16(__s2_330, __p3_330), __s0_330, __p1_330); \
	48955	#define vcopyq_laneq_u32(__p0_330, __p1_330, __p2_330, __p3_330) __extension__ ({ \
	48956	uint32x4_t __ret_330; \
	48957	uint32x4_t __s0_330 = __p0_330; \
	48958	uint32x4_t __s2_330 = __p2_330; \
	48959	__ret_330 = vsetq_lane_u32(vgetq_lane_u32(__s2_330, __p3_330), __s0_330, __p1_330); \
49082	48960	__ret_330; \
49083	48961	})
49084	48962	#else
49085		#define vcopyq_laneq_p16(__p0_331, __p1_331, __p2_331, __p3_331) __extension__ ({ \
49086		poly16x8_t __ret_331; \
49087		poly16x8_t __s0_331 = __p0_331; \
49088		poly16x8_t __s2_331 = __p2_331; \
49089		poly16x8_t __rev0_331; __rev0_331 = __builtin_shufflevector(__s0_331, __s0_331, __lane_reverse_128_16); \
49090		poly16x8_t __rev2_331; __rev2_331 = __builtin_shufflevector(__s2_331, __s2_331, __lane_reverse_128_16); \
49091		__ret_331 = __noswap_vsetq_lane_p16(__noswap_vgetq_lane_p16(__rev2_331, __p3_331), __rev0_331, __p1_331); \
49092		__ret_331 = __builtin_shufflevector(__ret_331, __ret_331, __lane_reverse_128_16); \
	48963	#define vcopyq_laneq_u32(__p0_331, __p1_331, __p2_331, __p3_331) __extension__ ({ \
	48964	uint32x4_t __ret_331; \
	48965	uint32x4_t __s0_331 = __p0_331; \
	48966	uint32x4_t __s2_331 = __p2_331; \
	48967	uint32x4_t __rev0_331; __rev0_331 = __builtin_shufflevector(__s0_331, __s0_331, __lane_reverse_128_32); \
	48968	uint32x4_t __rev2_331; __rev2_331 = __builtin_shufflevector(__s2_331, __s2_331, __lane_reverse_128_32); \
	48969	__ret_331 = __noswap_vsetq_lane_u32(__noswap_vgetq_lane_u32(__rev2_331, __p3_331), __rev0_331, __p1_331); \
	48970	__ret_331 = __builtin_shufflevector(__ret_331, __ret_331, __lane_reverse_128_32); \
49093	48971	__ret_331; \
49094	48972	})
49095	48973	#endif
49096	48974
49097	48975	#ifdef __LITTLE_ENDIAN__
49098		#define vcopyq_laneq_u8(__p0_332, __p1_332, __p2_332, __p3_332) __extension__ ({ \
49099		uint8x16_t __ret_332; \
49100		uint8x16_t __s0_332 = __p0_332; \
49101		uint8x16_t __s2_332 = __p2_332; \
49102		__ret_332 = vsetq_lane_u8(vgetq_lane_u8(__s2_332, __p3_332), __s0_332, __p1_332); \
	48976	#define vcopyq_laneq_u64(__p0_332, __p1_332, __p2_332, __p3_332) __extension__ ({ \
	48977	uint64x2_t __ret_332; \
	48978	uint64x2_t __s0_332 = __p0_332; \
	48979	uint64x2_t __s2_332 = __p2_332; \
	48980	__ret_332 = vsetq_lane_u64(vgetq_lane_u64(__s2_332, __p3_332), __s0_332, __p1_332); \
49103	48981	__ret_332; \
49104	48982	})
49105	48983	#else
49106		#define vcopyq_laneq_u8(__p0_333, __p1_333, __p2_333, __p3_333) __extension__ ({ \
49107		uint8x16_t __ret_333; \
49108		uint8x16_t __s0_333 = __p0_333; \
49109		uint8x16_t __s2_333 = __p2_333; \
49110		uint8x16_t __rev0_333; __rev0_333 = __builtin_shufflevector(__s0_333, __s0_333, __lane_reverse_128_8); \
49111		uint8x16_t __rev2_333; __rev2_333 = __builtin_shufflevector(__s2_333, __s2_333, __lane_reverse_128_8); \
49112		__ret_333 = __noswap_vsetq_lane_u8(__noswap_vgetq_lane_u8(__rev2_333, __p3_333), __rev0_333, __p1_333); \
49113		__ret_333 = __builtin_shufflevector(__ret_333, __ret_333, __lane_reverse_128_8); \
	48984	#define vcopyq_laneq_u64(__p0_333, __p1_333, __p2_333, __p3_333) __extension__ ({ \
	48985	uint64x2_t __ret_333; \
	48986	uint64x2_t __s0_333 = __p0_333; \
	48987	uint64x2_t __s2_333 = __p2_333; \
	48988	uint64x2_t __rev0_333; __rev0_333 = __builtin_shufflevector(__s0_333, __s0_333, __lane_reverse_128_64); \
	48989	uint64x2_t __rev2_333; __rev2_333 = __builtin_shufflevector(__s2_333, __s2_333, __lane_reverse_128_64); \
	48990	__ret_333 = __noswap_vsetq_lane_u64(__noswap_vgetq_lane_u64(__rev2_333, __p3_333), __rev0_333, __p1_333); \
	48991	__ret_333 = __builtin_shufflevector(__ret_333, __ret_333, __lane_reverse_128_64); \
49114	48992	__ret_333; \
49115	48993	})
49116	48994	#endif
49117	48995
49118	48996	#ifdef __LITTLE_ENDIAN__
49119		#define vcopyq_laneq_u32(__p0_334, __p1_334, __p2_334, __p3_334) __extension__ ({ \
49120		uint32x4_t __ret_334; \
49121		uint32x4_t __s0_334 = __p0_334; \
49122		uint32x4_t __s2_334 = __p2_334; \
49123		__ret_334 = vsetq_lane_u32(vgetq_lane_u32(__s2_334, __p3_334), __s0_334, __p1_334); \
	48997	#define vcopyq_laneq_u16(__p0_334, __p1_334, __p2_334, __p3_334) __extension__ ({ \
	48998	uint16x8_t __ret_334; \
	48999	uint16x8_t __s0_334 = __p0_334; \
	49000	uint16x8_t __s2_334 = __p2_334; \
	49001	__ret_334 = vsetq_lane_u16(vgetq_lane_u16(__s2_334, __p3_334), __s0_334, __p1_334); \
49124	49002	__ret_334; \
49125	49003	})
49126	49004	#else
49127		#define vcopyq_laneq_u32(__p0_335, __p1_335, __p2_335, __p3_335) __extension__ ({ \
49128		uint32x4_t __ret_335; \
49129		uint32x4_t __s0_335 = __p0_335; \
49130		uint32x4_t __s2_335 = __p2_335; \
49131		uint32x4_t __rev0_335; __rev0_335 = __builtin_shufflevector(__s0_335, __s0_335, __lane_reverse_128_32); \
49132		uint32x4_t __rev2_335; __rev2_335 = __builtin_shufflevector(__s2_335, __s2_335, __lane_reverse_128_32); \
49133		__ret_335 = __noswap_vsetq_lane_u32(__noswap_vgetq_lane_u32(__rev2_335, __p3_335), __rev0_335, __p1_335); \
49134		__ret_335 = __builtin_shufflevector(__ret_335, __ret_335, __lane_reverse_128_32); \
	49005	#define vcopyq_laneq_u16(__p0_335, __p1_335, __p2_335, __p3_335) __extension__ ({ \
	49006	uint16x8_t __ret_335; \
	49007	uint16x8_t __s0_335 = __p0_335; \
	49008	uint16x8_t __s2_335 = __p2_335; \
	49009	uint16x8_t __rev0_335; __rev0_335 = __builtin_shufflevector(__s0_335, __s0_335, __lane_reverse_128_16); \
	49010	uint16x8_t __rev2_335; __rev2_335 = __builtin_shufflevector(__s2_335, __s2_335, __lane_reverse_128_16); \
	49011	__ret_335 = __noswap_vsetq_lane_u16(__noswap_vgetq_lane_u16(__rev2_335, __p3_335), __rev0_335, __p1_335); \
	49012	__ret_335 = __builtin_shufflevector(__ret_335, __ret_335, __lane_reverse_128_16); \
49135	49013	__ret_335; \
49136	49014	})
49137	49015	#endif
49138	49016
49139	49017	#ifdef __LITTLE_ENDIAN__
49140		#define vcopyq_laneq_u64(__p0_336, __p1_336, __p2_336, __p3_336) __extension__ ({ \
49141		uint64x2_t __ret_336; \
49142		uint64x2_t __s0_336 = __p0_336; \
49143		uint64x2_t __s2_336 = __p2_336; \
49144		__ret_336 = vsetq_lane_u64(vgetq_lane_u64(__s2_336, __p3_336), __s0_336, __p1_336); \
	49018	#define vcopyq_laneq_s8(__p0_336, __p1_336, __p2_336, __p3_336) __extension__ ({ \
	49019	int8x16_t __ret_336; \
	49020	int8x16_t __s0_336 = __p0_336; \
	49021	int8x16_t __s2_336 = __p2_336; \
	49022	__ret_336 = vsetq_lane_s8(vgetq_lane_s8(__s2_336, __p3_336), __s0_336, __p1_336); \
49145	49023	__ret_336; \
49146	49024	})
49147	49025	#else
49148		#define vcopyq_laneq_u64(__p0_337, __p1_337, __p2_337, __p3_337) __extension__ ({ \
49149		uint64x2_t __ret_337; \
49150		uint64x2_t __s0_337 = __p0_337; \
49151		uint64x2_t __s2_337 = __p2_337; \
49152		uint64x2_t __rev0_337; __rev0_337 = __builtin_shufflevector(__s0_337, __s0_337, __lane_reverse_128_64); \
49153		uint64x2_t __rev2_337; __rev2_337 = __builtin_shufflevector(__s2_337, __s2_337, __lane_reverse_128_64); \
49154		__ret_337 = __noswap_vsetq_lane_u64(__noswap_vgetq_lane_u64(__rev2_337, __p3_337), __rev0_337, __p1_337); \
49155		__ret_337 = __builtin_shufflevector(__ret_337, __ret_337, __lane_reverse_128_64); \
	49026	#define vcopyq_laneq_s8(__p0_337, __p1_337, __p2_337, __p3_337) __extension__ ({ \
	49027	int8x16_t __ret_337; \
	49028	int8x16_t __s0_337 = __p0_337; \
	49029	int8x16_t __s2_337 = __p2_337; \
	49030	int8x16_t __rev0_337; __rev0_337 = __builtin_shufflevector(__s0_337, __s0_337, __lane_reverse_128_8); \
	49031	int8x16_t __rev2_337; __rev2_337 = __builtin_shufflevector(__s2_337, __s2_337, __lane_reverse_128_8); \
	49032	__ret_337 = __noswap_vsetq_lane_s8(__noswap_vgetq_lane_s8(__rev2_337, __p3_337), __rev0_337, __p1_337); \
	49033	__ret_337 = __builtin_shufflevector(__ret_337, __ret_337, __lane_reverse_128_8); \
49156	49034	__ret_337; \
49157	49035	})
49158	49036	#endif
49159	49037
49160	49038	#ifdef __LITTLE_ENDIAN__
49161		#define vcopyq_laneq_u16(__p0_338, __p1_338, __p2_338, __p3_338) __extension__ ({ \
49162		uint16x8_t __ret_338; \
49163		uint16x8_t __s0_338 = __p0_338; \
49164		uint16x8_t __s2_338 = __p2_338; \
49165		__ret_338 = vsetq_lane_u16(vgetq_lane_u16(__s2_338, __p3_338), __s0_338, __p1_338); \
	49039	#define vcopyq_laneq_f32(__p0_338, __p1_338, __p2_338, __p3_338) __extension__ ({ \
	49040	float32x4_t __ret_338; \
	49041	float32x4_t __s0_338 = __p0_338; \
	49042	float32x4_t __s2_338 = __p2_338; \
	49043	__ret_338 = vsetq_lane_f32(vgetq_lane_f32(__s2_338, __p3_338), __s0_338, __p1_338); \
49166	49044	__ret_338; \
49167	49045	})
49168	49046	#else
49169		#define vcopyq_laneq_u16(__p0_339, __p1_339, __p2_339, __p3_339) __extension__ ({ \
49170		uint16x8_t __ret_339; \
49171		uint16x8_t __s0_339 = __p0_339; \
49172		uint16x8_t __s2_339 = __p2_339; \
49173		uint16x8_t __rev0_339; __rev0_339 = __builtin_shufflevector(__s0_339, __s0_339, __lane_reverse_128_16); \
49174		uint16x8_t __rev2_339; __rev2_339 = __builtin_shufflevector(__s2_339, __s2_339, __lane_reverse_128_16); \
49175		__ret_339 = __noswap_vsetq_lane_u16(__noswap_vgetq_lane_u16(__rev2_339, __p3_339), __rev0_339, __p1_339); \
49176		__ret_339 = __builtin_shufflevector(__ret_339, __ret_339, __lane_reverse_128_16); \
	49047	#define vcopyq_laneq_f32(__p0_339, __p1_339, __p2_339, __p3_339) __extension__ ({ \
	49048	float32x4_t __ret_339; \
	49049	float32x4_t __s0_339 = __p0_339; \
	49050	float32x4_t __s2_339 = __p2_339; \
	49051	float32x4_t __rev0_339; __rev0_339 = __builtin_shufflevector(__s0_339, __s0_339, __lane_reverse_128_32); \
	49052	float32x4_t __rev2_339; __rev2_339 = __builtin_shufflevector(__s2_339, __s2_339, __lane_reverse_128_32); \
	49053	__ret_339 = __noswap_vsetq_lane_f32(__noswap_vgetq_lane_f32(__rev2_339, __p3_339), __rev0_339, __p1_339); \
	49054	__ret_339 = __builtin_shufflevector(__ret_339, __ret_339, __lane_reverse_128_32); \
49177	49055	__ret_339; \
49178	49056	})
49179	49057	#endif
49180	49058
49181	49059	#ifdef __LITTLE_ENDIAN__
49182		#define vcopyq_laneq_s8(__p0_340, __p1_340, __p2_340, __p3_340) __extension__ ({ \
49183		int8x16_t __ret_340; \
49184		int8x16_t __s0_340 = __p0_340; \
49185		int8x16_t __s2_340 = __p2_340; \
49186		__ret_340 = vsetq_lane_s8(vgetq_lane_s8(__s2_340, __p3_340), __s0_340, __p1_340); \
	49060	#define vcopyq_laneq_s32(__p0_340, __p1_340, __p2_340, __p3_340) __extension__ ({ \
	49061	int32x4_t __ret_340; \
	49062	int32x4_t __s0_340 = __p0_340; \
	49063	int32x4_t __s2_340 = __p2_340; \
	49064	__ret_340 = vsetq_lane_s32(vgetq_lane_s32(__s2_340, __p3_340), __s0_340, __p1_340); \
49187	49065	__ret_340; \
49188	49066	})
49189	49067	#else
49190		#define vcopyq_laneq_s8(__p0_341, __p1_341, __p2_341, __p3_341) __extension__ ({ \
49191		int8x16_t __ret_341; \
49192		int8x16_t __s0_341 = __p0_341; \
49193		int8x16_t __s2_341 = __p2_341; \
49194		int8x16_t __rev0_341; __rev0_341 = __builtin_shufflevector(__s0_341, __s0_341, __lane_reverse_128_8); \
49195		int8x16_t __rev2_341; __rev2_341 = __builtin_shufflevector(__s2_341, __s2_341, __lane_reverse_128_8); \
49196		__ret_341 = __noswap_vsetq_lane_s8(__noswap_vgetq_lane_s8(__rev2_341, __p3_341), __rev0_341, __p1_341); \
49197		__ret_341 = __builtin_shufflevector(__ret_341, __ret_341, __lane_reverse_128_8); \
	49068	#define vcopyq_laneq_s32(__p0_341, __p1_341, __p2_341, __p3_341) __extension__ ({ \
	49069	int32x4_t __ret_341; \
	49070	int32x4_t __s0_341 = __p0_341; \
	49071	int32x4_t __s2_341 = __p2_341; \
	49072	int32x4_t __rev0_341; __rev0_341 = __builtin_shufflevector(__s0_341, __s0_341, __lane_reverse_128_32); \
	49073	int32x4_t __rev2_341; __rev2_341 = __builtin_shufflevector(__s2_341, __s2_341, __lane_reverse_128_32); \
	49074	__ret_341 = __noswap_vsetq_lane_s32(__noswap_vgetq_lane_s32(__rev2_341, __p3_341), __rev0_341, __p1_341); \
	49075	__ret_341 = __builtin_shufflevector(__ret_341, __ret_341, __lane_reverse_128_32); \
49198	49076	__ret_341; \
49199	49077	})
49200	49078	#endif
49201	49079
49202	49080	#ifdef __LITTLE_ENDIAN__
49203		#define vcopyq_laneq_f32(__p0_342, __p1_342, __p2_342, __p3_342) __extension__ ({ \
49204		float32x4_t __ret_342; \
49205		float32x4_t __s0_342 = __p0_342; \
49206		float32x4_t __s2_342 = __p2_342; \
49207		__ret_342 = vsetq_lane_f32(vgetq_lane_f32(__s2_342, __p3_342), __s0_342, __p1_342); \
	49081	#define vcopyq_laneq_s64(__p0_342, __p1_342, __p2_342, __p3_342) __extension__ ({ \
	49082	int64x2_t __ret_342; \
	49083	int64x2_t __s0_342 = __p0_342; \
	49084	int64x2_t __s2_342 = __p2_342; \
	49085	__ret_342 = vsetq_lane_s64(vgetq_lane_s64(__s2_342, __p3_342), __s0_342, __p1_342); \
49208	49086	__ret_342; \
49209	49087	})
49210	49088	#else
49211		#define vcopyq_laneq_f32(__p0_343, __p1_343, __p2_343, __p3_343) __extension__ ({ \
49212		float32x4_t __ret_343; \
49213		float32x4_t __s0_343 = __p0_343; \
49214		float32x4_t __s2_343 = __p2_343; \
49215		float32x4_t __rev0_343; __rev0_343 = __builtin_shufflevector(__s0_343, __s0_343, __lane_reverse_128_32); \
49216		float32x4_t __rev2_343; __rev2_343 = __builtin_shufflevector(__s2_343, __s2_343, __lane_reverse_128_32); \
49217		__ret_343 = __noswap_vsetq_lane_f32(__noswap_vgetq_lane_f32(__rev2_343, __p3_343), __rev0_343, __p1_343); \
49218		__ret_343 = __builtin_shufflevector(__ret_343, __ret_343, __lane_reverse_128_32); \
	49089	#define vcopyq_laneq_s64(__p0_343, __p1_343, __p2_343, __p3_343) __extension__ ({ \
	49090	int64x2_t __ret_343; \
	49091	int64x2_t __s0_343 = __p0_343; \
	49092	int64x2_t __s2_343 = __p2_343; \
	49093	int64x2_t __rev0_343; __rev0_343 = __builtin_shufflevector(__s0_343, __s0_343, __lane_reverse_128_64); \
	49094	int64x2_t __rev2_343; __rev2_343 = __builtin_shufflevector(__s2_343, __s2_343, __lane_reverse_128_64); \
	49095	__ret_343 = __noswap_vsetq_lane_s64(__noswap_vgetq_lane_s64(__rev2_343, __p3_343), __rev0_343, __p1_343); \
	49096	__ret_343 = __builtin_shufflevector(__ret_343, __ret_343, __lane_reverse_128_64); \
49219	49097	__ret_343; \
49220	49098	})
49221	49099	#endif
49222	49100
49223	49101	#ifdef __LITTLE_ENDIAN__
49224		#define vcopyq_laneq_s32(__p0_344, __p1_344, __p2_344, __p3_344) __extension__ ({ \
49225		int32x4_t __ret_344; \
49226		int32x4_t __s0_344 = __p0_344; \
49227		int32x4_t __s2_344 = __p2_344; \
49228		__ret_344 = vsetq_lane_s32(vgetq_lane_s32(__s2_344, __p3_344), __s0_344, __p1_344); \
	49102	#define vcopyq_laneq_mf8(__p0_344, __p1_344, __p2_344, __p3_344) __extension__ ({ \
	49103	mfloat8x16_t __ret_344; \
	49104	mfloat8x16_t __s0_344 = __p0_344; \
	49105	mfloat8x16_t __s2_344 = __p2_344; \
	49106	__ret_344 = vsetq_lane_mf8(vgetq_lane_mf8(__s2_344, __p3_344), __s0_344, __p1_344); \
49229	49107	__ret_344; \
49230	49108	})
49231	49109	#else
49232		#define vcopyq_laneq_s32(__p0_345, __p1_345, __p2_345, __p3_345) __extension__ ({ \
49233		int32x4_t __ret_345; \
49234		int32x4_t __s0_345 = __p0_345; \
49235		int32x4_t __s2_345 = __p2_345; \
49236		int32x4_t __rev0_345; __rev0_345 = __builtin_shufflevector(__s0_345, __s0_345, __lane_reverse_128_32); \
49237		int32x4_t __rev2_345; __rev2_345 = __builtin_shufflevector(__s2_345, __s2_345, __lane_reverse_128_32); \
49238		__ret_345 = __noswap_vsetq_lane_s32(__noswap_vgetq_lane_s32(__rev2_345, __p3_345), __rev0_345, __p1_345); \
49239		__ret_345 = __builtin_shufflevector(__ret_345, __ret_345, __lane_reverse_128_32); \
	49110	#define vcopyq_laneq_mf8(__p0_345, __p1_345, __p2_345, __p3_345) __extension__ ({ \
	49111	mfloat8x16_t __ret_345; \
	49112	mfloat8x16_t __s0_345 = __p0_345; \
	49113	mfloat8x16_t __s2_345 = __p2_345; \
	49114	mfloat8x16_t __rev0_345; __rev0_345 = __builtin_shufflevector(__s0_345, __s0_345, __lane_reverse_128_8); \
	49115	mfloat8x16_t __rev2_345; __rev2_345 = __builtin_shufflevector(__s2_345, __s2_345, __lane_reverse_128_8); \
	49116	__ret_345 = __noswap_vsetq_lane_mf8(__noswap_vgetq_lane_mf8(__rev2_345, __p3_345), __rev0_345, __p1_345); \
	49117	__ret_345 = __builtin_shufflevector(__ret_345, __ret_345, __lane_reverse_128_8); \
49240	49118	__ret_345; \
49241	49119	})
49242	49120	#endif
49243	49121
49244	49122	#ifdef __LITTLE_ENDIAN__
49245		#define vcopyq_laneq_s64(__p0_346, __p1_346, __p2_346, __p3_346) __extension__ ({ \
49246		int64x2_t __ret_346; \
49247		int64x2_t __s0_346 = __p0_346; \
49248		int64x2_t __s2_346 = __p2_346; \
49249		__ret_346 = vsetq_lane_s64(vgetq_lane_s64(__s2_346, __p3_346), __s0_346, __p1_346); \
	49123	#define vcopyq_laneq_s16(__p0_346, __p1_346, __p2_346, __p3_346) __extension__ ({ \
	49124	int16x8_t __ret_346; \
	49125	int16x8_t __s0_346 = __p0_346; \
	49126	int16x8_t __s2_346 = __p2_346; \
	49127	__ret_346 = vsetq_lane_s16(vgetq_lane_s16(__s2_346, __p3_346), __s0_346, __p1_346); \
49250	49128	__ret_346; \
49251	49129	})
49252	49130	#else
49253		#define vcopyq_laneq_s64(__p0_347, __p1_347, __p2_347, __p3_347) __extension__ ({ \
49254		int64x2_t __ret_347; \
49255		int64x2_t __s0_347 = __p0_347; \
49256		int64x2_t __s2_347 = __p2_347; \
49257		int64x2_t __rev0_347; __rev0_347 = __builtin_shufflevector(__s0_347, __s0_347, __lane_reverse_128_64); \
49258		int64x2_t __rev2_347; __rev2_347 = __builtin_shufflevector(__s2_347, __s2_347, __lane_reverse_128_64); \
49259		__ret_347 = __noswap_vsetq_lane_s64(__noswap_vgetq_lane_s64(__rev2_347, __p3_347), __rev0_347, __p1_347); \
49260		__ret_347 = __builtin_shufflevector(__ret_347, __ret_347, __lane_reverse_128_64); \
	49131	#define vcopyq_laneq_s16(__p0_347, __p1_347, __p2_347, __p3_347) __extension__ ({ \
	49132	int16x8_t __ret_347; \
	49133	int16x8_t __s0_347 = __p0_347; \
	49134	int16x8_t __s2_347 = __p2_347; \
	49135	int16x8_t __rev0_347; __rev0_347 = __builtin_shufflevector(__s0_347, __s0_347, __lane_reverse_128_16); \
	49136	int16x8_t __rev2_347; __rev2_347 = __builtin_shufflevector(__s2_347, __s2_347, __lane_reverse_128_16); \
	49137	__ret_347 = __noswap_vsetq_lane_s16(__noswap_vgetq_lane_s16(__rev2_347, __p3_347), __rev0_347, __p1_347); \
	49138	__ret_347 = __builtin_shufflevector(__ret_347, __ret_347, __lane_reverse_128_16); \
49261	49139	__ret_347; \
49262	49140	})
49263	49141	#endif
49264	49142
49265	49143	#ifdef __LITTLE_ENDIAN__
49266		#define vcopyq_laneq_mf8(__p0_348, __p1_348, __p2_348, __p3_348) __extension__ ({ \
49267		mfloat8x16_t __ret_348; \
49268		mfloat8x16_t __s0_348 = __p0_348; \
49269		mfloat8x16_t __s2_348 = __p2_348; \
49270		__ret_348 = vsetq_lane_mf8(vgetq_lane_mf8(__s2_348, __p3_348), __s0_348, __p1_348); \
	49144	#define vcopyq_laneq_bf16(__p0_348, __p1_348, __p2_348, __p3_348) __extension__ ({ \
	49145	bfloat16x8_t __ret_348; \
	49146	bfloat16x8_t __s0_348 = __p0_348; \
	49147	bfloat16x8_t __s2_348 = __p2_348; \
	49148	__ret_348 = vsetq_lane_bf16(vgetq_lane_bf16(__s2_348, __p3_348), __s0_348, __p1_348); \
49271	49149	__ret_348; \
49272	49150	})
49273	49151	#else
49274		#define vcopyq_laneq_mf8(__p0_349, __p1_349, __p2_349, __p3_349) __extension__ ({ \
49275		mfloat8x16_t __ret_349; \
49276		mfloat8x16_t __s0_349 = __p0_349; \
49277		mfloat8x16_t __s2_349 = __p2_349; \
49278		mfloat8x16_t __rev0_349; __rev0_349 = __builtin_shufflevector(__s0_349, __s0_349, __lane_reverse_128_8); \
49279		mfloat8x16_t __rev2_349; __rev2_349 = __builtin_shufflevector(__s2_349, __s2_349, __lane_reverse_128_8); \
49280		__ret_349 = __noswap_vsetq_lane_mf8(__noswap_vgetq_lane_mf8(__rev2_349, __p3_349), __rev0_349, __p1_349); \
49281		__ret_349 = __builtin_shufflevector(__ret_349, __ret_349, __lane_reverse_128_8); \
	49152	#define vcopyq_laneq_bf16(__p0_349, __p1_349, __p2_349, __p3_349) __extension__ ({ \
	49153	bfloat16x8_t __ret_349; \
	49154	bfloat16x8_t __s0_349 = __p0_349; \
	49155	bfloat16x8_t __s2_349 = __p2_349; \
	49156	bfloat16x8_t __rev0_349; __rev0_349 = __builtin_shufflevector(__s0_349, __s0_349, __lane_reverse_128_16); \
	49157	bfloat16x8_t __rev2_349; __rev2_349 = __builtin_shufflevector(__s2_349, __s2_349, __lane_reverse_128_16); \
	49158	__ret_349 = __noswap_vsetq_lane_bf16(__noswap_vgetq_lane_bf16(__rev2_349, __p3_349), __rev0_349, __p1_349); \
	49159	__ret_349 = __builtin_shufflevector(__ret_349, __ret_349, __lane_reverse_128_16); \
49282	49160	__ret_349; \
49283	49161	})
49284	49162	#endif
49285	49163
49286	49164	#ifdef __LITTLE_ENDIAN__
49287		#define vcopyq_laneq_s16(__p0_350, __p1_350, __p2_350, __p3_350) __extension__ ({ \
49288		int16x8_t __ret_350; \
49289		int16x8_t __s0_350 = __p0_350; \
49290		int16x8_t __s2_350 = __p2_350; \
49291		__ret_350 = vsetq_lane_s16(vgetq_lane_s16(__s2_350, __p3_350), __s0_350, __p1_350); \
	49165	#define vcopy_laneq_p8(__p0_350, __p1_350, __p2_350, __p3_350) __extension__ ({ \
	49166	poly8x8_t __ret_350; \
	49167	poly8x8_t __s0_350 = __p0_350; \
	49168	poly8x16_t __s2_350 = __p2_350; \
	49169	__ret_350 = vset_lane_p8(vgetq_lane_p8(__s2_350, __p3_350), __s0_350, __p1_350); \
49292	49170	__ret_350; \
49293	49171	})
49294	49172	#else
49295		#define vcopyq_laneq_s16(__p0_351, __p1_351, __p2_351, __p3_351) __extension__ ({ \
49296		int16x8_t __ret_351; \
49297		int16x8_t __s0_351 = __p0_351; \
49298		int16x8_t __s2_351 = __p2_351; \
49299		int16x8_t __rev0_351; __rev0_351 = __builtin_shufflevector(__s0_351, __s0_351, __lane_reverse_128_16); \
49300		int16x8_t __rev2_351; __rev2_351 = __builtin_shufflevector(__s2_351, __s2_351, __lane_reverse_128_16); \
49301		__ret_351 = __noswap_vsetq_lane_s16(__noswap_vgetq_lane_s16(__rev2_351, __p3_351), __rev0_351, __p1_351); \
49302		__ret_351 = __builtin_shufflevector(__ret_351, __ret_351, __lane_reverse_128_16); \
	49173	#define vcopy_laneq_p8(__p0_351, __p1_351, __p2_351, __p3_351) __extension__ ({ \
	49174	poly8x8_t __ret_351; \
	49175	poly8x8_t __s0_351 = __p0_351; \
	49176	poly8x16_t __s2_351 = __p2_351; \
	49177	poly8x8_t __rev0_351; __rev0_351 = __builtin_shufflevector(__s0_351, __s0_351, __lane_reverse_64_8); \
	49178	poly8x16_t __rev2_351; __rev2_351 = __builtin_shufflevector(__s2_351, __s2_351, __lane_reverse_128_8); \
	49179	__ret_351 = __noswap_vset_lane_p8(__noswap_vgetq_lane_p8(__rev2_351, __p3_351), __rev0_351, __p1_351); \
	49180	__ret_351 = __builtin_shufflevector(__ret_351, __ret_351, __lane_reverse_64_8); \
49303	49181	__ret_351; \
49304	49182	})
49305	49183	#endif
49306	49184
49307	49185	#ifdef __LITTLE_ENDIAN__
49308		#define vcopy_laneq_p8(__p0_352, __p1_352, __p2_352, __p3_352) __extension__ ({ \
49309		poly8x8_t __ret_352; \
49310		poly8x8_t __s0_352 = __p0_352; \
49311		poly8x16_t __s2_352 = __p2_352; \
49312		__ret_352 = vset_lane_p8(vgetq_lane_p8(__s2_352, __p3_352), __s0_352, __p1_352); \
	49186	#define vcopy_laneq_p16(__p0_352, __p1_352, __p2_352, __p3_352) __extension__ ({ \
	49187	poly16x4_t __ret_352; \
	49188	poly16x4_t __s0_352 = __p0_352; \
	49189	poly16x8_t __s2_352 = __p2_352; \
	49190	__ret_352 = vset_lane_p16(vgetq_lane_p16(__s2_352, __p3_352), __s0_352, __p1_352); \
49313	49191	__ret_352; \
49314	49192	})
49315	49193	#else
49316		#define vcopy_laneq_p8(__p0_353, __p1_353, __p2_353, __p3_353) __extension__ ({ \
49317		poly8x8_t __ret_353; \
49318		poly8x8_t __s0_353 = __p0_353; \
49319		poly8x16_t __s2_353 = __p2_353; \
49320		poly8x8_t __rev0_353; __rev0_353 = __builtin_shufflevector(__s0_353, __s0_353, __lane_reverse_64_8); \
49321		poly8x16_t __rev2_353; __rev2_353 = __builtin_shufflevector(__s2_353, __s2_353, __lane_reverse_128_8); \
49322		__ret_353 = __noswap_vset_lane_p8(__noswap_vgetq_lane_p8(__rev2_353, __p3_353), __rev0_353, __p1_353); \
49323		__ret_353 = __builtin_shufflevector(__ret_353, __ret_353, __lane_reverse_64_8); \
	49194	#define vcopy_laneq_p16(__p0_353, __p1_353, __p2_353, __p3_353) __extension__ ({ \
	49195	poly16x4_t __ret_353; \
	49196	poly16x4_t __s0_353 = __p0_353; \
	49197	poly16x8_t __s2_353 = __p2_353; \
	49198	poly16x4_t __rev0_353; __rev0_353 = __builtin_shufflevector(__s0_353, __s0_353, __lane_reverse_64_16); \
	49199	poly16x8_t __rev2_353; __rev2_353 = __builtin_shufflevector(__s2_353, __s2_353, __lane_reverse_128_16); \
	49200	__ret_353 = __noswap_vset_lane_p16(__noswap_vgetq_lane_p16(__rev2_353, __p3_353), __rev0_353, __p1_353); \
	49201	__ret_353 = __builtin_shufflevector(__ret_353, __ret_353, __lane_reverse_64_16); \
49324	49202	__ret_353; \
49325	49203	})
49326	49204	#endif
49327	49205
49328	49206	#ifdef __LITTLE_ENDIAN__
49329		#define vcopy_laneq_p16(__p0_354, __p1_354, __p2_354, __p3_354) __extension__ ({ \
49330		poly16x4_t __ret_354; \
49331		poly16x4_t __s0_354 = __p0_354; \
49332		poly16x8_t __s2_354 = __p2_354; \
49333		__ret_354 = vset_lane_p16(vgetq_lane_p16(__s2_354, __p3_354), __s0_354, __p1_354); \
	49207	#define vcopy_laneq_u8(__p0_354, __p1_354, __p2_354, __p3_354) __extension__ ({ \
	49208	uint8x8_t __ret_354; \
	49209	uint8x8_t __s0_354 = __p0_354; \
	49210	uint8x16_t __s2_354 = __p2_354; \
	49211	__ret_354 = vset_lane_u8(vgetq_lane_u8(__s2_354, __p3_354), __s0_354, __p1_354); \
49334	49212	__ret_354; \
49335	49213	})
49336	49214	#else
49337		#define vcopy_laneq_p16(__p0_355, __p1_355, __p2_355, __p3_355) __extension__ ({ \
49338		poly16x4_t __ret_355; \
49339		poly16x4_t __s0_355 = __p0_355; \
49340		poly16x8_t __s2_355 = __p2_355; \
49341		poly16x4_t __rev0_355; __rev0_355 = __builtin_shufflevector(__s0_355, __s0_355, __lane_reverse_64_16); \
49342		poly16x8_t __rev2_355; __rev2_355 = __builtin_shufflevector(__s2_355, __s2_355, __lane_reverse_128_16); \
49343		__ret_355 = __noswap_vset_lane_p16(__noswap_vgetq_lane_p16(__rev2_355, __p3_355), __rev0_355, __p1_355); \
49344		__ret_355 = __builtin_shufflevector(__ret_355, __ret_355, __lane_reverse_64_16); \
	49215	#define vcopy_laneq_u8(__p0_355, __p1_355, __p2_355, __p3_355) __extension__ ({ \
	49216	uint8x8_t __ret_355; \
	49217	uint8x8_t __s0_355 = __p0_355; \
	49218	uint8x16_t __s2_355 = __p2_355; \
	49219	uint8x8_t __rev0_355; __rev0_355 = __builtin_shufflevector(__s0_355, __s0_355, __lane_reverse_64_8); \
	49220	uint8x16_t __rev2_355; __rev2_355 = __builtin_shufflevector(__s2_355, __s2_355, __lane_reverse_128_8); \
	49221	__ret_355 = __noswap_vset_lane_u8(__noswap_vgetq_lane_u8(__rev2_355, __p3_355), __rev0_355, __p1_355); \
	49222	__ret_355 = __builtin_shufflevector(__ret_355, __ret_355, __lane_reverse_64_8); \
49345	49223	__ret_355; \
49346	49224	})
49347	49225	#endif
49348	49226
49349	49227	#ifdef __LITTLE_ENDIAN__
49350		#define vcopy_laneq_u8(__p0_356, __p1_356, __p2_356, __p3_356) __extension__ ({ \
49351		uint8x8_t __ret_356; \
49352		uint8x8_t __s0_356 = __p0_356; \
49353		uint8x16_t __s2_356 = __p2_356; \
49354		__ret_356 = vset_lane_u8(vgetq_lane_u8(__s2_356, __p3_356), __s0_356, __p1_356); \
	49228	#define vcopy_laneq_u32(__p0_356, __p1_356, __p2_356, __p3_356) __extension__ ({ \
	49229	uint32x2_t __ret_356; \
	49230	uint32x2_t __s0_356 = __p0_356; \
	49231	uint32x4_t __s2_356 = __p2_356; \
	49232	__ret_356 = vset_lane_u32(vgetq_lane_u32(__s2_356, __p3_356), __s0_356, __p1_356); \
49355	49233	__ret_356; \
49356	49234	})
49357	49235	#else
49358		#define vcopy_laneq_u8(__p0_357, __p1_357, __p2_357, __p3_357) __extension__ ({ \
49359		uint8x8_t __ret_357; \
49360		uint8x8_t __s0_357 = __p0_357; \
49361		uint8x16_t __s2_357 = __p2_357; \
49362		uint8x8_t __rev0_357; __rev0_357 = __builtin_shufflevector(__s0_357, __s0_357, __lane_reverse_64_8); \
49363		uint8x16_t __rev2_357; __rev2_357 = __builtin_shufflevector(__s2_357, __s2_357, __lane_reverse_128_8); \
49364		__ret_357 = __noswap_vset_lane_u8(__noswap_vgetq_lane_u8(__rev2_357, __p3_357), __rev0_357, __p1_357); \
49365		__ret_357 = __builtin_shufflevector(__ret_357, __ret_357, __lane_reverse_64_8); \
	49236	#define vcopy_laneq_u32(__p0_357, __p1_357, __p2_357, __p3_357) __extension__ ({ \
	49237	uint32x2_t __ret_357; \
	49238	uint32x2_t __s0_357 = __p0_357; \
	49239	uint32x4_t __s2_357 = __p2_357; \
	49240	uint32x2_t __rev0_357; __rev0_357 = __builtin_shufflevector(__s0_357, __s0_357, __lane_reverse_64_32); \
	49241	uint32x4_t __rev2_357; __rev2_357 = __builtin_shufflevector(__s2_357, __s2_357, __lane_reverse_128_32); \
	49242	__ret_357 = __noswap_vset_lane_u32(__noswap_vgetq_lane_u32(__rev2_357, __p3_357), __rev0_357, __p1_357); \
	49243	__ret_357 = __builtin_shufflevector(__ret_357, __ret_357, __lane_reverse_64_32); \
49366	49244	__ret_357; \
49367	49245	})
49368	49246	#endif
49369	49247
49370	49248	#ifdef __LITTLE_ENDIAN__
49371		#define vcopy_laneq_u32(__p0_358, __p1_358, __p2_358, __p3_358) __extension__ ({ \
49372		uint32x2_t __ret_358; \
49373		uint32x2_t __s0_358 = __p0_358; \
49374		uint32x4_t __s2_358 = __p2_358; \
49375		__ret_358 = vset_lane_u32(vgetq_lane_u32(__s2_358, __p3_358), __s0_358, __p1_358); \
	49249	#define vcopy_laneq_u64(__p0_358, __p1_358, __p2_358, __p3_358) __extension__ ({ \
	49250	uint64x1_t __ret_358; \
	49251	uint64x1_t __s0_358 = __p0_358; \
	49252	uint64x2_t __s2_358 = __p2_358; \
	49253	__ret_358 = vset_lane_u64(vgetq_lane_u64(__s2_358, __p3_358), __s0_358, __p1_358); \
49376	49254	__ret_358; \
49377	49255	})
49378	49256	#else
49379		#define vcopy_laneq_u32(__p0_359, __p1_359, __p2_359, __p3_359) __extension__ ({ \
49380		uint32x2_t __ret_359; \
49381		uint32x2_t __s0_359 = __p0_359; \
49382		uint32x4_t __s2_359 = __p2_359; \
49383		uint32x2_t __rev0_359; __rev0_359 = __builtin_shufflevector(__s0_359, __s0_359, __lane_reverse_64_32); \
49384		uint32x4_t __rev2_359; __rev2_359 = __builtin_shufflevector(__s2_359, __s2_359, __lane_reverse_128_32); \
49385		__ret_359 = __noswap_vset_lane_u32(__noswap_vgetq_lane_u32(__rev2_359, __p3_359), __rev0_359, __p1_359); \
49386		__ret_359 = __builtin_shufflevector(__ret_359, __ret_359, __lane_reverse_64_32); \
	49257	#define vcopy_laneq_u64(__p0_359, __p1_359, __p2_359, __p3_359) __extension__ ({ \
	49258	uint64x1_t __ret_359; \
	49259	uint64x1_t __s0_359 = __p0_359; \
	49260	uint64x2_t __s2_359 = __p2_359; \
	49261	uint64x2_t __rev2_359; __rev2_359 = __builtin_shufflevector(__s2_359, __s2_359, __lane_reverse_128_64); \
	49262	__ret_359 = vset_lane_u64(__noswap_vgetq_lane_u64(__rev2_359, __p3_359), __s0_359, __p1_359); \
49387	49263	__ret_359; \
49388	49264	})
49389	49265	#endif
49390	49266
49391	49267	#ifdef __LITTLE_ENDIAN__
49392		#define vcopy_laneq_u64(__p0_360, __p1_360, __p2_360, __p3_360) __extension__ ({ \
49393		uint64x1_t __ret_360; \
49394		uint64x1_t __s0_360 = __p0_360; \
49395		uint64x2_t __s2_360 = __p2_360; \
49396		__ret_360 = vset_lane_u64(vgetq_lane_u64(__s2_360, __p3_360), __s0_360, __p1_360); \
	49268	#define vcopy_laneq_u16(__p0_360, __p1_360, __p2_360, __p3_360) __extension__ ({ \
	49269	uint16x4_t __ret_360; \
	49270	uint16x4_t __s0_360 = __p0_360; \
	49271	uint16x8_t __s2_360 = __p2_360; \
	49272	__ret_360 = vset_lane_u16(vgetq_lane_u16(__s2_360, __p3_360), __s0_360, __p1_360); \
49397	49273	__ret_360; \
49398	49274	})
49399	49275	#else
49400		#define vcopy_laneq_u64(__p0_361, __p1_361, __p2_361, __p3_361) __extension__ ({ \
49401		uint64x1_t __ret_361; \
49402		uint64x1_t __s0_361 = __p0_361; \
49403		uint64x2_t __s2_361 = __p2_361; \
49404		uint64x2_t __rev2_361; __rev2_361 = __builtin_shufflevector(__s2_361, __s2_361, __lane_reverse_128_64); \
49405		__ret_361 = vset_lane_u64(__noswap_vgetq_lane_u64(__rev2_361, __p3_361), __s0_361, __p1_361); \
	49276	#define vcopy_laneq_u16(__p0_361, __p1_361, __p2_361, __p3_361) __extension__ ({ \
	49277	uint16x4_t __ret_361; \
	49278	uint16x4_t __s0_361 = __p0_361; \
	49279	uint16x8_t __s2_361 = __p2_361; \
	49280	uint16x4_t __rev0_361; __rev0_361 = __builtin_shufflevector(__s0_361, __s0_361, __lane_reverse_64_16); \
	49281	uint16x8_t __rev2_361; __rev2_361 = __builtin_shufflevector(__s2_361, __s2_361, __lane_reverse_128_16); \
	49282	__ret_361 = __noswap_vset_lane_u16(__noswap_vgetq_lane_u16(__rev2_361, __p3_361), __rev0_361, __p1_361); \
	49283	__ret_361 = __builtin_shufflevector(__ret_361, __ret_361, __lane_reverse_64_16); \
49406	49284	__ret_361; \
49407	49285	})
49408	49286	#endif
49409	49287
49410	49288	#ifdef __LITTLE_ENDIAN__
49411		#define vcopy_laneq_u16(__p0_362, __p1_362, __p2_362, __p3_362) __extension__ ({ \
49412		uint16x4_t __ret_362; \
49413		uint16x4_t __s0_362 = __p0_362; \
49414		uint16x8_t __s2_362 = __p2_362; \
49415		__ret_362 = vset_lane_u16(vgetq_lane_u16(__s2_362, __p3_362), __s0_362, __p1_362); \
	49289	#define vcopy_laneq_s8(__p0_362, __p1_362, __p2_362, __p3_362) __extension__ ({ \
	49290	int8x8_t __ret_362; \
	49291	int8x8_t __s0_362 = __p0_362; \
	49292	int8x16_t __s2_362 = __p2_362; \
	49293	__ret_362 = vset_lane_s8(vgetq_lane_s8(__s2_362, __p3_362), __s0_362, __p1_362); \
49416	49294	__ret_362; \
49417	49295	})
49418	49296	#else
49419		#define vcopy_laneq_u16(__p0_363, __p1_363, __p2_363, __p3_363) __extension__ ({ \
49420		uint16x4_t __ret_363; \
49421		uint16x4_t __s0_363 = __p0_363; \
49422		uint16x8_t __s2_363 = __p2_363; \
49423		uint16x4_t __rev0_363; __rev0_363 = __builtin_shufflevector(__s0_363, __s0_363, __lane_reverse_64_16); \
49424		uint16x8_t __rev2_363; __rev2_363 = __builtin_shufflevector(__s2_363, __s2_363, __lane_reverse_128_16); \
49425		__ret_363 = __noswap_vset_lane_u16(__noswap_vgetq_lane_u16(__rev2_363, __p3_363), __rev0_363, __p1_363); \
49426		__ret_363 = __builtin_shufflevector(__ret_363, __ret_363, __lane_reverse_64_16); \
	49297	#define vcopy_laneq_s8(__p0_363, __p1_363, __p2_363, __p3_363) __extension__ ({ \
	49298	int8x8_t __ret_363; \
	49299	int8x8_t __s0_363 = __p0_363; \
	49300	int8x16_t __s2_363 = __p2_363; \
	49301	int8x8_t __rev0_363; __rev0_363 = __builtin_shufflevector(__s0_363, __s0_363, __lane_reverse_64_8); \
	49302	int8x16_t __rev2_363; __rev2_363 = __builtin_shufflevector(__s2_363, __s2_363, __lane_reverse_128_8); \
	49303	__ret_363 = __noswap_vset_lane_s8(__noswap_vgetq_lane_s8(__rev2_363, __p3_363), __rev0_363, __p1_363); \
	49304	__ret_363 = __builtin_shufflevector(__ret_363, __ret_363, __lane_reverse_64_8); \
49427	49305	__ret_363; \
49428	49306	})
49429	49307	#endif
49430	49308
49431	49309	#ifdef __LITTLE_ENDIAN__
49432		#define vcopy_laneq_s8(__p0_364, __p1_364, __p2_364, __p3_364) __extension__ ({ \
49433		int8x8_t __ret_364; \
49434		int8x8_t __s0_364 = __p0_364; \
49435		int8x16_t __s2_364 = __p2_364; \
49436		__ret_364 = vset_lane_s8(vgetq_lane_s8(__s2_364, __p3_364), __s0_364, __p1_364); \
	49310	#define vcopy_laneq_f32(__p0_364, __p1_364, __p2_364, __p3_364) __extension__ ({ \
	49311	float32x2_t __ret_364; \
	49312	float32x2_t __s0_364 = __p0_364; \
	49313	float32x4_t __s2_364 = __p2_364; \
	49314	__ret_364 = vset_lane_f32(vgetq_lane_f32(__s2_364, __p3_364), __s0_364, __p1_364); \
49437	49315	__ret_364; \
49438	49316	})
49439	49317	#else
49440		#define vcopy_laneq_s8(__p0_365, __p1_365, __p2_365, __p3_365) __extension__ ({ \
49441		int8x8_t __ret_365; \
49442		int8x8_t __s0_365 = __p0_365; \
49443		int8x16_t __s2_365 = __p2_365; \
49444		int8x8_t __rev0_365; __rev0_365 = __builtin_shufflevector(__s0_365, __s0_365, __lane_reverse_64_8); \
49445		int8x16_t __rev2_365; __rev2_365 = __builtin_shufflevector(__s2_365, __s2_365, __lane_reverse_128_8); \
49446		__ret_365 = __noswap_vset_lane_s8(__noswap_vgetq_lane_s8(__rev2_365, __p3_365), __rev0_365, __p1_365); \
49447		__ret_365 = __builtin_shufflevector(__ret_365, __ret_365, __lane_reverse_64_8); \
	49318	#define vcopy_laneq_f32(__p0_365, __p1_365, __p2_365, __p3_365) __extension__ ({ \
	49319	float32x2_t __ret_365; \
	49320	float32x2_t __s0_365 = __p0_365; \
	49321	float32x4_t __s2_365 = __p2_365; \
	49322	float32x2_t __rev0_365; __rev0_365 = __builtin_shufflevector(__s0_365, __s0_365, __lane_reverse_64_32); \
	49323	float32x4_t __rev2_365; __rev2_365 = __builtin_shufflevector(__s2_365, __s2_365, __lane_reverse_128_32); \
	49324	__ret_365 = __noswap_vset_lane_f32(__noswap_vgetq_lane_f32(__rev2_365, __p3_365), __rev0_365, __p1_365); \
	49325	__ret_365 = __builtin_shufflevector(__ret_365, __ret_365, __lane_reverse_64_32); \
49448	49326	__ret_365; \
49449	49327	})
49450	49328	#endif
49451	49329
49452	49330	#ifdef __LITTLE_ENDIAN__
49453		#define vcopy_laneq_f32(__p0_366, __p1_366, __p2_366, __p3_366) __extension__ ({ \
49454		float32x2_t __ret_366; \
49455		float32x2_t __s0_366 = __p0_366; \
49456		float32x4_t __s2_366 = __p2_366; \
49457		__ret_366 = vset_lane_f32(vgetq_lane_f32(__s2_366, __p3_366), __s0_366, __p1_366); \
	49331	#define vcopy_laneq_s32(__p0_366, __p1_366, __p2_366, __p3_366) __extension__ ({ \
	49332	int32x2_t __ret_366; \
	49333	int32x2_t __s0_366 = __p0_366; \
	49334	int32x4_t __s2_366 = __p2_366; \
	49335	__ret_366 = vset_lane_s32(vgetq_lane_s32(__s2_366, __p3_366), __s0_366, __p1_366); \
49458	49336	__ret_366; \
49459	49337	})
49460	49338	#else
49461		#define vcopy_laneq_f32(__p0_367, __p1_367, __p2_367, __p3_367) __extension__ ({ \
49462		float32x2_t __ret_367; \
49463		float32x2_t __s0_367 = __p0_367; \
49464		float32x4_t __s2_367 = __p2_367; \
49465		float32x2_t __rev0_367; __rev0_367 = __builtin_shufflevector(__s0_367, __s0_367, __lane_reverse_64_32); \
49466		float32x4_t __rev2_367; __rev2_367 = __builtin_shufflevector(__s2_367, __s2_367, __lane_reverse_128_32); \
49467		__ret_367 = __noswap_vset_lane_f32(__noswap_vgetq_lane_f32(__rev2_367, __p3_367), __rev0_367, __p1_367); \
	49339	#define vcopy_laneq_s32(__p0_367, __p1_367, __p2_367, __p3_367) __extension__ ({ \
	49340	int32x2_t __ret_367; \
	49341	int32x2_t __s0_367 = __p0_367; \
	49342	int32x4_t __s2_367 = __p2_367; \
	49343	int32x2_t __rev0_367; __rev0_367 = __builtin_shufflevector(__s0_367, __s0_367, __lane_reverse_64_32); \
	49344	int32x4_t __rev2_367; __rev2_367 = __builtin_shufflevector(__s2_367, __s2_367, __lane_reverse_128_32); \
	49345	__ret_367 = __noswap_vset_lane_s32(__noswap_vgetq_lane_s32(__rev2_367, __p3_367), __rev0_367, __p1_367); \
49468	49346	__ret_367 = __builtin_shufflevector(__ret_367, __ret_367, __lane_reverse_64_32); \
49469	49347	__ret_367; \
49470	49348	})
49471	49349	#endif
49472	49350
49473	49351	#ifdef __LITTLE_ENDIAN__
49474		#define vcopy_laneq_s32(__p0_368, __p1_368, __p2_368, __p3_368) __extension__ ({ \
49475		int32x2_t __ret_368; \
49476		int32x2_t __s0_368 = __p0_368; \
49477		int32x4_t __s2_368 = __p2_368; \
49478		__ret_368 = vset_lane_s32(vgetq_lane_s32(__s2_368, __p3_368), __s0_368, __p1_368); \
	49352	#define vcopy_laneq_s64(__p0_368, __p1_368, __p2_368, __p3_368) __extension__ ({ \
	49353	int64x1_t __ret_368; \
	49354	int64x1_t __s0_368 = __p0_368; \
	49355	int64x2_t __s2_368 = __p2_368; \
	49356	__ret_368 = vset_lane_s64(vgetq_lane_s64(__s2_368, __p3_368), __s0_368, __p1_368); \
49479	49357	__ret_368; \
49480	49358	})
49481	49359	#else
49482		#define vcopy_laneq_s32(__p0_369, __p1_369, __p2_369, __p3_369) __extension__ ({ \
49483		int32x2_t __ret_369; \
49484		int32x2_t __s0_369 = __p0_369; \
49485		int32x4_t __s2_369 = __p2_369; \
49486		int32x2_t __rev0_369; __rev0_369 = __builtin_shufflevector(__s0_369, __s0_369, __lane_reverse_64_32); \
49487		int32x4_t __rev2_369; __rev2_369 = __builtin_shufflevector(__s2_369, __s2_369, __lane_reverse_128_32); \
49488		__ret_369 = __noswap_vset_lane_s32(__noswap_vgetq_lane_s32(__rev2_369, __p3_369), __rev0_369, __p1_369); \
49489		__ret_369 = __builtin_shufflevector(__ret_369, __ret_369, __lane_reverse_64_32); \
	49360	#define vcopy_laneq_s64(__p0_369, __p1_369, __p2_369, __p3_369) __extension__ ({ \
	49361	int64x1_t __ret_369; \
	49362	int64x1_t __s0_369 = __p0_369; \
	49363	int64x2_t __s2_369 = __p2_369; \
	49364	int64x2_t __rev2_369; __rev2_369 = __builtin_shufflevector(__s2_369, __s2_369, __lane_reverse_128_64); \
	49365	__ret_369 = vset_lane_s64(__noswap_vgetq_lane_s64(__rev2_369, __p3_369), __s0_369, __p1_369); \
49490	49366	__ret_369; \
49491	49367	})
49492	49368	#endif
49493	49369
49494	49370	#ifdef __LITTLE_ENDIAN__
49495		#define vcopy_laneq_s64(__p0_370, __p1_370, __p2_370, __p3_370) __extension__ ({ \
49496		int64x1_t __ret_370; \
49497		int64x1_t __s0_370 = __p0_370; \
49498		int64x2_t __s2_370 = __p2_370; \
49499		__ret_370 = vset_lane_s64(vgetq_lane_s64(__s2_370, __p3_370), __s0_370, __p1_370); \
	49371	#define vcopy_laneq_mf8(__p0_370, __p1_370, __p2_370, __p3_370) __extension__ ({ \
	49372	mfloat8x8_t __ret_370; \
	49373	mfloat8x8_t __s0_370 = __p0_370; \
	49374	mfloat8x16_t __s2_370 = __p2_370; \
	49375	__ret_370 = vset_lane_mf8(vgetq_lane_mf8(__s2_370, __p3_370), __s0_370, __p1_370); \
49500	49376	__ret_370; \
49501	49377	})
49502	49378	#else
49503		#define vcopy_laneq_s64(__p0_371, __p1_371, __p2_371, __p3_371) __extension__ ({ \
49504		int64x1_t __ret_371; \
49505		int64x1_t __s0_371 = __p0_371; \
49506		int64x2_t __s2_371 = __p2_371; \
49507		int64x2_t __rev2_371; __rev2_371 = __builtin_shufflevector(__s2_371, __s2_371, __lane_reverse_128_64); \
49508		__ret_371 = vset_lane_s64(__noswap_vgetq_lane_s64(__rev2_371, __p3_371), __s0_371, __p1_371); \
	49379	#define vcopy_laneq_mf8(__p0_371, __p1_371, __p2_371, __p3_371) __extension__ ({ \
	49380	mfloat8x8_t __ret_371; \
	49381	mfloat8x8_t __s0_371 = __p0_371; \
	49382	mfloat8x16_t __s2_371 = __p2_371; \
	49383	mfloat8x8_t __rev0_371; __rev0_371 = __builtin_shufflevector(__s0_371, __s0_371, __lane_reverse_64_8); \
	49384	mfloat8x16_t __rev2_371; __rev2_371 = __builtin_shufflevector(__s2_371, __s2_371, __lane_reverse_128_8); \
	49385	__ret_371 = __noswap_vset_lane_mf8(__noswap_vgetq_lane_mf8(__rev2_371, __p3_371), __rev0_371, __p1_371); \
	49386	__ret_371 = __builtin_shufflevector(__ret_371, __ret_371, __lane_reverse_64_8); \
49509	49387	__ret_371; \
49510	49388	})
49511	49389	#endif
49512	49390
49513	49391	#ifdef __LITTLE_ENDIAN__
49514		#define vcopy_laneq_mf8(__p0_372, __p1_372, __p2_372, __p3_372) __extension__ ({ \
49515		mfloat8x8_t __ret_372; \
49516		mfloat8x8_t __s0_372 = __p0_372; \
49517		mfloat8x16_t __s2_372 = __p2_372; \
49518		__ret_372 = vset_lane_mf8(vgetq_lane_mf8(__s2_372, __p3_372), __s0_372, __p1_372); \
	49392	#define vcopy_laneq_s16(__p0_372, __p1_372, __p2_372, __p3_372) __extension__ ({ \
	49393	int16x4_t __ret_372; \
	49394	int16x4_t __s0_372 = __p0_372; \
	49395	int16x8_t __s2_372 = __p2_372; \
	49396	__ret_372 = vset_lane_s16(vgetq_lane_s16(__s2_372, __p3_372), __s0_372, __p1_372); \
49519	49397	__ret_372; \
49520	49398	})
49521	49399	#else
49522		#define vcopy_laneq_mf8(__p0_373, __p1_373, __p2_373, __p3_373) __extension__ ({ \
49523		mfloat8x8_t __ret_373; \
49524		mfloat8x8_t __s0_373 = __p0_373; \
49525		mfloat8x16_t __s2_373 = __p2_373; \
49526		mfloat8x8_t __rev0_373; __rev0_373 = __builtin_shufflevector(__s0_373, __s0_373, __lane_reverse_64_8); \
49527		mfloat8x16_t __rev2_373; __rev2_373 = __builtin_shufflevector(__s2_373, __s2_373, __lane_reverse_128_8); \
49528		__ret_373 = __noswap_vset_lane_mf8(__noswap_vgetq_lane_mf8(__rev2_373, __p3_373), __rev0_373, __p1_373); \
49529		__ret_373 = __builtin_shufflevector(__ret_373, __ret_373, __lane_reverse_64_8); \
	49400	#define vcopy_laneq_s16(__p0_373, __p1_373, __p2_373, __p3_373) __extension__ ({ \
	49401	int16x4_t __ret_373; \
	49402	int16x4_t __s0_373 = __p0_373; \
	49403	int16x8_t __s2_373 = __p2_373; \
	49404	int16x4_t __rev0_373; __rev0_373 = __builtin_shufflevector(__s0_373, __s0_373, __lane_reverse_64_16); \
	49405	int16x8_t __rev2_373; __rev2_373 = __builtin_shufflevector(__s2_373, __s2_373, __lane_reverse_128_16); \
	49406	__ret_373 = __noswap_vset_lane_s16(__noswap_vgetq_lane_s16(__rev2_373, __p3_373), __rev0_373, __p1_373); \
	49407	__ret_373 = __builtin_shufflevector(__ret_373, __ret_373, __lane_reverse_64_16); \
49530	49408	__ret_373; \
49531	49409	})
49532	49410	#endif
49533	49411
49534	49412	#ifdef __LITTLE_ENDIAN__
49535		#define vcopy_laneq_s16(__p0_374, __p1_374, __p2_374, __p3_374) __extension__ ({ \
49536		int16x4_t __ret_374; \
49537		int16x4_t __s0_374 = __p0_374; \
49538		int16x8_t __s2_374 = __p2_374; \
49539		__ret_374 = vset_lane_s16(vgetq_lane_s16(__s2_374, __p3_374), __s0_374, __p1_374); \
	49413	#define vcopy_laneq_bf16(__p0_374, __p1_374, __p2_374, __p3_374) __extension__ ({ \
	49414	bfloat16x4_t __ret_374; \
	49415	bfloat16x4_t __s0_374 = __p0_374; \
	49416	bfloat16x8_t __s2_374 = __p2_374; \
	49417	__ret_374 = vset_lane_bf16(vgetq_lane_bf16(__s2_374, __p3_374), __s0_374, __p1_374); \
49540	49418	__ret_374; \
49541	49419	})
49542	49420	#else
49543		#define vcopy_laneq_s16(__p0_375, __p1_375, __p2_375, __p3_375) __extension__ ({ \
49544		int16x4_t __ret_375; \
49545		int16x4_t __s0_375 = __p0_375; \
49546		int16x8_t __s2_375 = __p2_375; \
49547		int16x4_t __rev0_375; __rev0_375 = __builtin_shufflevector(__s0_375, __s0_375, __lane_reverse_64_16); \
49548		int16x8_t __rev2_375; __rev2_375 = __builtin_shufflevector(__s2_375, __s2_375, __lane_reverse_128_16); \
49549		__ret_375 = __noswap_vset_lane_s16(__noswap_vgetq_lane_s16(__rev2_375, __p3_375), __rev0_375, __p1_375); \
	49421	#define vcopy_laneq_bf16(__p0_375, __p1_375, __p2_375, __p3_375) __extension__ ({ \
	49422	bfloat16x4_t __ret_375; \
	49423	bfloat16x4_t __s0_375 = __p0_375; \
	49424	bfloat16x8_t __s2_375 = __p2_375; \
	49425	bfloat16x4_t __rev0_375; __rev0_375 = __builtin_shufflevector(__s0_375, __s0_375, __lane_reverse_64_16); \
	49426	bfloat16x8_t __rev2_375; __rev2_375 = __builtin_shufflevector(__s2_375, __s2_375, __lane_reverse_128_16); \
	49427	__ret_375 = __noswap_vset_lane_bf16(__noswap_vgetq_lane_bf16(__rev2_375, __p3_375), __rev0_375, __p1_375); \
49550	49428	__ret_375 = __builtin_shufflevector(__ret_375, __ret_375, __lane_reverse_64_16); \
49551	49429	__ret_375; \
49552	49430	})
...	...	@@ -64144,6 +64022,296 @@ __ai __attribute__((target("neon"))) int16x4_t vreinterpret_s16_mf8(mfloat8x8_t
64144	64022	__ret = __builtin_bit_cast(int16x4_t, __p0);
64145	64023	return __ret;
64146	64024	}
	64025	__ai __attribute__((target("neon"))) poly8x8_t vreinterpret_p8_bf16(bfloat16x4_t __p0) {
	64026	poly8x8_t __ret;
	64027	__ret = __builtin_bit_cast(poly8x8_t, __p0);
	64028	return __ret;
	64029	}
	64030	__ai __attribute__((target("neon"))) poly64x1_t vreinterpret_p64_bf16(bfloat16x4_t __p0) {
	64031	poly64x1_t __ret;
	64032	__ret = __builtin_bit_cast(poly64x1_t, __p0);
	64033	return __ret;
	64034	}
	64035	__ai __attribute__((target("neon"))) poly16x4_t vreinterpret_p16_bf16(bfloat16x4_t __p0) {
	64036	poly16x4_t __ret;
	64037	__ret = __builtin_bit_cast(poly16x4_t, __p0);
	64038	return __ret;
	64039	}
	64040	__ai __attribute__((target("neon"))) poly8x16_t vreinterpretq_p8_bf16(bfloat16x8_t __p0) {
	64041	poly8x16_t __ret;
	64042	__ret = __builtin_bit_cast(poly8x16_t, __p0);
	64043	return __ret;
	64044	}
	64045	__ai __attribute__((target("neon"))) poly128_t vreinterpretq_p128_bf16(bfloat16x8_t __p0) {
	64046	poly128_t __ret;
	64047	__ret = __builtin_bit_cast(poly128_t, __p0);
	64048	return __ret;
	64049	}
	64050	__ai __attribute__((target("neon"))) poly64x2_t vreinterpretq_p64_bf16(bfloat16x8_t __p0) {
	64051	poly64x2_t __ret;
	64052	__ret = __builtin_bit_cast(poly64x2_t, __p0);
	64053	return __ret;
	64054	}
	64055	__ai __attribute__((target("neon"))) poly16x8_t vreinterpretq_p16_bf16(bfloat16x8_t __p0) {
	64056	poly16x8_t __ret;
	64057	__ret = __builtin_bit_cast(poly16x8_t, __p0);
	64058	return __ret;
	64059	}
	64060	__ai __attribute__((target("neon"))) uint8x16_t vreinterpretq_u8_bf16(bfloat16x8_t __p0) {
	64061	uint8x16_t __ret;
	64062	__ret = __builtin_bit_cast(uint8x16_t, __p0);
	64063	return __ret;
	64064	}
	64065	__ai __attribute__((target("neon"))) uint32x4_t vreinterpretq_u32_bf16(bfloat16x8_t __p0) {
	64066	uint32x4_t __ret;
	64067	__ret = __builtin_bit_cast(uint32x4_t, __p0);
	64068	return __ret;
	64069	}
	64070	__ai __attribute__((target("neon"))) uint64x2_t vreinterpretq_u64_bf16(bfloat16x8_t __p0) {
	64071	uint64x2_t __ret;
	64072	__ret = __builtin_bit_cast(uint64x2_t, __p0);
	64073	return __ret;
	64074	}
	64075	__ai __attribute__((target("neon"))) uint16x8_t vreinterpretq_u16_bf16(bfloat16x8_t __p0) {
	64076	uint16x8_t __ret;
	64077	__ret = __builtin_bit_cast(uint16x8_t, __p0);
	64078	return __ret;
	64079	}
	64080	__ai __attribute__((target("neon"))) int8x16_t vreinterpretq_s8_bf16(bfloat16x8_t __p0) {
	64081	int8x16_t __ret;
	64082	__ret = __builtin_bit_cast(int8x16_t, __p0);
	64083	return __ret;
	64084	}
	64085	__ai __attribute__((target("neon"))) float64x2_t vreinterpretq_f64_bf16(bfloat16x8_t __p0) {
	64086	float64x2_t __ret;
	64087	__ret = __builtin_bit_cast(float64x2_t, __p0);
	64088	return __ret;
	64089	}
	64090	__ai __attribute__((target("neon"))) float32x4_t vreinterpretq_f32_bf16(bfloat16x8_t __p0) {
	64091	float32x4_t __ret;
	64092	__ret = __builtin_bit_cast(float32x4_t, __p0);
	64093	return __ret;
	64094	}
	64095	__ai __attribute__((target("neon"))) float16x8_t vreinterpretq_f16_bf16(bfloat16x8_t __p0) {
	64096	float16x8_t __ret;
	64097	__ret = __builtin_bit_cast(float16x8_t, __p0);
	64098	return __ret;
	64099	}
	64100	__ai __attribute__((target("neon"))) int32x4_t vreinterpretq_s32_bf16(bfloat16x8_t __p0) {
	64101	int32x4_t __ret;
	64102	__ret = __builtin_bit_cast(int32x4_t, __p0);
	64103	return __ret;
	64104	}
	64105	__ai __attribute__((target("neon"))) int64x2_t vreinterpretq_s64_bf16(bfloat16x8_t __p0) {
	64106	int64x2_t __ret;
	64107	__ret = __builtin_bit_cast(int64x2_t, __p0);
	64108	return __ret;
	64109	}
	64110	__ai __attribute__((target("neon"))) int16x8_t vreinterpretq_s16_bf16(bfloat16x8_t __p0) {
	64111	int16x8_t __ret;
	64112	__ret = __builtin_bit_cast(int16x8_t, __p0);
	64113	return __ret;
	64114	}
	64115	__ai __attribute__((target("neon"))) uint8x8_t vreinterpret_u8_bf16(bfloat16x4_t __p0) {
	64116	uint8x8_t __ret;
	64117	__ret = __builtin_bit_cast(uint8x8_t, __p0);
	64118	return __ret;
	64119	}
	64120	__ai __attribute__((target("neon"))) uint32x2_t vreinterpret_u32_bf16(bfloat16x4_t __p0) {
	64121	uint32x2_t __ret;
	64122	__ret = __builtin_bit_cast(uint32x2_t, __p0);
	64123	return __ret;
	64124	}
	64125	__ai __attribute__((target("neon"))) uint64x1_t vreinterpret_u64_bf16(bfloat16x4_t __p0) {
	64126	uint64x1_t __ret;
	64127	__ret = __builtin_bit_cast(uint64x1_t, __p0);
	64128	return __ret;
	64129	}
	64130	__ai __attribute__((target("neon"))) uint16x4_t vreinterpret_u16_bf16(bfloat16x4_t __p0) {
	64131	uint16x4_t __ret;
	64132	__ret = __builtin_bit_cast(uint16x4_t, __p0);
	64133	return __ret;
	64134	}
	64135	__ai __attribute__((target("neon"))) int8x8_t vreinterpret_s8_bf16(bfloat16x4_t __p0) {
	64136	int8x8_t __ret;
	64137	__ret = __builtin_bit_cast(int8x8_t, __p0);
	64138	return __ret;
	64139	}
	64140	__ai __attribute__((target("neon"))) float64x1_t vreinterpret_f64_bf16(bfloat16x4_t __p0) {
	64141	float64x1_t __ret;
	64142	__ret = __builtin_bit_cast(float64x1_t, __p0);
	64143	return __ret;
	64144	}
	64145	__ai __attribute__((target("neon"))) float32x2_t vreinterpret_f32_bf16(bfloat16x4_t __p0) {
	64146	float32x2_t __ret;
	64147	__ret = __builtin_bit_cast(float32x2_t, __p0);
	64148	return __ret;
	64149	}
	64150	__ai __attribute__((target("neon"))) float16x4_t vreinterpret_f16_bf16(bfloat16x4_t __p0) {
	64151	float16x4_t __ret;
	64152	__ret = __builtin_bit_cast(float16x4_t, __p0);
	64153	return __ret;
	64154	}
	64155	__ai __attribute__((target("neon"))) int32x2_t vreinterpret_s32_bf16(bfloat16x4_t __p0) {
	64156	int32x2_t __ret;
	64157	__ret = __builtin_bit_cast(int32x2_t, __p0);
	64158	return __ret;
	64159	}
	64160	__ai __attribute__((target("neon"))) int64x1_t vreinterpret_s64_bf16(bfloat16x4_t __p0) {
	64161	int64x1_t __ret;
	64162	__ret = __builtin_bit_cast(int64x1_t, __p0);
	64163	return __ret;
	64164	}
	64165	__ai __attribute__((target("neon"))) int16x4_t vreinterpret_s16_bf16(bfloat16x4_t __p0) {
	64166	int16x4_t __ret;
	64167	__ret = __builtin_bit_cast(int16x4_t, __p0);
	64168	return __ret;
	64169	}
	64170	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p8(poly8x16_t __p0) {
	64171	bfloat16x8_t __ret;
	64172	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64173	return __ret;
	64174	}
	64175	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p128(poly128_t __p0) {
	64176	bfloat16x8_t __ret;
	64177	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64178	return __ret;
	64179	}
	64180	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p64(poly64x2_t __p0) {
	64181	bfloat16x8_t __ret;
	64182	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64183	return __ret;
	64184	}
	64185	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_p16(poly16x8_t __p0) {
	64186	bfloat16x8_t __ret;
	64187	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64188	return __ret;
	64189	}
	64190	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u8(uint8x16_t __p0) {
	64191	bfloat16x8_t __ret;
	64192	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64193	return __ret;
	64194	}
	64195	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u32(uint32x4_t __p0) {
	64196	bfloat16x8_t __ret;
	64197	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64198	return __ret;
	64199	}
	64200	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u64(uint64x2_t __p0) {
	64201	bfloat16x8_t __ret;
	64202	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64203	return __ret;
	64204	}
	64205	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_u16(uint16x8_t __p0) {
	64206	bfloat16x8_t __ret;
	64207	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64208	return __ret;
	64209	}
	64210	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s8(int8x16_t __p0) {
	64211	bfloat16x8_t __ret;
	64212	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64213	return __ret;
	64214	}
	64215	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_f64(float64x2_t __p0) {
	64216	bfloat16x8_t __ret;
	64217	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64218	return __ret;
	64219	}
	64220	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_f32(float32x4_t __p0) {
	64221	bfloat16x8_t __ret;
	64222	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64223	return __ret;
	64224	}
	64225	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_f16(float16x8_t __p0) {
	64226	bfloat16x8_t __ret;
	64227	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64228	return __ret;
	64229	}
	64230	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s32(int32x4_t __p0) {
	64231	bfloat16x8_t __ret;
	64232	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64233	return __ret;
	64234	}
	64235	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s64(int64x2_t __p0) {
	64236	bfloat16x8_t __ret;
	64237	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64238	return __ret;
	64239	}
	64240	__ai __attribute__((target("neon"))) bfloat16x8_t vreinterpretq_bf16_s16(int16x8_t __p0) {
	64241	bfloat16x8_t __ret;
	64242	__ret = __builtin_bit_cast(bfloat16x8_t, __p0);
	64243	return __ret;
	64244	}
	64245	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_p8(poly8x8_t __p0) {
	64246	bfloat16x4_t __ret;
	64247	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64248	return __ret;
	64249	}
	64250	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_p64(poly64x1_t __p0) {
	64251	bfloat16x4_t __ret;
	64252	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64253	return __ret;
	64254	}
	64255	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_p16(poly16x4_t __p0) {
	64256	bfloat16x4_t __ret;
	64257	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64258	return __ret;
	64259	}
	64260	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u8(uint8x8_t __p0) {
	64261	bfloat16x4_t __ret;
	64262	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64263	return __ret;
	64264	}
	64265	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u32(uint32x2_t __p0) {
	64266	bfloat16x4_t __ret;
	64267	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64268	return __ret;
	64269	}
	64270	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u64(uint64x1_t __p0) {
	64271	bfloat16x4_t __ret;
	64272	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64273	return __ret;
	64274	}
	64275	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_u16(uint16x4_t __p0) {
	64276	bfloat16x4_t __ret;
	64277	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64278	return __ret;
	64279	}
	64280	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s8(int8x8_t __p0) {
	64281	bfloat16x4_t __ret;
	64282	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64283	return __ret;
	64284	}
	64285	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_f64(float64x1_t __p0) {
	64286	bfloat16x4_t __ret;
	64287	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64288	return __ret;
	64289	}
	64290	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_f32(float32x2_t __p0) {
	64291	bfloat16x4_t __ret;
	64292	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64293	return __ret;
	64294	}
	64295	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_f16(float16x4_t __p0) {
	64296	bfloat16x4_t __ret;
	64297	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64298	return __ret;
	64299	}
	64300	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s32(int32x2_t __p0) {
	64301	bfloat16x4_t __ret;
	64302	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64303	return __ret;
	64304	}
	64305	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s64(int64x1_t __p0) {
	64306	bfloat16x4_t __ret;
	64307	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64308	return __ret;
	64309	}
	64310	__ai __attribute__((target("neon"))) bfloat16x4_t vreinterpret_bf16_s16(int16x4_t __p0) {
	64311	bfloat16x4_t __ret;
	64312	__ret = __builtin_bit_cast(bfloat16x4_t, __p0);
	64313	return __ret;
	64314	}
64147	64315	__ai __attribute__((target("neon"))) uint64_t vrshld_u64(uint64_t __p0, int64_t __p1) {
64148	64316	uint64_t __ret;
64149	64317	__ret = __builtin_bit_cast(uint64_t, __builtin_neon_vrshld_u64(__p0, __p1));

lib/include/arm_sme.h+12

...	...	@@ -3732,6 +3732,18 @@ __ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svzero_za64_vg4x2)))
3732	3732	void svzero_za64_vg4x2(uint32_t);
3733	3733	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svzero_za64_vg4x4)))
3734	3734	void svzero_za64_vg4x4(uint32_t);
	3735	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svluti6_zt_u8)))
	3736	svuint8_t svluti6_zt_u8(uint64_t, svuint8_t);
	3737	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svluti6_zt_s8)))
	3738	svint8_t svluti6_zt_s8(uint64_t, svuint8_t);
	3739	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svluti6_zt_mf8)))
	3740	svmfloat8_t svluti6_zt_mf8(uint64_t, svuint8_t);
	3741	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svluti6_zt_u8_x4)))
	3742	svuint8x4_t svluti6_zt_u8_x4(uint64_t, svuint8x3_t);
	3743	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svluti6_zt_s8_x4)))
	3744	svint8x4_t svluti6_zt_s8_x4(uint64_t, svuint8x3_t);
	3745	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sme_svluti6_zt_mf8_x4)))
	3746	svmfloat8x4_t svluti6_zt_mf8_x4(uint64_t, svuint8x3_t);
3735	3747	#ifdef __cplusplus
3736	3748	} // extern "C"
3737	3749	#endif

lib/include/arm_sve.h+420

...	...	@@ -4697,6 +4697,38 @@ __aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svmul_f32_x4)))
4697	4697	svfloat32x4_t svmul(svfloat32x4_t, svfloat32x4_t);
4698	4698	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svmul_f16_x4)))
4699	4699	svfloat16x4_t svmul(svfloat16x4_t, svfloat16x4_t);
	4700	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_u16_x4_u16_x2_u8_x2)))
	4701	svuint16x4_t svluti6_lane_u16_x4_u16_x2_u8_x2(svuint16x2_t, svuint8x2_t, uint64_t);
	4702	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_bf16_x4_bf16_x2_u8_x2)))
	4703	svbfloat16x4_t svluti6_lane_bf16_x4_bf16_x2_u8_x2(svbfloat16x2_t, svuint8x2_t, uint64_t);
	4704	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_f16_x4_f16_x2_u8_x2)))
	4705	svfloat16x4_t svluti6_lane_f16_x4_f16_x2_u8_x2(svfloat16x2_t, svuint8x2_t, uint64_t);
	4706	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_s16_x4_s16_x2_u8_x2)))
	4707	svint16x4_t svluti6_lane_s16_x4_s16_x2_u8_x2(svint16x2_t, svuint8x2_t, uint64_t);
	4708	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_u16_x4_u16_x2_u8_x3)))
	4709	svuint16x4_t svluti6_lane_u16_x4_u16_x2_u8_x3(svuint16x2_t, svuint8x3_t, uint64_t);
	4710	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_bf16_x4_bf16_x2_u8_x3)))
	4711	svbfloat16x4_t svluti6_lane_bf16_x4_bf16_x2_u8_x3(svbfloat16x2_t, svuint8x3_t, uint64_t);
	4712	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_f16_x4_f16_x2_u8_x3)))
	4713	svfloat16x4_t svluti6_lane_f16_x4_f16_x2_u8_x3(svfloat16x2_t, svuint8x3_t, uint64_t);
	4714	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_s16_x4_s16_x2_u8_x3)))
	4715	svint16x4_t svluti6_lane_s16_x4_s16_x2_u8_x3(svint16x2_t, svuint8x3_t, uint64_t);
	4716	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_u16_x4_u16_x2_u8_x2)))
	4717	svuint16x4_t svluti6_lane_u16_x4(svuint16x2_t, svuint8x2_t, uint64_t);
	4718	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_bf16_x4_bf16_x2_u8_x2)))
	4719	svbfloat16x4_t svluti6_lane_bf16_x4(svbfloat16x2_t, svuint8x2_t, uint64_t);
	4720	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_f16_x4_f16_x2_u8_x2)))
	4721	svfloat16x4_t svluti6_lane_f16_x4(svfloat16x2_t, svuint8x2_t, uint64_t);
	4722	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_s16_x4_s16_x2_u8_x2)))
	4723	svint16x4_t svluti6_lane_s16_x4(svint16x2_t, svuint8x2_t, uint64_t);
	4724	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_u16_x4_u16_x2_u8_x3)))
	4725	svuint16x4_t svluti6_lane_u16_x4(svuint16x2_t, svuint8x3_t, uint64_t);
	4726	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_bf16_x4_bf16_x2_u8_x3)))
	4727	svbfloat16x4_t svluti6_lane_bf16_x4(svbfloat16x2_t, svuint8x3_t, uint64_t);
	4728	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_f16_x4_f16_x2_u8_x3)))
	4729	svfloat16x4_t svluti6_lane_f16_x4(svfloat16x2_t, svuint8x3_t, uint64_t);
	4730	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_s16_x4_s16_x2_u8_x3)))
	4731	svint16x4_t svluti6_lane_s16_x4(svint16x2_t, svuint8x3_t, uint64_t);
4700	4732	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svadda_f64)))
4701	4733	float64_t svadda_f64(svbool_t, float64_t, svfloat64_t);
4702	4734	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svadda_f32)))
...	...	@@ -7223,6 +7255,12 @@ __ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcreate2_b)))
7223	7255	svboolx2_t svcreate2_b(svbool_t, svbool_t);
7224	7256	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcreate4_b)))
7225	7257	svboolx4_t svcreate4_b(svbool_t, svbool_t, svbool_t, svbool_t);
	7258	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_f32_f16)))
	7259	svfloat32_t svdot_n_f32_f16(svfloat32_t, svfloat16_t, float16_t);
	7260	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_s32_s16)))
	7261	svint32_t svdot_n_s32_s16(svint32_t, svint16_t, int16_t);
	7262	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_u32_u16)))
	7263	svuint32_t svdot_n_u32_u16(svuint32_t, svuint16_t, uint16_t);
7226	7264	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_f32_f16)))
7227	7265	svfloat32_t svdot_f32_f16(svfloat32_t, svfloat16_t, svfloat16_t);
7228	7266	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_s32_s16)))
...	...	@@ -7341,6 +7379,12 @@ __aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcreate2_b)))
7341	7379	svboolx2_t svcreate2(svbool_t, svbool_t);
7342	7380	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcreate4_b)))
7343	7381	svboolx4_t svcreate4(svbool_t, svbool_t, svbool_t, svbool_t);
	7382	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_f32_f16)))
	7383	svfloat32_t svdot(svfloat32_t, svfloat16_t, float16_t);
	7384	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_s32_s16)))
	7385	svint32_t svdot(svint32_t, svint16_t, int16_t);
	7386	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_u32_u16)))
	7387	svuint32_t svdot(svuint32_t, svuint16_t, uint16_t);
7344	7388	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_f32_f16)))
7345	7389	svfloat32_t svdot(svfloat32_t, svfloat16_t, svfloat16_t);
7346	7390	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_s32_s16)))
...	...	@@ -9049,6 +9093,346 @@ __aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svexpand_mf8)))
9049	9093	svmfloat8_t svexpand(svbool_t, svmfloat8_t);
9050	9094	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svexpand_s16)))
9051	9095	svint16_t svexpand(svbool_t, svint16_t);
	9096	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_s32)))
	9097	svint32_t svabal_n_s32(svint32_t, svint16_t, int16_t);
	9098	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_s64)))
	9099	svint64_t svabal_n_s64(svint64_t, svint32_t, int32_t);
	9100	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_s16)))
	9101	svint16_t svabal_n_s16(svint16_t, svint8_t, int8_t);
	9102	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_u32)))
	9103	svuint32_t svabal_n_u32(svuint32_t, svuint16_t, uint16_t);
	9104	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_u64)))
	9105	svuint64_t svabal_n_u64(svuint64_t, svuint32_t, uint32_t);
	9106	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_u16)))
	9107	svuint16_t svabal_n_u16(svuint16_t, svuint8_t, uint8_t);
	9108	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_s32)))
	9109	svint32_t svabal_s32(svint32_t, svint16_t, svint16_t);
	9110	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_s64)))
	9111	svint64_t svabal_s64(svint64_t, svint32_t, svint32_t);
	9112	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_s16)))
	9113	svint16_t svabal_s16(svint16_t, svint8_t, svint8_t);
	9114	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_u32)))
	9115	svuint32_t svabal_u32(svuint32_t, svuint16_t, svuint16_t);
	9116	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_u64)))
	9117	svuint64_t svabal_u64(svuint64_t, svuint32_t, svuint32_t);
	9118	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_u16)))
	9119	svuint16_t svabal_u16(svuint16_t, svuint8_t, svuint8_t);
	9120	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u8)))
	9121	svuint8_t svaddqp_u8(svuint8_t, svuint8_t);
	9122	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u32)))
	9123	svuint32_t svaddqp_u32(svuint32_t, svuint32_t);
	9124	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u64)))
	9125	svuint64_t svaddqp_u64(svuint64_t, svuint64_t);
	9126	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u16)))
	9127	svuint16_t svaddqp_u16(svuint16_t, svuint16_t);
	9128	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s8)))
	9129	svint8_t svaddqp_s8(svint8_t, svint8_t);
	9130	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s32)))
	9131	svint32_t svaddqp_s32(svint32_t, svint32_t);
	9132	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s64)))
	9133	svint64_t svaddqp_s64(svint64_t, svint64_t);
	9134	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s16)))
	9135	svint16_t svaddqp_s16(svint16_t, svint16_t);
	9136	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u8)))
	9137	svuint8_t svaddsubp_u8(svuint8_t, svuint8_t);
	9138	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u32)))
	9139	svuint32_t svaddsubp_u32(svuint32_t, svuint32_t);
	9140	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u64)))
	9141	svuint64_t svaddsubp_u64(svuint64_t, svuint64_t);
	9142	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u16)))
	9143	svuint16_t svaddsubp_u16(svuint16_t, svuint16_t);
	9144	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s8)))
	9145	svint8_t svaddsubp_s8(svint8_t, svint8_t);
	9146	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s32)))
	9147	svint32_t svaddsubp_s32(svint32_t, svint32_t);
	9148	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s64)))
	9149	svint64_t svaddsubp_s64(svint64_t, svint64_t);
	9150	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s16)))
	9151	svint16_t svaddsubp_s16(svint16_t, svint16_t);
	9152	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f64_s32)))
	9153	svfloat64_t svcvtb_f64_s32(svint32_t);
	9154	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f32_s16)))
	9155	svfloat32_t svcvtb_f32_s16(svint16_t);
	9156	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f16_s8)))
	9157	svfloat16_t svcvtb_f16_s8(svint8_t);
	9158	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f64_u32)))
	9159	svfloat64_t svcvtb_f64_u32(svuint32_t);
	9160	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f32_u16)))
	9161	svfloat32_t svcvtb_f32_u16(svuint16_t);
	9162	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f16_u8)))
	9163	svfloat16_t svcvtb_f16_u8(svuint8_t);
	9164	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_s32_f64_x2)))
	9165	svint32_t svcvtn_s32_f64_x2(svfloat64x2_t);
	9166	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_s16_f32_x2)))
	9167	svint16_t svcvtn_s16_f32_x2(svfloat32x2_t);
	9168	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_s8_f16_x2)))
	9169	svint8_t svcvtn_s8_f16_x2(svfloat16x2_t);
	9170	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_u32_f64_x2)))
	9171	svuint32_t svcvtn_u32_f64_x2(svfloat64x2_t);
	9172	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_u16_f32_x2)))
	9173	svuint16_t svcvtn_u16_f32_x2(svfloat32x2_t);
	9174	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_u8_f16_x2)))
	9175	svuint8_t svcvtn_u8_f16_x2(svfloat16x2_t);
	9176	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f64_s32)))
	9177	svfloat64_t svcvtt_f64_s32(svint32_t);
	9178	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f32_s16)))
	9179	svfloat32_t svcvtt_f32_s16(svint16_t);
	9180	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f16_s8)))
	9181	svfloat16_t svcvtt_f16_s8(svint8_t);
	9182	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f64_u32)))
	9183	svfloat64_t svcvtt_f64_u32(svuint32_t);
	9184	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f32_u16)))
	9185	svfloat32_t svcvtt_f32_u16(svuint16_t);
	9186	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f16_u8)))
	9187	svfloat16_t svcvtt_f16_u8(svuint8_t);
	9188	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_s16_s8)))
	9189	svint16_t svdot_n_s16_s8(svint16_t, svint8_t, int8_t);
	9190	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_u16_u8)))
	9191	svuint16_t svdot_n_u16_u8(svuint16_t, svuint8_t, uint8_t);
	9192	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_s16_s8)))
	9193	svint16_t svdot_s16_s8(svint16_t, svint8_t, svint8_t);
	9194	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_u16_u8)))
	9195	svuint16_t svdot_u16_u8(svuint16_t, svuint8_t, svuint8_t);
	9196	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_lane_s16_s8)))
	9197	svint16_t svdot_lane_s16_s8(svint16_t, svint8_t, svint8_t, uint64_t);
	9198	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_lane_u16_u8)))
	9199	svuint16_t svdot_lane_u16_u8(svuint16_t, svuint8_t, svuint8_t, uint64_t);
	9200	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqrshrn_n_s8_s16_x2)))
	9201	svint8_t svqrshrn_n_s8_s16_x2(svint16x2_t, uint64_t);
	9202	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqrshrn_n_u8_u16_x2)))
	9203	svuint8_t svqrshrn_n_u8_u16_x2(svuint16x2_t, uint64_t);
	9204	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqrshrun_n_u8_s16_x2)))
	9205	svuint8_t svqrshrun_n_u8_s16_x2(svint16x2_t, uint64_t);
	9206	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_s16_s32_x2)))
	9207	svint16_t svqshrn_n_s16_s32_x2(svint32x2_t, uint64_t);
	9208	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_s8_s16_x2)))
	9209	svint8_t svqshrn_n_s8_s16_x2(svint16x2_t, uint64_t);
	9210	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_u16_u32_x2)))
	9211	svuint16_t svqshrn_n_u16_u32_x2(svuint32x2_t, uint64_t);
	9212	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_u8_u16_x2)))
	9213	svuint8_t svqshrn_n_u8_u16_x2(svuint16x2_t, uint64_t);
	9214	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrun_n_u16_s32_x2)))
	9215	svuint16_t svqshrun_n_u16_s32_x2(svint32x2_t, uint64_t);
	9216	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrun_n_u8_s16_x2)))
	9217	svuint8_t svqshrun_n_u8_s16_x2(svint16x2_t, uint64_t);
	9218	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u8_m)))
	9219	svuint8_t svsubp_u8_m(svbool_t, svuint8_t, svuint8_t);
	9220	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u32_m)))
	9221	svuint32_t svsubp_u32_m(svbool_t, svuint32_t, svuint32_t);
	9222	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u64_m)))
	9223	svuint64_t svsubp_u64_m(svbool_t, svuint64_t, svuint64_t);
	9224	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u16_m)))
	9225	svuint16_t svsubp_u16_m(svbool_t, svuint16_t, svuint16_t);
	9226	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s8_m)))
	9227	svint8_t svsubp_s8_m(svbool_t, svint8_t, svint8_t);
	9228	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s32_m)))
	9229	svint32_t svsubp_s32_m(svbool_t, svint32_t, svint32_t);
	9230	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s64_m)))
	9231	svint64_t svsubp_s64_m(svbool_t, svint64_t, svint64_t);
	9232	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s16_m)))
	9233	svint16_t svsubp_s16_m(svbool_t, svint16_t, svint16_t);
	9234	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u8_x)))
	9235	svuint8_t svsubp_u8_x(svbool_t, svuint8_t, svuint8_t);
	9236	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u32_x)))
	9237	svuint32_t svsubp_u32_x(svbool_t, svuint32_t, svuint32_t);
	9238	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u64_x)))
	9239	svuint64_t svsubp_u64_x(svbool_t, svuint64_t, svuint64_t);
	9240	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u16_x)))
	9241	svuint16_t svsubp_u16_x(svbool_t, svuint16_t, svuint16_t);
	9242	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s8_x)))
	9243	svint8_t svsubp_s8_x(svbool_t, svint8_t, svint8_t);
	9244	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s32_x)))
	9245	svint32_t svsubp_s32_x(svbool_t, svint32_t, svint32_t);
	9246	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s64_x)))
	9247	svint64_t svsubp_s64_x(svbool_t, svint64_t, svint64_t);
	9248	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s16_x)))
	9249	svint16_t svsubp_s16_x(svbool_t, svint16_t, svint16_t);
	9250	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u8_z)))
	9251	svuint8_t svsubp_u8_z(svbool_t, svuint8_t, svuint8_t);
	9252	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u32_z)))
	9253	svuint32_t svsubp_u32_z(svbool_t, svuint32_t, svuint32_t);
	9254	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u64_z)))
	9255	svuint64_t svsubp_u64_z(svbool_t, svuint64_t, svuint64_t);
	9256	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u16_z)))
	9257	svuint16_t svsubp_u16_z(svbool_t, svuint16_t, svuint16_t);
	9258	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s8_z)))
	9259	svint8_t svsubp_s8_z(svbool_t, svint8_t, svint8_t);
	9260	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s32_z)))
	9261	svint32_t svsubp_s32_z(svbool_t, svint32_t, svint32_t);
	9262	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s64_z)))
	9263	svint64_t svsubp_s64_z(svbool_t, svint64_t, svint64_t);
	9264	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s16_z)))
	9265	svint16_t svsubp_s16_z(svbool_t, svint16_t, svint16_t);
	9266	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_s32)))
	9267	svint32_t svabal(svint32_t, svint16_t, int16_t);
	9268	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_s64)))
	9269	svint64_t svabal(svint64_t, svint32_t, int32_t);
	9270	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_s16)))
	9271	svint16_t svabal(svint16_t, svint8_t, int8_t);
	9272	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_u32)))
	9273	svuint32_t svabal(svuint32_t, svuint16_t, uint16_t);
	9274	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_u64)))
	9275	svuint64_t svabal(svuint64_t, svuint32_t, uint32_t);
	9276	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_n_u16)))
	9277	svuint16_t svabal(svuint16_t, svuint8_t, uint8_t);
	9278	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_s32)))
	9279	svint32_t svabal(svint32_t, svint16_t, svint16_t);
	9280	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_s64)))
	9281	svint64_t svabal(svint64_t, svint32_t, svint32_t);
	9282	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_s16)))
	9283	svint16_t svabal(svint16_t, svint8_t, svint8_t);
	9284	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_u32)))
	9285	svuint32_t svabal(svuint32_t, svuint16_t, svuint16_t);
	9286	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_u64)))
	9287	svuint64_t svabal(svuint64_t, svuint32_t, svuint32_t);
	9288	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabal_u16)))
	9289	svuint16_t svabal(svuint16_t, svuint8_t, svuint8_t);
	9290	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u8)))
	9291	svuint8_t svaddqp(svuint8_t, svuint8_t);
	9292	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u32)))
	9293	svuint32_t svaddqp(svuint32_t, svuint32_t);
	9294	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u64)))
	9295	svuint64_t svaddqp(svuint64_t, svuint64_t);
	9296	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_u16)))
	9297	svuint16_t svaddqp(svuint16_t, svuint16_t);
	9298	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s8)))
	9299	svint8_t svaddqp(svint8_t, svint8_t);
	9300	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s32)))
	9301	svint32_t svaddqp(svint32_t, svint32_t);
	9302	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s64)))
	9303	svint64_t svaddqp(svint64_t, svint64_t);
	9304	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddqp_s16)))
	9305	svint16_t svaddqp(svint16_t, svint16_t);
	9306	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u8)))
	9307	svuint8_t svaddsubp(svuint8_t, svuint8_t);
	9308	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u32)))
	9309	svuint32_t svaddsubp(svuint32_t, svuint32_t);
	9310	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u64)))
	9311	svuint64_t svaddsubp(svuint64_t, svuint64_t);
	9312	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_u16)))
	9313	svuint16_t svaddsubp(svuint16_t, svuint16_t);
	9314	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s8)))
	9315	svint8_t svaddsubp(svint8_t, svint8_t);
	9316	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s32)))
	9317	svint32_t svaddsubp(svint32_t, svint32_t);
	9318	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s64)))
	9319	svint64_t svaddsubp(svint64_t, svint64_t);
	9320	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaddsubp_s16)))
	9321	svint16_t svaddsubp(svint16_t, svint16_t);
	9322	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f64_s32)))
	9323	svfloat64_t svcvtb_f64(svint32_t);
	9324	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f32_s16)))
	9325	svfloat32_t svcvtb_f32(svint16_t);
	9326	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f16_s8)))
	9327	svfloat16_t svcvtb_f16(svint8_t);
	9328	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f64_u32)))
	9329	svfloat64_t svcvtb_f64(svuint32_t);
	9330	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f32_u16)))
	9331	svfloat32_t svcvtb_f32(svuint16_t);
	9332	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtb_f16_u8)))
	9333	svfloat16_t svcvtb_f16(svuint8_t);
	9334	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_s32_f64_x2)))
	9335	svint32_t svcvtn_s32(svfloat64x2_t);
	9336	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_s16_f32_x2)))
	9337	svint16_t svcvtn_s16(svfloat32x2_t);
	9338	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_s8_f16_x2)))
	9339	svint8_t svcvtn_s8(svfloat16x2_t);
	9340	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_u32_f64_x2)))
	9341	svuint32_t svcvtn_u32(svfloat64x2_t);
	9342	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_u16_f32_x2)))
	9343	svuint16_t svcvtn_u16(svfloat32x2_t);
	9344	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtn_u8_f16_x2)))
	9345	svuint8_t svcvtn_u8(svfloat16x2_t);
	9346	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f64_s32)))
	9347	svfloat64_t svcvtt_f64(svint32_t);
	9348	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f32_s16)))
	9349	svfloat32_t svcvtt_f32(svint16_t);
	9350	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f16_s8)))
	9351	svfloat16_t svcvtt_f16(svint8_t);
	9352	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f64_u32)))
	9353	svfloat64_t svcvtt_f64(svuint32_t);
	9354	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f32_u16)))
	9355	svfloat32_t svcvtt_f32(svuint16_t);
	9356	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svcvtt_f16_u8)))
	9357	svfloat16_t svcvtt_f16(svuint8_t);
	9358	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_s16_s8)))
	9359	svint16_t svdot(svint16_t, svint8_t, int8_t);
	9360	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_n_u16_u8)))
	9361	svuint16_t svdot(svuint16_t, svuint8_t, uint8_t);
	9362	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_s16_s8)))
	9363	svint16_t svdot(svint16_t, svint8_t, svint8_t);
	9364	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_u16_u8)))
	9365	svuint16_t svdot(svuint16_t, svuint8_t, svuint8_t);
	9366	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_lane_s16_s8)))
	9367	svint16_t svdot_lane(svint16_t, svint8_t, svint8_t, uint64_t);
	9368	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svdot_lane_u16_u8)))
	9369	svuint16_t svdot_lane(svuint16_t, svuint8_t, svuint8_t, uint64_t);
	9370	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqrshrn_n_s8_s16_x2)))
	9371	svint8_t svqrshrn_s8(svint16x2_t, uint64_t);
	9372	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqrshrn_n_u8_u16_x2)))
	9373	svuint8_t svqrshrn_u8(svuint16x2_t, uint64_t);
	9374	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqrshrun_n_u8_s16_x2)))
	9375	svuint8_t svqrshrun_u8(svint16x2_t, uint64_t);
	9376	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_s16_s32_x2)))
	9377	svint16_t svqshrn_s16(svint32x2_t, uint64_t);
	9378	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_s8_s16_x2)))
	9379	svint8_t svqshrn_s8(svint16x2_t, uint64_t);
	9380	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_u16_u32_x2)))
	9381	svuint16_t svqshrn_u16(svuint32x2_t, uint64_t);
	9382	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrn_n_u8_u16_x2)))
	9383	svuint8_t svqshrn_u8(svuint16x2_t, uint64_t);
	9384	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrun_n_u16_s32_x2)))
	9385	svuint16_t svqshrun_u16(svint32x2_t, uint64_t);
	9386	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svqshrun_n_u8_s16_x2)))
	9387	svuint8_t svqshrun_u8(svint16x2_t, uint64_t);
	9388	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u8_m)))
	9389	svuint8_t svsubp_m(svbool_t, svuint8_t, svuint8_t);
	9390	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u32_m)))
	9391	svuint32_t svsubp_m(svbool_t, svuint32_t, svuint32_t);
	9392	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u64_m)))
	9393	svuint64_t svsubp_m(svbool_t, svuint64_t, svuint64_t);
	9394	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u16_m)))
	9395	svuint16_t svsubp_m(svbool_t, svuint16_t, svuint16_t);
	9396	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s8_m)))
	9397	svint8_t svsubp_m(svbool_t, svint8_t, svint8_t);
	9398	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s32_m)))
	9399	svint32_t svsubp_m(svbool_t, svint32_t, svint32_t);
	9400	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s64_m)))
	9401	svint64_t svsubp_m(svbool_t, svint64_t, svint64_t);
	9402	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s16_m)))
	9403	svint16_t svsubp_m(svbool_t, svint16_t, svint16_t);
	9404	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u8_x)))
	9405	svuint8_t svsubp_x(svbool_t, svuint8_t, svuint8_t);
	9406	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u32_x)))
	9407	svuint32_t svsubp_x(svbool_t, svuint32_t, svuint32_t);
	9408	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u64_x)))
	9409	svuint64_t svsubp_x(svbool_t, svuint64_t, svuint64_t);
	9410	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u16_x)))
	9411	svuint16_t svsubp_x(svbool_t, svuint16_t, svuint16_t);
	9412	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s8_x)))
	9413	svint8_t svsubp_x(svbool_t, svint8_t, svint8_t);
	9414	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s32_x)))
	9415	svint32_t svsubp_x(svbool_t, svint32_t, svint32_t);
	9416	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s64_x)))
	9417	svint64_t svsubp_x(svbool_t, svint64_t, svint64_t);
	9418	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s16_x)))
	9419	svint16_t svsubp_x(svbool_t, svint16_t, svint16_t);
	9420	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u8_z)))
	9421	svuint8_t svsubp_z(svbool_t, svuint8_t, svuint8_t);
	9422	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u32_z)))
	9423	svuint32_t svsubp_z(svbool_t, svuint32_t, svuint32_t);
	9424	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u64_z)))
	9425	svuint64_t svsubp_z(svbool_t, svuint64_t, svuint64_t);
	9426	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_u16_z)))
	9427	svuint16_t svsubp_z(svbool_t, svuint16_t, svuint16_t);
	9428	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s8_z)))
	9429	svint8_t svsubp_z(svbool_t, svint8_t, svint8_t);
	9430	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s32_z)))
	9431	svint32_t svsubp_z(svbool_t, svint32_t, svint32_t);
	9432	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s64_z)))
	9433	svint64_t svsubp_z(svbool_t, svint64_t, svint64_t);
	9434	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsubp_s16_z)))
	9435	svint16_t svsubp_z(svbool_t, svint16_t, svint16_t);
9052	9436	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaba_n_s8)))
9053	9437	svint8_t svaba_n_s8(svint8_t, svint8_t, int8_t);
9054	9438	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svaba_n_s32)))
...	...	@@ -16581,6 +16965,10 @@ __aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsub_bf16_x)))
16581	16965	svbfloat16_t svsub_x(svbool_t, svbfloat16_t, svbfloat16_t);
16582	16966	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svsub_bf16_z)))
16583	16967	svbfloat16_t svsub_z(svbool_t, svbfloat16_t, svbfloat16_t);
	16968	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svmmla_bf16)))
	16969	svbfloat16_t svmmla_bf16(svbfloat16_t, svbfloat16_t, svbfloat16_t);
	16970	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svmmla_bf16)))
	16971	svbfloat16_t svmmla(svbfloat16_t, svbfloat16_t, svbfloat16_t);
16584	16972	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svscale_n_bf16_m)))
16585	16973	svbfloat16_t svscale_n_bf16_m(svbool_t, svbfloat16_t, int16_t);
16586	16974	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svscale_n_bf16_x)))
...	...	@@ -19415,6 +19803,38 @@ __aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svwhilelt_c64_s64))
19415	19803	svcount_t svwhilelt_c64(int64_t, int64_t, uint64_t);
19416	19804	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svwhilelt_c16_s64)))
19417	19805	svcount_t svwhilelt_c16(int64_t, int64_t, uint64_t);
	19806	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svmmla_f16)))
	19807	svfloat16_t svmmla_f16(svfloat16_t, svfloat16_t, svfloat16_t);
	19808	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svmmla_f16)))
	19809	svfloat16_t svmmla(svfloat16_t, svfloat16_t, svfloat16_t);
	19810	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_u8_x2)))
	19811	svuint8_t svluti6_u8_x2(svuint8x2_t, svuint8_t);
	19812	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_s8_x2)))
	19813	svint8_t svluti6_s8_x2(svint8x2_t, svuint8_t);
	19814	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_mf8_x2)))
	19815	svmfloat8_t svluti6_mf8_x2(svmfloat8x2_t, svuint8_t);
	19816	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_u8_x2)))
	19817	svuint8_t svluti6(svuint8x2_t, svuint8_t);
	19818	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_s8_x2)))
	19819	svint8_t svluti6(svint8x2_t, svuint8_t);
	19820	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_mf8_x2)))
	19821	svmfloat8_t svluti6(svmfloat8x2_t, svuint8_t);
	19822	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_u16_x2)))
	19823	svuint16_t svluti6_lane_u16_x2(svuint16x2_t, svuint8_t, uint64_t);
	19824	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_bf16_x2)))
	19825	svbfloat16_t svluti6_lane_bf16_x2(svbfloat16x2_t, svuint8_t, uint64_t);
	19826	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_f16_x2)))
	19827	svfloat16_t svluti6_lane_f16_x2(svfloat16x2_t, svuint8_t, uint64_t);
	19828	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_s16_x2)))
	19829	svint16_t svluti6_lane_s16_x2(svint16x2_t, svuint8_t, uint64_t);
	19830	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_u16_x2)))
	19831	svuint16_t svluti6_lane(svuint16x2_t, svuint8_t, uint64_t);
	19832	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_bf16_x2)))
	19833	svbfloat16_t svluti6_lane(svbfloat16x2_t, svuint8_t, uint64_t);
	19834	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_f16_x2)))
	19835	svfloat16_t svluti6_lane(svfloat16x2_t, svuint8_t, uint64_t);
	19836	__aio __attribute__((__clang_arm_builtin_alias(__builtin_sve_svluti6_lane_s16_x2)))
	19837	svint16_t svluti6_lane(svint16x2_t, svuint8_t, uint64_t);
19418	19838	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabd_n_f64_m)))
19419	19839	svfloat64_t svabd_n_f64_m(svbool_t, svfloat64_t, float64_t);
19420	19840	__ai __attribute__((__clang_arm_builtin_alias(__builtin_sve_svabd_n_f32_m)))

lib/include/avx2intrin.h+4-5

...	...	@@ -1810,10 +1810,9 @@ _mm256_or_si256(__m256i __a, __m256i __b)
1810	1810	/// \param __b
1811	1811	/// A 256-bit integer vector.
1812	1812	/// \returns A 256-bit integer vector containing the result.
1813		static __inline__ __m256i __DEFAULT_FN_ATTRS256
1814		_mm256_sad_epu8(__m256i __a, __m256i __b)
1815		{
1816		return __builtin_ia32_psadbw256((__v32qi)__a, (__v32qi)__b);
	1813	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	1814	_mm256_sad_epu8(__m256i __a, __m256i __b) {
	1815	return __builtin_ia32_psadbw256((__v32qu)__a, (__v32qu)__b);
1817	1816	}
1818	1817
1819	1818	/// Shuffles 8-bit integers in the 256-bit integer vector \a __a according
...	...	@@ -3058,7 +3057,7 @@ _mm256_broadcastsi128_si256(__m128i __X) {
3058	3057	/// An immediate 8-bit integer operand, with bits [7:0] specifying the
3059	3058	/// source for each element of the result. The position of the mask bit
3060	3059	/// corresponds to the index of a copied value. When a mask bit is 0, the
3061		/// element is copied from \a V1; otherwise, it is is copied from \a V2.
	3060	/// element is copied from \a V1; otherwise, it is copied from \a V2.
3062	3061	/// \returns A 256-bit vector of [8 x i32] containing the result.
3063	3062	#define _mm256_blend_epi32(V1, V2, M) \
3064	3063	((__m256i)__builtin_ia32_pblendd256((__v8si)(__m256i)(V1), \

lib/include/avx512bmmintrin.h created+174

...	...	@@ -0,0 +1,174 @@
	1	/===-------- avx512bmmintrin.h - AVX512BMM intrinsics ------------------===
	2	*
	3	*
	4	* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	5	* See https://llvm.org/LICENSE.txt for license information.
	6	* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	7	*
	8	*===---------------------------------------------------------------------===
	9	*/
	10
	11	#ifndef __IMMINTRIN_H
	12	#error "Never use <avx512bmmintrin.h> directly; include <immintrin.h> instead."
	13	#endif
	14
	15	#ifndef _AVX512BMMINTRIN_H
	16	#define _AVX512BMMINTRIN_H
	17
	18	/* Define the default attributes for the functions in this file. */
	19	#define __DEFAULT_FN_ATTRS \
	20	__attribute__((__always_inline__, __nodebug__, __target__("avx512bmm"), \
	21	__min_vector_width__(512)))
	22
	23	#if defined(__cplusplus) && (__cplusplus >= 201103L)
	24	#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr
	25	#else
	26	#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS
	27	#endif
	28
	29	/// Multiplies two 16x16 bit matrices using OR reduction and ORs the product
	30	/// into a third 16x16 bit matrix (which is also the destination).
	31	///
	32	/// For the 512-bit ZMM form, each register contains two 16x16 (256-bit)
	33	/// matrices in bits [255:0] and [511:256]. The operation performs:
	34	/// \code{.operation}
	35	/// for i in 0 to 15
	36	/// for j in 0 to 15
	37	/// reduction_bit = __C[16*i+j]
	38	/// for k in 0 to 15
	39	/// reduction_bit \|= __A[16i+k] & __B[16k+j]
	40	/// end for k
	41	/// dest[16*i+j] = reduction_bit
	42	/// end for j
	43	/// end for i
	44	/// \endcode
	45	///
	46	/// \headerfile <immintrin.h>
	47	///
	48	/// This intrinsic corresponds to the <c> VBMACOR16X16X16 </c> instruction.
	49	///
	50	/// \param __A
	51	/// A 512-bit vector containing two 16x16 bit matrices (one per 256-bit
	52	/// lane).
	53	/// \param __B
	54	/// A 512-bit vector containing two 16x16 bit matrices (one per 256-bit
	55	/// lane).
	56	/// \param __C
	57	/// A 512-bit accumulator vector containing the initial values to OR with.
	58	/// \returns A 512-bit vector containing the accumulated result for each lane.
	59	/// \note This instruction does not support masking.
	60	static __inline __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	61	_mm512_bmacor16x16x16(__m512i __A, __m512i __B, __m512i __C) {
	62	return (__m512i)__builtin_ia32_bmacor16x16x16_v32hi(
	63	(__v32hi)__A, (__v32hi)__B, (__v32hi)__C);
	64	}
	65
	66	/// Multiplies two 16x16 bit matrices using XOR reduction and XORs the product
	67	/// into a third 16x16 bit matrix (which is also the destination).
	68	///
	69	/// For the 512-bit ZMM form, each register contains two 16x16 (256-bit)
	70	/// matrices in bits [255:0] and [511:256]. The operation performs:
	71	/// \code{.operation}
	72	/// for i in 0 to 15
	73	/// for j in 0 to 15
	74	/// reduction_bit = __C[16*i+j]
	75	/// for k in 0 to 15
	76	/// reduction_bit ^= __A[16i+k] & __B[16k+j]
	77	/// end for k
	78	/// dest[16*i+j] = reduction_bit
	79	/// end for j
	80	/// end for i
	81	/// \endcode
	82	///
	83	/// \headerfile <immintrin.h>
	84	///
	85	/// This intrinsic corresponds to the <c> VBMACXOR16X16X16 </c> instruction.
	86	///
	87	/// \param __A
	88	/// A 512-bit vector containing two 16x16 bit matrices (one per 256-bit
	89	/// lane).
	90	/// \param __B
	91	/// A 512-bit vector containing two 16x16 bit matrices (one per 256-bit
	92	/// lane).
	93	/// \param __C
	94	/// A 512-bit accumulator vector containing the initial values to XOR with.
	95	/// \returns A 512-bit vector containing the accumulated result for each lane.
	96	/// \note This instruction does not support masking.
	97	static __inline __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	98	_mm512_bmacxor16x16x16(__m512i __A, __m512i __B, __m512i __C) {
	99	return (__m512i)__builtin_ia32_bmacxor16x16x16_v32hi(
	100	(__v32hi)__A, (__v32hi)__B, (__v32hi)__C);
	101	}
	102
	103	/// Reverses the bits within each byte of the source vector.
	104	///
	105	/// For each byte in the source, reverses the order of its 8 bits to generate
	106	/// the corresponding destination byte. For example, 0b10110001 becomes
	107	/// 0b10001101.
	108	///
	109	/// \headerfile <immintrin.h>
	110	///
	111	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	112	///
	113	/// \param __A
	114	/// A 512-bit vector of [64 x i8] where each byte will have its bits
	115	/// reversed.
	116	/// \returns A 512-bit vector of [64 x i8] with bit-reversed bytes.
	117	static __inline __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	118	_mm512_bitrev_epi8(__m512i __A) {
	119	return (__m512i)__builtin_elementwise_bitreverse((__v64qi)__A);
	120	}
	121
	122	/// Reverses the bits within each byte of the source vector, using a writemask
	123	/// to conditionally select elements.
	124	///
	125	/// For each byte position, if the corresponding mask bit is 1, the byte from
	126	/// \a A has its bits reversed and stored in the result. If the mask bit is 0,
	127	/// the corresponding byte from \a B is copied to the result (merge masking).
	128	///
	129	/// \headerfile <immintrin.h>
	130	///
	131	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	132	///
	133	/// \param __U
	134	/// A 64-bit mask value where each bit controls one byte (per 8-bit element).
	135	/// A 1 performs bit reversal; a 0 selects the passthrough byte from __B.
	136	/// \param __A
	137	/// A 512-bit vector of [64 x i8] to be bit-reversed.
	138	/// \param __B
	139	/// A 512-bit vector of [64 x i8] providing passthrough values.
	140	/// \returns A 512-bit vector combining bit-reversed and passthrough bytes.
	141	static __inline __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	142	_mm512_mask_bitrev_epi8(__mmask64 __U, __m512i __A, __m512i __B) {
	143	return (__m512i)__builtin_ia32_selectb_512(
	144	(__mmask64)__U, (__v64qi)_mm512_bitrev_epi8(__A), (__v64qi)__B);
	145	}
	146
	147	/// Reverses the bits within each byte of the source vector, zeroing elements
	148	/// based on the writemask.
	149	///
	150	/// For each byte position, if the corresponding mask bit is 1, the byte from
	151	/// \a A has its bits reversed and stored in the result. If the mask bit is 0,
	152	/// the result byte is set to zero (zero masking).
	153	///
	154	/// \headerfile <immintrin.h>
	155	///
	156	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	157	///
	158	/// \param __U
	159	/// A 64-bit mask value where each bit controls one byte (per 8-bit element).
	160	/// A 1 performs bit reversal; a 0 sets the byte to zero.
	161	/// \param __A
	162	/// A 512-bit vector of [64 x i8] to be bit-reversed.
	163	/// \returns A 512-bit vector with bit-reversed or zeroed bytes.
	164	static __inline __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	165	_mm512_maskz_bitrev_epi8(__mmask64 __U, __m512i __A) {
	166	return (__m512i)__builtin_ia32_selectb_512((__mmask64)__U,
	167	(__v64qi)_mm512_bitrev_epi8(__A),
	168	(__v64qi)_mm512_setzero_si512());
	169	}
	170
	171	#undef __DEFAULT_FN_ATTRS
	172	#undef __DEFAULT_FN_ATTRS_CONSTEXPR
	173
	174	#endif

lib/include/avx512bmmvlintrin.h created+245

...	...	@@ -0,0 +1,245 @@
	1	/*===------------- avx512bmmvlintrin.h - BMM intrinsics ------------------===
	2	*
	3	*
	4	* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	5	* See https://llvm.org/LICENSE.txt for license information.
	6	* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	7	*
	8	*===-----------------------------------------------------------------------===
	9	*/
	10	#ifndef __IMMINTRIN_H
	11	#error \
	12	"Never use <avx512bmmvlintrin.h> directly; include <immintrin.h> instead."
	13	#endif
	14
	15	#ifndef __BMMVLINTRIN_H
	16	#define __BMMVLINTRIN_H
	17
	18	/* Define the default attributes for the functions in this file. */
	19	#define __DEFAULT_FN_ATTRS128 \
	20	__attribute__((__always_inline__, __nodebug__, \
	21	__target__("avx512bmm,avx512vl"), __min_vector_width__(128)))
	22	#define __DEFAULT_FN_ATTRS256 \
	23	__attribute__((__always_inline__, __nodebug__, \
	24	__target__("avx512bmm,avx512vl"), __min_vector_width__(256)))
	25
	26	#if defined(__cplusplus) && (__cplusplus >= 201103L)
	27	#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr
	28	#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr
	29	#else
	30	#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128
	31	#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256
	32	#endif
	33
	34	/// Multiplies two 16x16 bit matrices using OR reduction and ORs the product
	35	/// into a third 16x16 bit matrix (which is also the destination).
	36	///
	37	/// For the 256-bit YMM form, the source registers/memory each contain a single
	38	/// 16x16 (256-bit) matrix in bits [255:0]. The operation performs:
	39	/// \code{.operation}
	40	/// for i in 0 to 15
	41	/// for j in 0 to 15
	42	/// reduction_bit = __C[16*i+j]
	43	/// for k in 0 to 15
	44	/// reduction_bit \|= __A[16i+k] & __B[16k+j]
	45	/// end for k
	46	/// dest[16*i+j] = reduction_bit
	47	/// end for j
	48	/// end for i
	49	/// \endcode
	50	///
	51	/// \headerfile <immintrin.h>
	52	///
	53	/// This intrinsic corresponds to the <c> VBMACOR16X16X16 </c> instruction.
	54	///
	55	/// \param __A
	56	/// A 256-bit vector containing a 16x16 bit matrix.
	57	/// \param __B
	58	/// A 256-bit vector containing a 16x16 bit matrix.
	59	/// \param __C
	60	/// A 256-bit accumulator vector containing the initial values to OR with.
	61	/// \returns A 256-bit vector containing the accumulated result.
	62	/// \note This instruction does not support masking.
	63	static __inline __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	64	_mm256_bmacor16x16x16(__m256i __A, __m256i __B, __m256i __C) {
	65	return (__m256i)__builtin_ia32_bmacor16x16x16_v16hi(
	66	(__v16hi)__A, (__v16hi)__B, (__v16hi)__C);
	67	}
	68
	69	/// Multiplies two 16x16 bit matrices using XOR reduction and XORs the product
	70	/// into a third 16x16 bit matrix (which is also the destination).
	71	///
	72	/// For the 256-bit YMM form, the source registers/memory each contain a single
	73	/// 16x16 (256-bit) matrix in bits [255:0]. The operation performs:
	74	/// \code{.operation}
	75	/// for i in 0 to 15
	76	/// for j in 0 to 15
	77	/// reduction_bit = __C[16*i+j]
	78	/// for k in 0 to 15
	79	/// reduction_bit ^= __A[16i+k] & __B[16k+j]
	80	/// end for k
	81	/// dest[16*i+j] = reduction_bit
	82	/// end for j
	83	/// end for i
	84	/// \endcode
	85	///
	86	/// \headerfile <immintrin.h>
	87	///
	88	/// This intrinsic corresponds to the <c> VBMACXOR16X16X16 </c> instruction.
	89	///
	90	/// \param __A
	91	/// A 256-bit vector containing a 16x16 bit matrix.
	92	/// \param __B
	93	/// A 256-bit vector containing a 16x16 bit matrix.
	94	/// \param __C
	95	/// A 256-bit accumulator vector containing the initial values to XOR with.
	96	/// \returns A 256-bit vector containing the accumulated result.
	97	/// \note This instruction does not support masking.
	98	static __inline __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	99	_mm256_bmacxor16x16x16(__m256i __A, __m256i __B, __m256i __C) {
	100	return (__m256i)__builtin_ia32_bmacxor16x16x16_v16hi(
	101	(__v16hi)__A, (__v16hi)__B, (__v16hi)__C);
	102	}
	103
	104	/// Reverses the bits within each byte of the source vector.
	105	///
	106	/// For each byte in the source, reverses the order of its 8 bits to generate
	107	/// the corresponding destination byte. For example, 0b10110001 becomes
	108	/// 0b10001101.
	109	///
	110	/// \headerfile <immintrin.h>
	111	///
	112	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	113	///
	114	/// \param __A
	115	/// A 128-bit vector of [16 x i8] where each byte will have its bits
	116	/// reversed.
	117	/// \returns A 128-bit vector of [16 x i8] with bit-reversed bytes.
	118	static __inline __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	119	_mm128_bitrev_epi8(__m128i __A) {
	120	return (__m128i)__builtin_elementwise_bitreverse((__v16qi)__A);
	121	}
	122
	123	/// Reverses the bits within each byte of the source vector.
	124	///
	125	/// For each byte in the source, reverses the order of its 8 bits to generate
	126	/// the corresponding destination byte. For example, 0b10110001 becomes
	127	/// 0b10001101.
	128	///
	129	/// \headerfile <immintrin.h>
	130	///
	131	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	132	///
	133	/// \param __A
	134	/// A 256-bit vector of [32 x i8] where each byte will have its bits
	135	/// reversed.
	136	/// \returns A 256-bit vector of [32 x i8] with bit-reversed bytes.
	137	static __inline __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	138	_mm256_bitrev_epi8(__m256i __A) {
	139	return (__m256i)__builtin_elementwise_bitreverse((__v32qi)__A);
	140	}
	141
	142	/// Reverses the bits within each byte of the source vector, using a writemask
	143	/// to conditionally select elements.
	144	///
	145	/// For each byte position, if the corresponding mask bit is 1, the byte from
	146	/// \a A has its bits reversed and stored in the result. If the mask bit is 0,
	147	/// the corresponding byte from \a B is copied to the result (merge masking).
	148	///
	149	/// \headerfile <immintrin.h>
	150	///
	151	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	152	///
	153	/// \param __U
	154	/// A 16-bit mask value where each bit controls one byte (per 8-bit element).
	155	/// A 1 performs bit reversal; a 0 selects the passthrough byte from __B.
	156	/// \param __A
	157	/// A 128-bit vector of [16 x i8] to be bit-reversed.
	158	/// \param __B
	159	/// A 128-bit vector of [16 x i8] providing passthrough values.
	160	/// \returns A 128-bit vector combining bit-reversed and passthrough bytes.
	161	static __inline __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	162	_mm128_mask_bitrev_epi8(__mmask16 __U, __m128i __A, __m128i __B) {
	163	return (__m128i)__builtin_ia32_selectb_128(
	164	(__mmask16)__U, (__v16qi)_mm128_bitrev_epi8(__A), (__v16qi)__B);
	165	}
	166
	167	/// Reverses the bits within each byte of the source vector, using a writemask
	168	/// to conditionally select elements.
	169	///
	170	/// For each byte position, if the corresponding mask bit is 1, the byte from
	171	/// \a A has its bits reversed and stored in the result. If the mask bit is 0,
	172	/// the corresponding byte from \a B is copied to the result (merge masking).
	173	///
	174	/// \headerfile <immintrin.h>
	175	///
	176	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	177	///
	178	/// \param __U
	179	/// A 32-bit mask value where each bit controls one byte (per 8-bit element).
	180	/// A 1 performs bit reversal; a 0 selects the passthrough byte from __B.
	181	/// \param __A
	182	/// A 256-bit vector of [32 x i8] to be bit-reversed.
	183	/// \param __B
	184	/// A 256-bit vector of [32 x i8] providing passthrough values.
	185	/// \returns A 256-bit vector combining bit-reversed and passthrough bytes.
	186	static __inline __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	187	_mm256_mask_bitrev_epi8(__mmask32 __U, __m256i __A, __m256i __B) {
	188	return (__m256i)__builtin_ia32_selectb_256(
	189	(__mmask32)__U, (__v32qi)_mm256_bitrev_epi8(__A), (__v32qi)__B);
	190	}
	191
	192	/// Reverses the bits within each byte of the source vector, zeroing elements
	193	/// based on the writemask.
	194	///
	195	/// For each byte position, if the corresponding mask bit is 1, the byte from
	196	/// \a A has its bits reversed and stored in the result. If the mask bit is 0,
	197	/// the result byte is set to zero (zero masking).
	198	///
	199	/// \headerfile <immintrin.h>
	200	///
	201	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	202	///
	203	/// \param __U
	204	/// A 16-bit mask value where each bit controls one byte (per 8-bit element).
	205	/// A 1 performs bit reversal; a 0 sets the byte to zero.
	206	/// \param __A
	207	/// A 128-bit vector of [16 x i8] to be bit-reversed.
	208	/// \returns A 128-bit vector with bit-reversed or zeroed bytes.
	209	static __inline __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	210	_mm128_maskz_bitrev_epi8(__mmask16 __U, __m128i __A) {
	211	return (__m128i)__builtin_ia32_selectb_128((__mmask16)__U,
	212	(__v16qi)_mm128_bitrev_epi8(__A),
	213	(__v16qi)_mm_setzero_si128());
	214	}
	215
	216	/// Reverses the bits within each byte of the source vector, zeroing elements
	217	/// based on the writemask.
	218	///
	219	/// For each byte position, if the corresponding mask bit is 1, the byte from
	220	/// \a A has its bits reversed and stored in the result. If the mask bit is 0,
	221	/// the result byte is set to zero (zero masking).
	222	///
	223	/// \headerfile <immintrin.h>
	224	///
	225	/// This intrinsic corresponds to the <c> VBITREV </c> instruction.
	226	///
	227	/// \param __U
	228	/// A 32-bit mask value where each bit controls one byte (per 8-bit element).
	229	/// A 1 performs bit reversal; a 0 sets the byte to zero.
	230	/// \param __A
	231	/// A 256-bit vector of [32 x i8] to be bit-reversed.
	232	/// \returns A 256-bit vector with bit-reversed or zeroed bytes.
	233	static __inline __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	234	_mm256_maskz_bitrev_epi8(__mmask32 __U, __m256i __A) {
	235	return (__m256i)__builtin_ia32_selectb_256((__mmask32)__U,
	236	(__v32qi)_mm256_bitrev_epi8(__A),
	237	(__v32qi)_mm256_setzero_si256());
	238	}
	239
	240	#undef __DEFAULT_FN_ATTRS128_CONSTEXPR
	241	#undef __DEFAULT_FN_ATTRS256_CONSTEXPR
	242	#undef __DEFAULT_FN_ATTRS128
	243	#undef __DEFAULT_FN_ATTRS256
	244
	245	#endif

lib/include/avx512bwintrin.h+19-29

...	...	@@ -1695,57 +1695,49 @@ _mm512_mask_storeu_epi8 (void *__P, __mmask64 __U, __m512i __A)
1695	1695	(__mmask64) __U);
1696	1696	}
1697	1697
1698		static __inline__ __mmask64 __DEFAULT_FN_ATTRS512
1699		_mm512_test_epi8_mask (__m512i __A, __m512i __B)
1700		{
	1698	static __inline__ __mmask64 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1699	_mm512_test_epi8_mask(__m512i __A, __m512i __B) {
1701	1700	return _mm512_cmpneq_epi8_mask (_mm512_and_epi32 (__A, __B),
1702	1701	_mm512_setzero_si512());
1703	1702	}
1704	1703
1705		static __inline__ __mmask64 __DEFAULT_FN_ATTRS512
1706		_mm512_mask_test_epi8_mask (__mmask64 __U, __m512i __A, __m512i __B)
1707		{
	1704	static __inline__ __mmask64 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1705	_mm512_mask_test_epi8_mask(__mmask64 __U, __m512i __A, __m512i __B) {
1708	1706	return _mm512_mask_cmpneq_epi8_mask (__U, _mm512_and_epi32 (__A, __B),
1709	1707	_mm512_setzero_si512());
1710	1708	}
1711	1709
1712		static __inline__ __mmask32 __DEFAULT_FN_ATTRS512
1713		_mm512_test_epi16_mask (__m512i __A, __m512i __B)
1714		{
	1710	static __inline__ __mmask32 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1711	_mm512_test_epi16_mask(__m512i __A, __m512i __B) {
1715	1712	return _mm512_cmpneq_epi16_mask (_mm512_and_epi32 (__A, __B),
1716	1713	_mm512_setzero_si512());
1717	1714	}
1718	1715
1719		static __inline__ __mmask32 __DEFAULT_FN_ATTRS512
1720		_mm512_mask_test_epi16_mask (__mmask32 __U, __m512i __A, __m512i __B)
1721		{
	1716	static __inline__ __mmask32 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1717	_mm512_mask_test_epi16_mask(__mmask32 __U, __m512i __A, __m512i __B) {
1722	1718	return _mm512_mask_cmpneq_epi16_mask (__U, _mm512_and_epi32 (__A, __B),
1723	1719	_mm512_setzero_si512());
1724	1720	}
1725	1721
1726		static __inline__ __mmask64 __DEFAULT_FN_ATTRS512
1727		_mm512_testn_epi8_mask (__m512i __A, __m512i __B)
1728		{
	1722	static __inline__ __mmask64 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1723	_mm512_testn_epi8_mask(__m512i __A, __m512i __B) {
1729	1724	return _mm512_cmpeq_epi8_mask (_mm512_and_epi32 (__A, __B), _mm512_setzero_si512());
1730	1725	}
1731	1726
1732		static __inline__ __mmask64 __DEFAULT_FN_ATTRS512
1733		_mm512_mask_testn_epi8_mask (__mmask64 __U, __m512i __A, __m512i __B)
1734		{
	1727	static __inline__ __mmask64 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1728	_mm512_mask_testn_epi8_mask(__mmask64 __U, __m512i __A, __m512i __B) {
1735	1729	return _mm512_mask_cmpeq_epi8_mask (__U, _mm512_and_epi32 (__A, __B),
1736	1730	_mm512_setzero_si512());
1737	1731	}
1738	1732
1739		static __inline__ __mmask32 __DEFAULT_FN_ATTRS512
1740		_mm512_testn_epi16_mask (__m512i __A, __m512i __B)
1741		{
	1733	static __inline__ __mmask32 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1734	_mm512_testn_epi16_mask(__m512i __A, __m512i __B) {
1742	1735	return _mm512_cmpeq_epi16_mask (_mm512_and_epi32 (__A, __B),
1743	1736	_mm512_setzero_si512());
1744	1737	}
1745	1738
1746		static __inline__ __mmask32 __DEFAULT_FN_ATTRS512
1747		_mm512_mask_testn_epi16_mask (__mmask32 __U, __m512i __A, __m512i __B)
1748		{
	1739	static __inline__ __mmask32 __DEFAULT_FN_ATTRS512_CONSTEXPR
	1740	_mm512_mask_testn_epi16_mask(__mmask32 __U, __m512i __A, __m512i __B) {
1749	1741	return _mm512_mask_cmpeq_epi16_mask (__U, _mm512_and_epi32 (__A, __B),
1750	1742	_mm512_setzero_si512());
1751	1743	}
...	...	@@ -1880,11 +1872,9 @@ _mm512_mask_permutexvar_epi16(__m512i __W, __mmask32 __M, __m512i __A,
1880	1872	(__v32hi)_mm512_dbsad_epu8((A), (B), (imm)), \
1881	1873	(__v32hi)_mm512_setzero_si512()))
1882	1874
1883		static __inline__ __m512i __DEFAULT_FN_ATTRS512
1884		_mm512_sad_epu8 (__m512i __A, __m512i __B)
1885		{
1886		return (__m512i) __builtin_ia32_psadbw512 ((__v64qi) __A,
1887		(__v64qi) __B);
	1875	static __inline__ __m512i
	1876	__DEFAULT_FN_ATTRS512_CONSTEXPR _mm512_sad_epu8(__m512i __A, __m512i __B) {
	1877	return (__m512i)__builtin_ia32_psadbw512((__v64qu)__A, (__v64qu)__B);
1888	1878	}
1889	1879
1890	1880	#undef __DEFAULT_FN_ATTRS512

lib/include/avx512fintrin.h+62-89

...	...	@@ -42,11 +42,12 @@ typedef unsigned char __mmask8;
42	42	typedef unsigned short __mmask16;
43	43
44	44	/* Rounding mode macros. */
45		#define _MM_FROUND_TO_NEAREST_INT 0x00
46		#define _MM_FROUND_TO_NEG_INF 0x01
47		#define _MM_FROUND_TO_POS_INF 0x02
48		#define _MM_FROUND_TO_ZERO 0x03
49		#define _MM_FROUND_CUR_DIRECTION 0x04
	45	#define _MM_FROUND_TO_NEAREST_INT 0x00
	46	#define _MM_FROUND_TO_NEAREST_TIES_EVEN 0x00
	47	#define _MM_FROUND_TO_NEG_INF 0x01
	48	#define _MM_FROUND_TO_POS_INF 0x02
	49	#define _MM_FROUND_TO_ZERO 0x03
	50	#define _MM_FROUND_CUR_DIRECTION 0x04
50	51
51	52	/* Constants for integer comparison predicates */
52	53	typedef enum {
...	...	@@ -986,10 +987,8 @@ _mm512_maskz_max_ps(__mmask16 __U, __m512 __A, __m512 __B) {
986	987	(__v16sf)_mm512_setzero_ps());
987	988	}
988	989
989		static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_mask_max_ss(__m128 __W,
990		__mmask8 __U,
991		__m128 __A,
992		__m128 __B) {
	990	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
	991	_mm_mask_max_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
993	992	return (__m128) __builtin_ia32_maxss_round_mask ((__v4sf) __A,
994	993	(__v4sf) __B,
995	994	(__v4sf) __W,
...	...	@@ -997,9 +996,8 @@ static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_mask_max_ss(__m128 __W,
997	996	_MM_FROUND_CUR_DIRECTION);
998	997	}
999	998
1000		static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_maskz_max_ss(__mmask8 __U,
1001		__m128 __A,
1002		__m128 __B) {
	999	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
	1000	_mm_maskz_max_ss(__mmask8 __U, __m128 __A, __m128 __B) {
1003	1001	return (__m128) __builtin_ia32_maxss_round_mask ((__v4sf) __A,
1004	1002	(__v4sf) __B,
1005	1003	(__v4sf) _mm_setzero_ps (),
...	...	@@ -1025,10 +1023,8 @@ static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_maskz_max_ss(__mmask8 __U,
1025	1023	(__v4sf)_mm_setzero_ps(), \
1026	1024	(__mmask8)(U), (int)(R)))
1027	1025
1028		static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_mask_max_sd(__m128d __W,
1029		__mmask8 __U,
1030		__m128d __A,
1031		__m128d __B) {
	1026	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
	1027	_mm_mask_max_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
1032	1028	return (__m128d) __builtin_ia32_maxsd_round_mask ((__v2df) __A,
1033	1029	(__v2df) __B,
1034	1030	(__v2df) __W,
...	...	@@ -1036,9 +1032,8 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_mask_max_sd(__m128d __W,
1036	1032	_MM_FROUND_CUR_DIRECTION);
1037	1033	}
1038	1034
1039		static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_maskz_max_sd(__mmask8 __U,
1040		__m128d __A,
1041		__m128d __B) {
	1035	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
	1036	_mm_maskz_max_sd(__mmask8 __U, __m128d __A, __m128d __B) {
1042	1037	return (__m128d) __builtin_ia32_maxsd_round_mask ((__v2df) __A,
1043	1038	(__v2df) __B,
1044	1039	(__v2df) _mm_setzero_pd (),
...	...	@@ -1208,10 +1203,8 @@ _mm512_maskz_min_ps(__mmask16 __U, __m512 __A, __m512 __B) {
1208	1203	(__v16sf)_mm512_setzero_ps());
1209	1204	}
1210	1205
1211		static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_mask_min_ss(__m128 __W,
1212		__mmask8 __U,
1213		__m128 __A,
1214		__m128 __B) {
	1206	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
	1207	_mm_mask_min_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
1215	1208	return (__m128) __builtin_ia32_minss_round_mask ((__v4sf) __A,
1216	1209	(__v4sf) __B,
1217	1210	(__v4sf) __W,
...	...	@@ -1219,9 +1212,8 @@ static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_mask_min_ss(__m128 __W,
1219	1212	_MM_FROUND_CUR_DIRECTION);
1220	1213	}
1221	1214
1222		static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_maskz_min_ss(__mmask8 __U,
1223		__m128 __A,
1224		__m128 __B) {
	1215	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
	1216	_mm_maskz_min_ss(__mmask8 __U, __m128 __A, __m128 __B) {
1225	1217	return (__m128) __builtin_ia32_minss_round_mask ((__v4sf) __A,
1226	1218	(__v4sf) __B,
1227	1219	(__v4sf) _mm_setzero_ps (),
...	...	@@ -1247,10 +1239,8 @@ static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_maskz_min_ss(__mmask8 __U,
1247	1239	(__v4sf)_mm_setzero_ps(), \
1248	1240	(__mmask8)(U), (int)(R)))
1249	1241
1250		static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_mask_min_sd(__m128d __W,
1251		__mmask8 __U,
1252		__m128d __A,
1253		__m128d __B) {
	1242	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
	1243	_mm_mask_min_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
1254	1244	return (__m128d) __builtin_ia32_minsd_round_mask ((__v2df) __A,
1255	1245	(__v2df) __B,
1256	1246	(__v2df) __W,
...	...	@@ -1258,9 +1248,8 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_mask_min_sd(__m128d __W,
1258	1248	_MM_FROUND_CUR_DIRECTION);
1259	1249	}
1260	1250
1261		static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_maskz_min_sd(__mmask8 __U,
1262		__m128d __A,
1263		__m128d __B) {
	1251	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
	1252	_mm_maskz_min_sd(__mmask8 __U, __m128d __A, __m128d __B) {
1264	1253	return (__m128d) __builtin_ia32_minsd_round_mask ((__v2df) __A,
1265	1254	(__v2df) __B,
1266	1255	(__v2df) _mm_setzero_pd (),
...	...	@@ -8108,68 +8097,60 @@ _mm512_stream_ps (void *__P, __m512 __A)
8108	8097	__builtin_nontemporal_store((__v16sf_aligned)__A, (__v16sf_aligned*)__P);
8109	8098	}
8110	8099
8111		static __inline__ __m512d __DEFAULT_FN_ATTRS512
8112		_mm512_mask_compress_pd (__m512d __W, __mmask8 __U, __m512d __A)
8113		{
	8100	static __inline__ __m512d __DEFAULT_FN_ATTRS512_CONSTEXPR
	8101	_mm512_mask_compress_pd(__m512d __W, __mmask8 __U, __m512d __A) {
8114	8102	return (__m512d) __builtin_ia32_compressdf512_mask ((__v8df) __A,
8115	8103	(__v8df) __W,
8116	8104	(__mmask8) __U);
8117	8105	}
8118	8106
8119		static __inline__ __m512d __DEFAULT_FN_ATTRS512
8120		_mm512_maskz_compress_pd (__mmask8 __U, __m512d __A)
8121		{
	8107	static __inline__ __m512d __DEFAULT_FN_ATTRS512_CONSTEXPR
	8108	_mm512_maskz_compress_pd(__mmask8 __U, __m512d __A) {
8122	8109	return (__m512d) __builtin_ia32_compressdf512_mask ((__v8df) __A,
8123	8110	(__v8df)
8124	8111	_mm512_setzero_pd (),
8125	8112	(__mmask8) __U);
8126	8113	}
8127	8114
8128		static __inline__ __m512i __DEFAULT_FN_ATTRS512
8129		_mm512_mask_compress_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
8130		{
	8115	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
	8116	_mm512_mask_compress_epi64(__m512i __W, __mmask8 __U, __m512i __A) {
8131	8117	return (__m512i) __builtin_ia32_compressdi512_mask ((__v8di) __A,
8132	8118	(__v8di) __W,
8133	8119	(__mmask8) __U);
8134	8120	}
8135	8121
8136		static __inline__ __m512i __DEFAULT_FN_ATTRS512
8137		_mm512_maskz_compress_epi64 (__mmask8 __U, __m512i __A)
8138		{
	8122	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
	8123	_mm512_maskz_compress_epi64(__mmask8 __U, __m512i __A) {
8139	8124	return (__m512i) __builtin_ia32_compressdi512_mask ((__v8di) __A,
8140	8125	(__v8di)
8141	8126	_mm512_setzero_si512 (),
8142	8127	(__mmask8) __U);
8143	8128	}
8144	8129
8145		static __inline__ __m512 __DEFAULT_FN_ATTRS512
8146		_mm512_mask_compress_ps (__m512 __W, __mmask16 __U, __m512 __A)
8147		{
	8130	static __inline__ __m512 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8131	_mm512_mask_compress_ps(__m512 __W, __mmask16 __U, __m512 __A) {
8148	8132	return (__m512) __builtin_ia32_compresssf512_mask ((__v16sf) __A,
8149	8133	(__v16sf) __W,
8150	8134	(__mmask16) __U);
8151	8135	}
8152	8136
8153		static __inline__ __m512 __DEFAULT_FN_ATTRS512
8154		_mm512_maskz_compress_ps (__mmask16 __U, __m512 __A)
8155		{
	8137	static __inline__ __m512 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8138	_mm512_maskz_compress_ps(__mmask16 __U, __m512 __A) {
8156	8139	return (__m512) __builtin_ia32_compresssf512_mask ((__v16sf) __A,
8157	8140	(__v16sf)
8158	8141	_mm512_setzero_ps (),
8159	8142	(__mmask16) __U);
8160	8143	}
8161	8144
8162		static __inline__ __m512i __DEFAULT_FN_ATTRS512
8163		_mm512_mask_compress_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
8164		{
	8145	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
	8146	_mm512_mask_compress_epi32(__m512i __W, __mmask16 __U, __m512i __A) {
8165	8147	return (__m512i) __builtin_ia32_compresssi512_mask ((__v16si) __A,
8166	8148	(__v16si) __W,
8167	8149	(__mmask16) __U);
8168	8150	}
8169	8151
8170		static __inline__ __m512i __DEFAULT_FN_ATTRS512
8171		_mm512_maskz_compress_epi32 (__mmask16 __U, __m512i __A)
8172		{
	8152	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
	8153	_mm512_maskz_compress_epi32(__mmask16 __U, __m512i __A) {
8173	8154	return (__m512i) __builtin_ia32_compresssi512_mask ((__v16si) __A,
8174	8155	(__v16si)
8175	8156	_mm512_setzero_si512 (),
...	...	@@ -8222,58 +8203,50 @@ _mm512_maskz_compress_epi32 (__mmask16 __U, __m512i __A)
8222	8203
8223	8204	/* Bit Test */
8224	8205
8225		static __inline __mmask16 __DEFAULT_FN_ATTRS512
8226		_mm512_test_epi32_mask (__m512i __A, __m512i __B)
8227		{
	8206	static __inline __mmask16 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8207	_mm512_test_epi32_mask(__m512i __A, __m512i __B) {
8228	8208	return _mm512_cmpneq_epi32_mask (_mm512_and_epi32(__A, __B),
8229	8209	_mm512_setzero_si512());
8230	8210	}
8231	8211
8232		static __inline__ __mmask16 __DEFAULT_FN_ATTRS512
8233		_mm512_mask_test_epi32_mask (__mmask16 __U, __m512i __A, __m512i __B)
8234		{
	8212	static __inline__ __mmask16 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8213	_mm512_mask_test_epi32_mask(__mmask16 __U, __m512i __A, __m512i __B) {
8235	8214	return _mm512_mask_cmpneq_epi32_mask (__U, _mm512_and_epi32 (__A, __B),
8236	8215	_mm512_setzero_si512());
8237	8216	}
8238	8217
8239		static __inline __mmask8 __DEFAULT_FN_ATTRS512
8240		_mm512_test_epi64_mask (__m512i __A, __m512i __B)
8241		{
	8218	static __inline __mmask8 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8219	_mm512_test_epi64_mask(__m512i __A, __m512i __B) {
8242	8220	return _mm512_cmpneq_epi64_mask (_mm512_and_epi32 (__A, __B),
8243	8221	_mm512_setzero_si512());
8244	8222	}
8245	8223
8246		static __inline__ __mmask8 __DEFAULT_FN_ATTRS512
8247		_mm512_mask_test_epi64_mask (__mmask8 __U, __m512i __A, __m512i __B)
8248		{
	8224	static __inline__ __mmask8 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8225	_mm512_mask_test_epi64_mask(__mmask8 __U, __m512i __A, __m512i __B) {
8249	8226	return _mm512_mask_cmpneq_epi64_mask (__U, _mm512_and_epi32 (__A, __B),
8250	8227	_mm512_setzero_si512());
8251	8228	}
8252	8229
8253		static __inline__ __mmask16 __DEFAULT_FN_ATTRS512
8254		_mm512_testn_epi32_mask (__m512i __A, __m512i __B)
8255		{
	8230	static __inline__ __mmask16 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8231	_mm512_testn_epi32_mask(__m512i __A, __m512i __B) {
8256	8232	return _mm512_cmpeq_epi32_mask (_mm512_and_epi32 (__A, __B),
8257	8233	_mm512_setzero_si512());
8258	8234	}
8259	8235
8260		static __inline__ __mmask16 __DEFAULT_FN_ATTRS512
8261		_mm512_mask_testn_epi32_mask (__mmask16 __U, __m512i __A, __m512i __B)
8262		{
	8236	static __inline__ __mmask16 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8237	_mm512_mask_testn_epi32_mask(__mmask16 __U, __m512i __A, __m512i __B) {
8263	8238	return _mm512_mask_cmpeq_epi32_mask (__U, _mm512_and_epi32 (__A, __B),
8264	8239	_mm512_setzero_si512());
8265	8240	}
8266	8241
8267		static __inline__ __mmask8 __DEFAULT_FN_ATTRS512
8268		_mm512_testn_epi64_mask (__m512i __A, __m512i __B)
8269		{
	8242	static __inline__ __mmask8 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8243	_mm512_testn_epi64_mask(__m512i __A, __m512i __B) {
8270	8244	return _mm512_cmpeq_epi64_mask (_mm512_and_epi32 (__A, __B),
8271	8245	_mm512_setzero_si512());
8272	8246	}
8273	8247
8274		static __inline__ __mmask8 __DEFAULT_FN_ATTRS512
8275		_mm512_mask_testn_epi64_mask (__mmask8 __U, __m512i __A, __m512i __B)
8276		{
	8248	static __inline__ __mmask8 __DEFAULT_FN_ATTRS512_CONSTEXPR
	8249	_mm512_mask_testn_epi64_mask(__mmask8 __U, __m512i __A, __m512i __B) {
8277	8250	return _mm512_mask_cmpeq_epi64_mask (__U, _mm512_and_epi32 (__A, __B),
8278	8251	_mm512_setzero_si512());
8279	8252	}
...	...	@@ -8403,7 +8376,7 @@ _mm_maskz_load_sd (__mmask8 __U, const double* __A)
8403	8376	(__v16si)_mm512_shuffle_epi32((A), (I)), \
8404	8377	(__v16si)_mm512_setzero_si512()))
8405	8378
8406		static __inline__ __m512d __DEFAULT_FN_ATTRS512
	8379	static __inline__ __m512d __DEFAULT_FN_ATTRS512_CONSTEXPR
8407	8380	_mm512_mask_expand_pd (__m512d __W, __mmask8 __U, __m512d __A)
8408	8381	{
8409	8382	return (__m512d) __builtin_ia32_expanddf512_mask ((__v8df) __A,
...	...	@@ -8411,7 +8384,7 @@ _mm512_mask_expand_pd (__m512d __W, __mmask8 __U, __m512d __A)
8411	8384	(__mmask8) __U);
8412	8385	}
8413	8386
8414		static __inline__ __m512d __DEFAULT_FN_ATTRS512
	8387	static __inline__ __m512d __DEFAULT_FN_ATTRS512_CONSTEXPR
8415	8388	_mm512_maskz_expand_pd (__mmask8 __U, __m512d __A)
8416	8389	{
8417	8390	return (__m512d) __builtin_ia32_expanddf512_mask ((__v8df) __A,
...	...	@@ -8419,7 +8392,7 @@ _mm512_maskz_expand_pd (__mmask8 __U, __m512d __A)
8419	8392	(__mmask8) __U);
8420	8393	}
8421	8394
8422		static __inline__ __m512i __DEFAULT_FN_ATTRS512
	8395	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
8423	8396	_mm512_mask_expand_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
8424	8397	{
8425	8398	return (__m512i) __builtin_ia32_expanddi512_mask ((__v8di) __A,
...	...	@@ -8427,7 +8400,7 @@ _mm512_mask_expand_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
8427	8400	(__mmask8) __U);
8428	8401	}
8429	8402
8430		static __inline__ __m512i __DEFAULT_FN_ATTRS512
	8403	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
8431	8404	_mm512_maskz_expand_epi64 ( __mmask8 __U, __m512i __A)
8432	8405	{
8433	8406	return (__m512i) __builtin_ia32_expanddi512_mask ((__v8di) __A,
...	...	@@ -8499,7 +8472,7 @@ _mm512_maskz_expandloadu_epi32(__mmask16 __U, void const *__P)
8499	8472	(__mmask16) __U);
8500	8473	}
8501	8474
8502		static __inline__ __m512 __DEFAULT_FN_ATTRS512
	8475	static __inline__ __m512 __DEFAULT_FN_ATTRS512_CONSTEXPR
8503	8476	_mm512_mask_expand_ps (__m512 __W, __mmask16 __U, __m512 __A)
8504	8477	{
8505	8478	return (__m512) __builtin_ia32_expandsf512_mask ((__v16sf) __A,
...	...	@@ -8507,7 +8480,7 @@ _mm512_mask_expand_ps (__m512 __W, __mmask16 __U, __m512 __A)
8507	8480	(__mmask16) __U);
8508	8481	}
8509	8482
8510		static __inline__ __m512 __DEFAULT_FN_ATTRS512
	8483	static __inline__ __m512 __DEFAULT_FN_ATTRS512_CONSTEXPR
8511	8484	_mm512_maskz_expand_ps (__mmask16 __U, __m512 __A)
8512	8485	{
8513	8486	return (__m512) __builtin_ia32_expandsf512_mask ((__v16sf) __A,
...	...	@@ -8515,7 +8488,7 @@ _mm512_maskz_expand_ps (__mmask16 __U, __m512 __A)
8515	8488	(__mmask16) __U);
8516	8489	}
8517	8490
8518		static __inline__ __m512i __DEFAULT_FN_ATTRS512
	8491	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
8519	8492	_mm512_mask_expand_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
8520	8493	{
8521	8494	return (__m512i) __builtin_ia32_expandsi512_mask ((__v16si) __A,
...	...	@@ -8523,7 +8496,7 @@ _mm512_mask_expand_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
8523	8496	(__mmask16) __U);
8524	8497	}
8525	8498
8526		static __inline__ __m512i __DEFAULT_FN_ATTRS512
	8499	static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
8527	8500	_mm512_maskz_expand_epi32 (__mmask16 __U, __m512i __A)
8528	8501	{
8529	8502	return (__m512i) __builtin_ia32_expandsi512_mask ((__v16si) __A,

lib/include/avx512fp16intrin.h+12-18

...	...	@@ -720,25 +720,22 @@ _mm_maskz_div_sh(__mmask8 __U, __m128h __A, __m128h __B) {
720	720	(__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (__v8hf)_mm_setzero_ph(), \
721	721	(__mmask8)(U), (int)(R)))
722	722
723		static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_min_sh(__m128h __A,
724		__m128h __B) {
	723	static __inline__ __m128h
	724	__DEFAULT_FN_ATTRS128_CONSTEXPR _mm_min_sh(__m128h __A, __m128h __B) {
725	725	return (__m128h)__builtin_ia32_minsh_round_mask(
726	726	(__v8hf)__A, (__v8hf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)-1,
727	727	_MM_FROUND_CUR_DIRECTION);
728	728	}
729	729
730		static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_min_sh(__m128h __W,
731		__mmask8 __U,
732		__m128h __A,
733		__m128h __B) {
	730	static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
	731	_mm_mask_min_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) {
734	732	return (__m128h)__builtin_ia32_minsh_round_mask((__v8hf)__A, (__v8hf)__B,
735	733	(__v8hf)__W, (__mmask8)__U,
736	734	_MM_FROUND_CUR_DIRECTION);
737	735	}
738	736
739		static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_min_sh(__mmask8 __U,
740		__m128h __A,
741		__m128h __B) {
	737	static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
	738	_mm_maskz_min_sh(__mmask8 __U, __m128h __A, __m128h __B) {
742	739	return (__m128h)__builtin_ia32_minsh_round_mask(
743	740	(__v8hf)__A, (__v8hf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)__U,
744	741	_MM_FROUND_CUR_DIRECTION);
...	...	@@ -759,25 +756,22 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_min_sh(__mmask8 __U,
759	756	(__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (__v8hf)_mm_setzero_ph(), \
760	757	(__mmask8)(U), (int)(R)))
761	758
762		static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_max_sh(__m128h __A,
763		__m128h __B) {
	759	static __inline__ __m128h
	760	__DEFAULT_FN_ATTRS128_CONSTEXPR _mm_max_sh(__m128h __A, __m128h __B) {
764	761	return (__m128h)__builtin_ia32_maxsh_round_mask(
765	762	(__v8hf)__A, (__v8hf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)-1,
766	763	_MM_FROUND_CUR_DIRECTION);
767	764	}
768	765
769		static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_max_sh(__m128h __W,
770		__mmask8 __U,
771		__m128h __A,
772		__m128h __B) {
	766	static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
	767	_mm_mask_max_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) {
773	768	return (__m128h)__builtin_ia32_maxsh_round_mask((__v8hf)__A, (__v8hf)__B,
774	769	(__v8hf)__W, (__mmask8)__U,
775	770	_MM_FROUND_CUR_DIRECTION);
776	771	}
777	772
778		static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_max_sh(__mmask8 __U,
779		__m128h __A,
780		__m128h __B) {
	773	static __inline__ __m128h __DEFAULT_FN_ATTRS128_CONSTEXPR
	774	_mm_maskz_max_sh(__mmask8 __U, __m128h __A, __m128h __B) {
781	775	return (__m128h)__builtin_ia32_maxsh_round_mask(
782	776	(__v8hf)__A, (__v8hf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)__U,
783	777	_MM_FROUND_CUR_DIRECTION);

lib/include/avx512vbmi2intrin.h+12-16

...	...	@@ -25,33 +25,29 @@
25	25	#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS
26	26	#endif
27	27
28		static __inline__ __m512i __DEFAULT_FN_ATTRS
29		_mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D)
30		{
	28	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	29	_mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D) {
31	30	return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
32	31	(__v32hi) __S,
33	32	__U);
34	33	}
35	34
36		static __inline__ __m512i __DEFAULT_FN_ATTRS
37		_mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D)
38		{
	35	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	36	_mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D) {
39	37	return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
40	38	(__v32hi) _mm512_setzero_si512(),
41	39	__U);
42	40	}
43	41
44		static __inline__ __m512i __DEFAULT_FN_ATTRS
45		_mm512_mask_compress_epi8(__m512i __S, __mmask64 __U, __m512i __D)
46		{
	42	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	43	_mm512_mask_compress_epi8(__m512i __S, __mmask64 __U, __m512i __D) {
47	44	return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
48	45	(__v64qi) __S,
49	46	__U);
50	47	}
51	48
52		static __inline__ __m512i __DEFAULT_FN_ATTRS
53		_mm512_maskz_compress_epi8(__mmask64 __U, __m512i __D)
54		{
	49	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
	50	_mm512_maskz_compress_epi8(__mmask64 __U, __m512i __D) {
55	51	return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
56	52	(__v64qi) _mm512_setzero_si512(),
57	53	__U);
...	...	@@ -71,7 +67,7 @@ _mm512_mask_compressstoreu_epi8(void *__P, __mmask64 __U, __m512i __D)
71	67	__U);
72	68	}
73	69
74		static __inline__ __m512i __DEFAULT_FN_ATTRS
	70	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
75	71	_mm512_mask_expand_epi16(__m512i __S, __mmask32 __U, __m512i __D)
76	72	{
77	73	return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
...	...	@@ -79,7 +75,7 @@ _mm512_mask_expand_epi16(__m512i __S, __mmask32 __U, __m512i __D)
79	75	__U);
80	76	}
81	77
82		static __inline__ __m512i __DEFAULT_FN_ATTRS
	78	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
83	79	_mm512_maskz_expand_epi16(__mmask32 __U, __m512i __D)
84	80	{
85	81	return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
...	...	@@ -87,7 +83,7 @@ _mm512_maskz_expand_epi16(__mmask32 __U, __m512i __D)
87	83	__U);
88	84	}
89	85
90		static __inline__ __m512i __DEFAULT_FN_ATTRS
	86	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
91	87	_mm512_mask_expand_epi8(__m512i __S, __mmask64 __U, __m512i __D)
92	88	{
93	89	return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
...	...	@@ -95,7 +91,7 @@ _mm512_mask_expand_epi8(__m512i __S, __mmask64 __U, __m512i __D)
95	91	__U);
96	92	}
97	93
98		static __inline__ __m512i __DEFAULT_FN_ATTRS
	94	static __inline__ __m512i __DEFAULT_FN_ATTRS_CONSTEXPR
99	95	_mm512_maskz_expand_epi8(__mmask64 __U, __m512i __D)
100	96	{
101	97	return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,

lib/include/avx512vlbwintrin.h+24-36

...	...	@@ -2394,36 +2394,31 @@ _mm256_test_epi8_mask(__m256i __A, __m256i __B) {
2394	2394	_mm256_setzero_si256());
2395	2395	}
2396	2396
2397		static __inline__ __mmask32 __DEFAULT_FN_ATTRS256
2398		_mm256_mask_test_epi8_mask (__mmask32 __U, __m256i __A, __m256i __B)
2399		{
	2397	static __inline__ __mmask32 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2398	_mm256_mask_test_epi8_mask(__mmask32 __U, __m256i __A, __m256i __B) {
2400	2399	return _mm256_mask_cmpneq_epi8_mask (__U, _mm256_and_si256(__A, __B),
2401	2400	_mm256_setzero_si256());
2402	2401	}
2403	2402
2404		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
2405		_mm_test_epi16_mask (__m128i __A, __m128i __B)
2406		{
	2403	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	2404	_mm_test_epi16_mask(__m128i __A, __m128i __B) {
2407	2405	return _mm_cmpneq_epi16_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
2408	2406	}
2409	2407
2410		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
2411		_mm_mask_test_epi16_mask (__mmask8 __U, __m128i __A, __m128i __B)
2412		{
	2408	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	2409	_mm_mask_test_epi16_mask(__mmask8 __U, __m128i __A, __m128i __B) {
2413	2410	return _mm_mask_cmpneq_epi16_mask (__U, _mm_and_si128 (__A, __B),
2414	2411	_mm_setzero_si128());
2415	2412	}
2416	2413
2417		static __inline__ __mmask16 __DEFAULT_FN_ATTRS256
2418		_mm256_test_epi16_mask (__m256i __A, __m256i __B)
2419		{
	2414	static __inline__ __mmask16 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2415	_mm256_test_epi16_mask(__m256i __A, __m256i __B) {
2420	2416	return _mm256_cmpneq_epi16_mask (_mm256_and_si256 (__A, __B),
2421	2417	_mm256_setzero_si256 ());
2422	2418	}
2423	2419
2424		static __inline__ __mmask16 __DEFAULT_FN_ATTRS256
2425		_mm256_mask_test_epi16_mask (__mmask16 __U, __m256i __A, __m256i __B)
2426		{
	2420	static __inline__ __mmask16 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2421	_mm256_mask_test_epi16_mask(__mmask16 __U, __m256i __A, __m256i __B) {
2427	2422	return _mm256_mask_cmpneq_epi16_mask (__U, _mm256_and_si256(__A, __B),
2428	2423	_mm256_setzero_si256());
2429	2424	}
...	...	@@ -2433,49 +2428,42 @@ _mm_testn_epi8_mask(__m128i __A, __m128i __B) {
2433	2428	return _mm_cmpeq_epi8_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
2434	2429	}
2435	2430
2436		static __inline__ __mmask16 __DEFAULT_FN_ATTRS128
2437		_mm_mask_testn_epi8_mask (__mmask16 __U, __m128i __A, __m128i __B)
2438		{
	2431	static __inline__ __mmask16 __DEFAULT_FN_ATTRS128_CONSTEXPR
	2432	_mm_mask_testn_epi8_mask(__mmask16 __U, __m128i __A, __m128i __B) {
2439	2433	return _mm_mask_cmpeq_epi8_mask (__U, _mm_and_si128 (__A, __B),
2440	2434	_mm_setzero_si128());
2441	2435	}
2442	2436
2443		static __inline__ __mmask32 __DEFAULT_FN_ATTRS256
2444		_mm256_testn_epi8_mask (__m256i __A, __m256i __B)
2445		{
	2437	static __inline__ __mmask32 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2438	_mm256_testn_epi8_mask(__m256i __A, __m256i __B) {
2446	2439	return _mm256_cmpeq_epi8_mask (_mm256_and_si256 (__A, __B),
2447	2440	_mm256_setzero_si256());
2448	2441	}
2449	2442
2450		static __inline__ __mmask32 __DEFAULT_FN_ATTRS256
2451		_mm256_mask_testn_epi8_mask (__mmask32 __U, __m256i __A, __m256i __B)
2452		{
	2443	static __inline__ __mmask32 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2444	_mm256_mask_testn_epi8_mask(__mmask32 __U, __m256i __A, __m256i __B) {
2453	2445	return _mm256_mask_cmpeq_epi8_mask (__U, _mm256_and_si256 (__A, __B),
2454	2446	_mm256_setzero_si256());
2455	2447	}
2456	2448
2457		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
2458		_mm_testn_epi16_mask (__m128i __A, __m128i __B)
2459		{
	2449	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	2450	_mm_testn_epi16_mask(__m128i __A, __m128i __B) {
2460	2451	return _mm_cmpeq_epi16_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
2461	2452	}
2462	2453
2463		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
2464		_mm_mask_testn_epi16_mask (__mmask8 __U, __m128i __A, __m128i __B)
2465		{
	2454	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	2455	_mm_mask_testn_epi16_mask(__mmask8 __U, __m128i __A, __m128i __B) {
2466	2456	return _mm_mask_cmpeq_epi16_mask (__U, _mm_and_si128(__A, __B), _mm_setzero_si128());
2467	2457	}
2468	2458
2469		static __inline__ __mmask16 __DEFAULT_FN_ATTRS256
2470		_mm256_testn_epi16_mask (__m256i __A, __m256i __B)
2471		{
	2459	static __inline__ __mmask16 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2460	_mm256_testn_epi16_mask(__m256i __A, __m256i __B) {
2472	2461	return _mm256_cmpeq_epi16_mask (_mm256_and_si256(__A, __B),
2473	2462	_mm256_setzero_si256());
2474	2463	}
2475	2464
2476		static __inline__ __mmask16 __DEFAULT_FN_ATTRS256
2477		_mm256_mask_testn_epi16_mask (__mmask16 __U, __m256i __A, __m256i __B)
2478		{
	2465	static __inline__ __mmask16 __DEFAULT_FN_ATTRS256_CONSTEXPR
	2466	_mm256_mask_testn_epi16_mask(__mmask16 __U, __m256i __A, __m256i __B) {
2479	2467	return _mm256_mask_cmpeq_epi16_mask (__U, _mm256_and_si256 (__A, __B),
2480	2468	_mm256_setzero_si256());
2481	2469	}

lib/include/avx512vlintrin.h+80-96

...	...	@@ -1530,120 +1530,120 @@ _mm256_mask_blend_epi64(__mmask8 __U, __m256i __A, __m256i __W) {
1530	1530	(__v4di) __A);
1531	1531	}
1532	1532
1533		static __inline__ __m128d __DEFAULT_FN_ATTRS128
1534		_mm_mask_compress_pd (__m128d __W, __mmask8 __U, __m128d __A) {
	1533	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
	1534	_mm_mask_compress_pd(__m128d __W, __mmask8 __U, __m128d __A) {
1535	1535	return (__m128d) __builtin_ia32_compressdf128_mask ((__v2df) __A,
1536	1536	(__v2df) __W,
1537	1537	(__mmask8) __U);
1538	1538	}
1539	1539
1540		static __inline__ __m128d __DEFAULT_FN_ATTRS128
1541		_mm_maskz_compress_pd (__mmask8 __U, __m128d __A) {
	1540	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
	1541	_mm_maskz_compress_pd(__mmask8 __U, __m128d __A) {
1542	1542	return (__m128d) __builtin_ia32_compressdf128_mask ((__v2df) __A,
1543	1543	(__v2df)
1544	1544	_mm_setzero_pd (),
1545	1545	(__mmask8) __U);
1546	1546	}
1547	1547
1548		static __inline__ __m256d __DEFAULT_FN_ATTRS256
1549		_mm256_mask_compress_pd (__m256d __W, __mmask8 __U, __m256d __A) {
	1548	static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
	1549	_mm256_mask_compress_pd(__m256d __W, __mmask8 __U, __m256d __A) {
1550	1550	return (__m256d) __builtin_ia32_compressdf256_mask ((__v4df) __A,
1551	1551	(__v4df) __W,
1552	1552	(__mmask8) __U);
1553	1553	}
1554	1554
1555		static __inline__ __m256d __DEFAULT_FN_ATTRS256
1556		_mm256_maskz_compress_pd (__mmask8 __U, __m256d __A) {
	1555	static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
	1556	_mm256_maskz_compress_pd(__mmask8 __U, __m256d __A) {
1557	1557	return (__m256d) __builtin_ia32_compressdf256_mask ((__v4df) __A,
1558	1558	(__v4df)
1559	1559	_mm256_setzero_pd (),
1560	1560	(__mmask8) __U);
1561	1561	}
1562	1562
1563		static __inline__ __m128i __DEFAULT_FN_ATTRS128
1564		_mm_mask_compress_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
	1563	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	1564	_mm_mask_compress_epi64(__m128i __W, __mmask8 __U, __m128i __A) {
1565	1565	return (__m128i) __builtin_ia32_compressdi128_mask ((__v2di) __A,
1566	1566	(__v2di) __W,
1567	1567	(__mmask8) __U);
1568	1568	}
1569	1569
1570		static __inline__ __m128i __DEFAULT_FN_ATTRS128
1571		_mm_maskz_compress_epi64 (__mmask8 __U, __m128i __A) {
	1570	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	1571	_mm_maskz_compress_epi64(__mmask8 __U, __m128i __A) {
1572	1572	return (__m128i) __builtin_ia32_compressdi128_mask ((__v2di) __A,
1573	1573	(__v2di)
1574	1574	_mm_setzero_si128 (),
1575	1575	(__mmask8) __U);
1576	1576	}
1577	1577
1578		static __inline__ __m256i __DEFAULT_FN_ATTRS256
1579		_mm256_mask_compress_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
	1578	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	1579	_mm256_mask_compress_epi64(__m256i __W, __mmask8 __U, __m256i __A) {
1580	1580	return (__m256i) __builtin_ia32_compressdi256_mask ((__v4di) __A,
1581	1581	(__v4di) __W,
1582	1582	(__mmask8) __U);
1583	1583	}
1584	1584
1585		static __inline__ __m256i __DEFAULT_FN_ATTRS256
1586		_mm256_maskz_compress_epi64 (__mmask8 __U, __m256i __A) {
	1585	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	1586	_mm256_maskz_compress_epi64(__mmask8 __U, __m256i __A) {
1587	1587	return (__m256i) __builtin_ia32_compressdi256_mask ((__v4di) __A,
1588	1588	(__v4di)
1589	1589	_mm256_setzero_si256 (),
1590	1590	(__mmask8) __U);
1591	1591	}
1592	1592
1593		static __inline__ __m128 __DEFAULT_FN_ATTRS128
1594		_mm_mask_compress_ps (__m128 __W, __mmask8 __U, __m128 __A) {
	1593	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
	1594	_mm_mask_compress_ps(__m128 __W, __mmask8 __U, __m128 __A) {
1595	1595	return (__m128) __builtin_ia32_compresssf128_mask ((__v4sf) __A,
1596	1596	(__v4sf) __W,
1597	1597	(__mmask8) __U);
1598	1598	}
1599	1599
1600		static __inline__ __m128 __DEFAULT_FN_ATTRS128
1601		_mm_maskz_compress_ps (__mmask8 __U, __m128 __A) {
	1600	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
	1601	_mm_maskz_compress_ps(__mmask8 __U, __m128 __A) {
1602	1602	return (__m128) __builtin_ia32_compresssf128_mask ((__v4sf) __A,
1603	1603	(__v4sf)
1604	1604	_mm_setzero_ps (),
1605	1605	(__mmask8) __U);
1606	1606	}
1607	1607
1608		static __inline__ __m256 __DEFAULT_FN_ATTRS256
1609		_mm256_mask_compress_ps (__m256 __W, __mmask8 __U, __m256 __A) {
	1608	static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
	1609	_mm256_mask_compress_ps(__m256 __W, __mmask8 __U, __m256 __A) {
1610	1610	return (__m256) __builtin_ia32_compresssf256_mask ((__v8sf) __A,
1611	1611	(__v8sf) __W,
1612	1612	(__mmask8) __U);
1613	1613	}
1614	1614
1615		static __inline__ __m256 __DEFAULT_FN_ATTRS256
1616		_mm256_maskz_compress_ps (__mmask8 __U, __m256 __A) {
	1615	static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
	1616	_mm256_maskz_compress_ps(__mmask8 __U, __m256 __A) {
1617	1617	return (__m256) __builtin_ia32_compresssf256_mask ((__v8sf) __A,
1618	1618	(__v8sf)
1619	1619	_mm256_setzero_ps (),
1620	1620	(__mmask8) __U);
1621	1621	}
1622	1622
1623		static __inline__ __m128i __DEFAULT_FN_ATTRS128
1624		_mm_mask_compress_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
	1623	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	1624	_mm_mask_compress_epi32(__m128i __W, __mmask8 __U, __m128i __A) {
1625	1625	return (__m128i) __builtin_ia32_compresssi128_mask ((__v4si) __A,
1626	1626	(__v4si) __W,
1627	1627	(__mmask8) __U);
1628	1628	}
1629	1629
1630		static __inline__ __m128i __DEFAULT_FN_ATTRS128
1631		_mm_maskz_compress_epi32 (__mmask8 __U, __m128i __A) {
	1630	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	1631	_mm_maskz_compress_epi32(__mmask8 __U, __m128i __A) {
1632	1632	return (__m128i) __builtin_ia32_compresssi128_mask ((__v4si) __A,
1633	1633	(__v4si)
1634	1634	_mm_setzero_si128 (),
1635	1635	(__mmask8) __U);
1636	1636	}
1637	1637
1638		static __inline__ __m256i __DEFAULT_FN_ATTRS256
1639		_mm256_mask_compress_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
	1638	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	1639	_mm256_mask_compress_epi32(__m256i __W, __mmask8 __U, __m256i __A) {
1640	1640	return (__m256i) __builtin_ia32_compresssi256_mask ((__v8si) __A,
1641	1641	(__v8si) __W,
1642	1642	(__mmask8) __U);
1643	1643	}
1644	1644
1645		static __inline__ __m256i __DEFAULT_FN_ATTRS256
1646		_mm256_maskz_compress_epi32 (__mmask8 __U, __m256i __A) {
	1645	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	1646	_mm256_maskz_compress_epi32(__mmask8 __U, __m256i __A) {
1647	1647	return (__m256i) __builtin_ia32_compresssi256_mask ((__v8si) __A,
1648	1648	(__v8si)
1649	1649	_mm256_setzero_si256 (),
...	...	@@ -2250,14 +2250,14 @@ _mm256_maskz_div_ps(__mmask8 __U, __m256 __A, __m256 __B) {
2250	2250	(__v8sf)_mm256_setzero_ps());
2251	2251	}
2252	2252
2253		static __inline__ __m128d __DEFAULT_FN_ATTRS128
	2253	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
2254	2254	_mm_mask_expand_pd (__m128d __W, __mmask8 __U, __m128d __A) {
2255	2255	return (__m128d) __builtin_ia32_expanddf128_mask ((__v2df) __A,
2256	2256	(__v2df) __W,
2257	2257	(__mmask8) __U);
2258	2258	}
2259	2259
2260		static __inline__ __m128d __DEFAULT_FN_ATTRS128
	2260	static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR
2261	2261	_mm_maskz_expand_pd (__mmask8 __U, __m128d __A) {
2262	2262	return (__m128d) __builtin_ia32_expanddf128_mask ((__v2df) __A,
2263	2263	(__v2df)
...	...	@@ -2265,14 +2265,14 @@ _mm_maskz_expand_pd (__mmask8 __U, __m128d __A) {
2265	2265	(__mmask8) __U);
2266	2266	}
2267	2267
2268		static __inline__ __m256d __DEFAULT_FN_ATTRS256
	2268	static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
2269	2269	_mm256_mask_expand_pd (__m256d __W, __mmask8 __U, __m256d __A) {
2270	2270	return (__m256d) __builtin_ia32_expanddf256_mask ((__v4df) __A,
2271	2271	(__v4df) __W,
2272	2272	(__mmask8) __U);
2273	2273	}
2274	2274
2275		static __inline__ __m256d __DEFAULT_FN_ATTRS256
	2275	static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR
2276	2276	_mm256_maskz_expand_pd (__mmask8 __U, __m256d __A) {
2277	2277	return (__m256d) __builtin_ia32_expanddf256_mask ((__v4df) __A,
2278	2278	(__v4df)
...	...	@@ -2280,14 +2280,14 @@ _mm256_maskz_expand_pd (__mmask8 __U, __m256d __A) {
2280	2280	(__mmask8) __U);
2281	2281	}
2282	2282
2283		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	2283	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
2284	2284	_mm_mask_expand_epi64 (__m128i __W, __mmask8 __U, __m128i __A) {
2285	2285	return (__m128i) __builtin_ia32_expanddi128_mask ((__v2di) __A,
2286	2286	(__v2di) __W,
2287	2287	(__mmask8) __U);
2288	2288	}
2289	2289
2290		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	2290	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
2291	2291	_mm_maskz_expand_epi64 (__mmask8 __U, __m128i __A) {
2292	2292	return (__m128i) __builtin_ia32_expanddi128_mask ((__v2di) __A,
2293	2293	(__v2di)
...	...	@@ -2295,14 +2295,14 @@ _mm_maskz_expand_epi64 (__mmask8 __U, __m128i __A) {
2295	2295	(__mmask8) __U);
2296	2296	}
2297	2297
2298		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	2298	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
2299	2299	_mm256_mask_expand_epi64 (__m256i __W, __mmask8 __U, __m256i __A) {
2300	2300	return (__m256i) __builtin_ia32_expanddi256_mask ((__v4di) __A,
2301	2301	(__v4di) __W,
2302	2302	(__mmask8) __U);
2303	2303	}
2304	2304
2305		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	2305	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
2306	2306	_mm256_maskz_expand_epi64 (__mmask8 __U, __m256i __A) {
2307	2307	return (__m256i) __builtin_ia32_expanddi256_mask ((__v4di) __A,
2308	2308	(__v4di)
...	...	@@ -2445,14 +2445,14 @@ _mm256_maskz_expandloadu_epi32 (__mmask8 __U, void const *__P) {
2445	2445	__U);
2446	2446	}
2447	2447
2448		static __inline__ __m128 __DEFAULT_FN_ATTRS128
	2448	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
2449	2449	_mm_mask_expand_ps (__m128 __W, __mmask8 __U, __m128 __A) {
2450	2450	return (__m128) __builtin_ia32_expandsf128_mask ((__v4sf) __A,
2451	2451	(__v4sf) __W,
2452	2452	(__mmask8) __U);
2453	2453	}
2454	2454
2455		static __inline__ __m128 __DEFAULT_FN_ATTRS128
	2455	static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
2456	2456	_mm_maskz_expand_ps (__mmask8 __U, __m128 __A) {
2457	2457	return (__m128) __builtin_ia32_expandsf128_mask ((__v4sf) __A,
2458	2458	(__v4sf)
...	...	@@ -2460,14 +2460,14 @@ _mm_maskz_expand_ps (__mmask8 __U, __m128 __A) {
2460	2460	(__mmask8) __U);
2461	2461	}
2462	2462
2463		static __inline__ __m256 __DEFAULT_FN_ATTRS256
	2463	static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
2464	2464	_mm256_mask_expand_ps (__m256 __W, __mmask8 __U, __m256 __A) {
2465	2465	return (__m256) __builtin_ia32_expandsf256_mask ((__v8sf) __A,
2466	2466	(__v8sf) __W,
2467	2467	(__mmask8) __U);
2468	2468	}
2469	2469
2470		static __inline__ __m256 __DEFAULT_FN_ATTRS256
	2470	static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
2471	2471	_mm256_maskz_expand_ps (__mmask8 __U, __m256 __A) {
2472	2472	return (__m256) __builtin_ia32_expandsf256_mask ((__v8sf) __A,
2473	2473	(__v8sf)
...	...	@@ -2475,14 +2475,14 @@ _mm256_maskz_expand_ps (__mmask8 __U, __m256 __A) {
2475	2475	(__mmask8) __U);
2476	2476	}
2477	2477
2478		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	2478	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
2479	2479	_mm_mask_expand_epi32 (__m128i __W, __mmask8 __U, __m128i __A) {
2480	2480	return (__m128i) __builtin_ia32_expandsi128_mask ((__v4si) __A,
2481	2481	(__v4si) __W,
2482	2482	(__mmask8) __U);
2483	2483	}
2484	2484
2485		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	2485	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
2486	2486	_mm_maskz_expand_epi32 (__mmask8 __U, __m128i __A) {
2487	2487	return (__m128i) __builtin_ia32_expandsi128_mask ((__v4si) __A,
2488	2488	(__v4si)
...	...	@@ -2490,14 +2490,14 @@ _mm_maskz_expand_epi32 (__mmask8 __U, __m128i __A) {
2490	2490	(__mmask8) __U);
2491	2491	}
2492	2492
2493		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	2493	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
2494	2494	_mm256_mask_expand_epi32 (__m256i __W, __mmask8 __U, __m256i __A) {
2495	2495	return (__m256i) __builtin_ia32_expandsi256_mask ((__v8si) __A,
2496	2496	(__v8si) __W,
2497	2497	(__mmask8) __U);
2498	2498	}
2499	2499
2500		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	2500	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
2501	2501	_mm256_maskz_expand_epi32 (__mmask8 __U, __m256i __A) {
2502	2502	return (__m256i) __builtin_ia32_expandsi256_mask ((__v8si) __A,
2503	2503	(__v8si)
...	...	@@ -5887,110 +5887,94 @@ _mm256_maskz_permutevar_ps(__mmask8 __U, __m256 __A, __m256i __C) {
5887	5887	(__v8sf)_mm256_setzero_ps());
5888	5888	}
5889	5889
5890		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5891		_mm_test_epi32_mask (__m128i __A, __m128i __B)
5892		{
	5890	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5891	_mm_test_epi32_mask(__m128i __A, __m128i __B) {
5893	5892	return _mm_cmpneq_epi32_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
5894	5893	}
5895	5894
5896		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5897		_mm_mask_test_epi32_mask (__mmask8 __U, __m128i __A, __m128i __B)
5898		{
	5895	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5896	_mm_mask_test_epi32_mask(__mmask8 __U, __m128i __A, __m128i __B) {
5899	5897	return _mm_mask_cmpneq_epi32_mask (__U, _mm_and_si128 (__A, __B),
5900	5898	_mm_setzero_si128());
5901	5899	}
5902	5900
5903		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5904		_mm256_test_epi32_mask (__m256i __A, __m256i __B)
5905		{
	5901	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5902	_mm256_test_epi32_mask(__m256i __A, __m256i __B) {
5906	5903	return _mm256_cmpneq_epi32_mask (_mm256_and_si256 (__A, __B),
5907	5904	_mm256_setzero_si256());
5908	5905	}
5909	5906
5910		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5911		_mm256_mask_test_epi32_mask (__mmask8 __U, __m256i __A, __m256i __B)
5912		{
	5907	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5908	_mm256_mask_test_epi32_mask(__mmask8 __U, __m256i __A, __m256i __B) {
5913	5909	return _mm256_mask_cmpneq_epi32_mask (__U, _mm256_and_si256 (__A, __B),
5914	5910	_mm256_setzero_si256());
5915	5911	}
5916	5912
5917		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5918		_mm_test_epi64_mask (__m128i __A, __m128i __B)
5919		{
	5913	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5914	_mm_test_epi64_mask(__m128i __A, __m128i __B) {
5920	5915	return _mm_cmpneq_epi64_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
5921	5916	}
5922	5917
5923		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5924		_mm_mask_test_epi64_mask (__mmask8 __U, __m128i __A, __m128i __B)
5925		{
	5918	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5919	_mm_mask_test_epi64_mask(__mmask8 __U, __m128i __A, __m128i __B) {
5926	5920	return _mm_mask_cmpneq_epi64_mask (__U, _mm_and_si128 (__A, __B),
5927	5921	_mm_setzero_si128());
5928	5922	}
5929	5923
5930		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5931		_mm256_test_epi64_mask (__m256i __A, __m256i __B)
5932		{
	5924	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5925	_mm256_test_epi64_mask(__m256i __A, __m256i __B) {
5933	5926	return _mm256_cmpneq_epi64_mask (_mm256_and_si256 (__A, __B),
5934	5927	_mm256_setzero_si256());
5935	5928	}
5936	5929
5937		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5938		_mm256_mask_test_epi64_mask (__mmask8 __U, __m256i __A, __m256i __B)
5939		{
	5930	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5931	_mm256_mask_test_epi64_mask(__mmask8 __U, __m256i __A, __m256i __B) {
5940	5932	return _mm256_mask_cmpneq_epi64_mask (__U, _mm256_and_si256 (__A, __B),
5941	5933	_mm256_setzero_si256());
5942	5934	}
5943	5935
5944		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5945		_mm_testn_epi32_mask (__m128i __A, __m128i __B)
5946		{
	5936	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5937	_mm_testn_epi32_mask(__m128i __A, __m128i __B) {
5947	5938	return _mm_cmpeq_epi32_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
5948	5939	}
5949	5940
5950		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5951		_mm_mask_testn_epi32_mask (__mmask8 __U, __m128i __A, __m128i __B)
5952		{
	5941	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5942	_mm_mask_testn_epi32_mask(__mmask8 __U, __m128i __A, __m128i __B) {
5953	5943	return _mm_mask_cmpeq_epi32_mask (__U, _mm_and_si128 (__A, __B),
5954	5944	_mm_setzero_si128());
5955	5945	}
5956	5946
5957		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5958		_mm256_testn_epi32_mask (__m256i __A, __m256i __B)
5959		{
	5947	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5948	_mm256_testn_epi32_mask(__m256i __A, __m256i __B) {
5960	5949	return _mm256_cmpeq_epi32_mask (_mm256_and_si256 (__A, __B),
5961	5950	_mm256_setzero_si256());
5962	5951	}
5963	5952
5964		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5965		_mm256_mask_testn_epi32_mask (__mmask8 __U, __m256i __A, __m256i __B)
5966		{
	5953	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5954	_mm256_mask_testn_epi32_mask(__mmask8 __U, __m256i __A, __m256i __B) {
5967	5955	return _mm256_mask_cmpeq_epi32_mask (__U, _mm256_and_si256 (__A, __B),
5968	5956	_mm256_setzero_si256());
5969	5957	}
5970	5958
5971		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5972		_mm_testn_epi64_mask (__m128i __A, __m128i __B)
5973		{
	5959	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5960	_mm_testn_epi64_mask(__m128i __A, __m128i __B) {
5974	5961	return _mm_cmpeq_epi64_mask (_mm_and_si128 (__A, __B), _mm_setzero_si128());
5975	5962	}
5976	5963
5977		static __inline__ __mmask8 __DEFAULT_FN_ATTRS128
5978		_mm_mask_testn_epi64_mask (__mmask8 __U, __m128i __A, __m128i __B)
5979		{
	5964	static __inline__ __mmask8 __DEFAULT_FN_ATTRS128_CONSTEXPR
	5965	_mm_mask_testn_epi64_mask(__mmask8 __U, __m128i __A, __m128i __B) {
5980	5966	return _mm_mask_cmpeq_epi64_mask (__U, _mm_and_si128 (__A, __B),
5981	5967	_mm_setzero_si128());
5982	5968	}
5983	5969
5984		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5985		_mm256_testn_epi64_mask (__m256i __A, __m256i __B)
5986		{
	5970	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5971	_mm256_testn_epi64_mask(__m256i __A, __m256i __B) {
5987	5972	return _mm256_cmpeq_epi64_mask (_mm256_and_si256 (__A, __B),
5988	5973	_mm256_setzero_si256());
5989	5974	}
5990	5975
5991		static __inline__ __mmask8 __DEFAULT_FN_ATTRS256
5992		_mm256_mask_testn_epi64_mask (__mmask8 __U, __m256i __A, __m256i __B)
5993		{
	5976	static __inline__ __mmask8 __DEFAULT_FN_ATTRS256_CONSTEXPR
	5977	_mm256_mask_testn_epi64_mask(__mmask8 __U, __m256i __A, __m256i __B) {
5994	5978	return _mm256_mask_cmpeq_epi64_mask (__U, _mm256_and_si256 (__A, __B),
5995	5979	_mm256_setzero_si256());
5996	5980	}

lib/include/avx512vlvbmi2intrin.h+24-32

...	...	@@ -32,33 +32,29 @@
32	32	#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256
33	33	#endif
34	34
35		static __inline__ __m128i __DEFAULT_FN_ATTRS128
36		_mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D)
37		{
	35	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	36	_mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) {
38	37	return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
39	38	(__v8hi) __S,
40	39	__U);
41	40	}
42	41
43		static __inline__ __m128i __DEFAULT_FN_ATTRS128
44		_mm_maskz_compress_epi16(__mmask8 __U, __m128i __D)
45		{
	42	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	43	_mm_maskz_compress_epi16(__mmask8 __U, __m128i __D) {
46	44	return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
47	45	(__v8hi) _mm_setzero_si128(),
48	46	__U);
49	47	}
50	48
51		static __inline__ __m128i __DEFAULT_FN_ATTRS128
52		_mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D)
53		{
	49	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	50	_mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) {
54	51	return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
55	52	(__v16qi) __S,
56	53	__U);
57	54	}
58	55
59		static __inline__ __m128i __DEFAULT_FN_ATTRS128
60		_mm_maskz_compress_epi8(__mmask16 __U, __m128i __D)
61		{
	56	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
	57	_mm_maskz_compress_epi8(__mmask16 __U, __m128i __D) {
62	58	return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
63	59	(__v16qi) _mm_setzero_si128(),
64	60	__U);
...	...	@@ -78,7 +74,7 @@ _mm_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D)
78	74	__U);
79	75	}
80	76
81		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	77	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
82	78	_mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D)
83	79	{
84	80	return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
...	...	@@ -86,7 +82,7 @@ _mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D)
86	82	__U);
87	83	}
88	84
89		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	85	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
90	86	_mm_maskz_expand_epi16(__mmask8 __U, __m128i __D)
91	87	{
92	88	return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
...	...	@@ -94,7 +90,7 @@ _mm_maskz_expand_epi16(__mmask8 __U, __m128i __D)
94	90	__U);
95	91	}
96	92
97		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	93	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
98	94	_mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D)
99	95	{
100	96	return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
...	...	@@ -102,7 +98,7 @@ _mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D)
102	98	__U);
103	99	}
104	100
105		static __inline__ __m128i __DEFAULT_FN_ATTRS128
	101	static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR
106	102	_mm_maskz_expand_epi8(__mmask16 __U, __m128i __D)
107	103	{
108	104	return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
...	...	@@ -142,33 +138,29 @@ _mm_maskz_expandloadu_epi8(__mmask16 __U, void const *__P)
142	138	__U);
143	139	}
144	140
145		static __inline__ __m256i __DEFAULT_FN_ATTRS256
146		_mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D)
147		{
	141	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	142	_mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D) {
148	143	return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
149	144	(__v16hi) __S,
150	145	__U);
151	146	}
152	147
153		static __inline__ __m256i __DEFAULT_FN_ATTRS256
154		_mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D)
155		{
	148	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	149	_mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D) {
156	150	return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
157	151	(__v16hi) _mm256_setzero_si256(),
158	152	__U);
159	153	}
160	154
161		static __inline__ __m256i __DEFAULT_FN_ATTRS256
162		_mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D)
163		{
	155	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	156	_mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D) {
164	157	return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
165	158	(__v32qi) __S,
166	159	__U);
167	160	}
168	161
169		static __inline__ __m256i __DEFAULT_FN_ATTRS256
170		_mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D)
171		{
	162	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
	163	_mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D) {
172	164	return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
173	165	(__v32qi) _mm256_setzero_si256(),
174	166	__U);
...	...	@@ -188,7 +180,7 @@ _mm256_mask_compressstoreu_epi8(void *__P, __mmask32 __U, __m256i __D)
188	180	__U);
189	181	}
190	182
191		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	183	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
192	184	_mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D)
193	185	{
194	186	return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
...	...	@@ -196,7 +188,7 @@ _mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D)
196	188	__U);
197	189	}
198	190
199		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	191	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
200	192	_mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D)
201	193	{
202	194	return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
...	...	@@ -204,7 +196,7 @@ _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D)
204	196	__U);
205	197	}
206	198
207		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	199	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
208	200	_mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D)
209	201	{
210	202	return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
...	...	@@ -212,7 +204,7 @@ _mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D)
212	204	__U);
213	205	}
214	206
215		static __inline__ __m256i __DEFAULT_FN_ATTRS256
	207	static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR
216	208	_mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D)
217	209	{
218	210	return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,

lib/include/avx512vlvnniintrin.h+29-34

...	...	@@ -15,6 +15,16 @@
15	15	#define __AVX512VLVNNIINTRIN_H
16	16
17	17	/* Define the default attributes for the functions in this file. */
	18	#if defined(__cplusplus) && (__cplusplus >= 201103L)
	19	#define __DEFAULT_FN_ATTRS128 \
	20	__attribute__((__always_inline__, __nodebug__, \
	21	__target__("avx512vl,avx512vnni"), \
	22	__min_vector_width__(128))) constexpr
	23	#define __DEFAULT_FN_ATTRS256 \
	24	__attribute__((__always_inline__, __nodebug__, \
	25	__target__("avx512vl,avx512vnni"), \
	26	__min_vector_width__(256))) constexpr
	27	#else
18	28	#define __DEFAULT_FN_ATTRS128 \
19	29	__attribute__((__always_inline__, __nodebug__, \
20	30	__target__("avx512vl,avx512vnni"), \
...	...	@@ -23,6 +33,7 @@
23	33	__attribute__((__always_inline__, __nodebug__, \
24	34	__target__("avx512vl,avx512vnni"), \
25	35	__min_vector_width__(256)))
	36	#endif
26	37
27	38	/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
28	39	/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
...	...	@@ -180,128 +191,112 @@
180	191	((__m128i)__builtin_ia32_vpdpwssds128((__v4si)(S), (__v8hi)(A), (__v8hi)(B)))
181	192
182	193	static __inline__ __m256i __DEFAULT_FN_ATTRS256
183		_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
184		{
	194	_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) {
185	195	return (__m256i)__builtin_ia32_selectd_256(__U,
186	196	(__v8si)_mm256_dpbusd_epi32(__S, __A, __B),
187	197	(__v8si)__S);
188	198	}
189	199
190	200	static __inline__ __m256i __DEFAULT_FN_ATTRS256
191		_mm256_maskz_dpbusd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
192		{
	201	_mm256_maskz_dpbusd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) {
193	202	return (__m256i)__builtin_ia32_selectd_256(__U,
194	203	(__v8si)_mm256_dpbusd_epi32(__S, __A, __B),
195	204	(__v8si)_mm256_setzero_si256());
196	205	}
197	206
198	207	static __inline__ __m256i __DEFAULT_FN_ATTRS256
199		_mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
200		{
	208	_mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) {
201	209	return (__m256i)__builtin_ia32_selectd_256(__U,
202	210	(__v8si)_mm256_dpbusds_epi32(__S, __A, __B),
203	211	(__v8si)__S);
204	212	}
205	213
206		static __inline__ __m256i __DEFAULT_FN_ATTRS256
207		_mm256_maskz_dpbusds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
208		{
	214	static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maskz_dpbusds_epi32(
	215	__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) {
209	216	return (__m256i)__builtin_ia32_selectd_256(__U,
210	217	(__v8si)_mm256_dpbusds_epi32(__S, __A, __B),
211	218	(__v8si)_mm256_setzero_si256());
212	219	}
213	220
214	221	static __inline__ __m256i __DEFAULT_FN_ATTRS256
215		_mm256_mask_dpwssd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
216		{
	222	_mm256_mask_dpwssd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) {
217	223	return (__m256i)__builtin_ia32_selectd_256(__U,
218	224	(__v8si)_mm256_dpwssd_epi32(__S, __A, __B),
219	225	(__v8si)__S);
220	226	}
221	227
222	228	static __inline__ __m256i __DEFAULT_FN_ATTRS256
223		_mm256_maskz_dpwssd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
224		{
	229	_mm256_maskz_dpwssd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) {
225	230	return (__m256i)__builtin_ia32_selectd_256(__U,
226	231	(__v8si)_mm256_dpwssd_epi32(__S, __A, __B),
227	232	(__v8si)_mm256_setzero_si256());
228	233	}
229	234
230	235	static __inline__ __m256i __DEFAULT_FN_ATTRS256
231		_mm256_mask_dpwssds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
232		{
	236	_mm256_mask_dpwssds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) {
233	237	return (__m256i)__builtin_ia32_selectd_256(__U,
234	238	(__v8si)_mm256_dpwssds_epi32(__S, __A, __B),
235	239	(__v8si)__S);
236	240	}
237	241
238		static __inline__ __m256i __DEFAULT_FN_ATTRS256
239		_mm256_maskz_dpwssds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
240		{
	242	static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maskz_dpwssds_epi32(
	243	__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) {
241	244	return (__m256i)__builtin_ia32_selectd_256(__U,
242	245	(__v8si)_mm256_dpwssds_epi32(__S, __A, __B),
243	246	(__v8si)_mm256_setzero_si256());
244	247	}
245	248
246	249	static __inline__ __m128i __DEFAULT_FN_ATTRS128
247		_mm_mask_dpbusd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
248		{
	250	_mm_mask_dpbusd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) {
249	251	return (__m128i)__builtin_ia32_selectd_128(__U,
250	252	(__v4si)_mm_dpbusd_epi32(__S, __A, __B),
251	253	(__v4si)__S);
252	254	}
253	255
254	256	static __inline__ __m128i __DEFAULT_FN_ATTRS128
255		_mm_maskz_dpbusd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
256		{
	257	_mm_maskz_dpbusd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) {
257	258	return (__m128i)__builtin_ia32_selectd_128(__U,
258	259	(__v4si)_mm_dpbusd_epi32(__S, __A, __B),
259	260	(__v4si)_mm_setzero_si128());
260	261	}
261	262
262	263	static __inline__ __m128i __DEFAULT_FN_ATTRS128
263		_mm_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
264		{
	264	_mm_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) {
265	265	return (__m128i)__builtin_ia32_selectd_128(__U,
266	266	(__v4si)_mm_dpbusds_epi32(__S, __A, __B),
267	267	(__v4si)__S);
268	268	}
269	269
270	270	static __inline__ __m128i __DEFAULT_FN_ATTRS128
271		_mm_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
272		{
	271	_mm_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) {
273	272	return (__m128i)__builtin_ia32_selectd_128(__U,
274	273	(__v4si)_mm_dpbusds_epi32(__S, __A, __B),
275	274	(__v4si)_mm_setzero_si128());
276	275	}
277	276
278	277	static __inline__ __m128i __DEFAULT_FN_ATTRS128
279		_mm_mask_dpwssd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
280		{
	278	_mm_mask_dpwssd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) {
281	279	return (__m128i)__builtin_ia32_selectd_128(__U,
282	280	(__v4si)_mm_dpwssd_epi32(__S, __A, __B),
283	281	(__v4si)__S);
284	282	}
285	283
286	284	static __inline__ __m128i __DEFAULT_FN_ATTRS128
287		_mm_maskz_dpwssd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
288		{
	285	_mm_maskz_dpwssd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) {
289	286	return (__m128i)__builtin_ia32_selectd_128(__U,
290	287	(__v4si)_mm_dpwssd_epi32(__S, __A, __B),
291	288	(__v4si)_mm_setzero_si128());
292	289	}
293	290
294	291	static __inline__ __m128i __DEFAULT_FN_ATTRS128
295		_mm_mask_dpwssds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
296		{
	292	_mm_mask_dpwssds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) {
297	293	return (__m128i)__builtin_ia32_selectd_128(__U,
298	294	(__v4si)_mm_dpwssds_epi32(__S, __A, __B),
299	295	(__v4si)__S);
300	296	}
301	297
302	298	static __inline__ __m128i __DEFAULT_FN_ATTRS128
303		_mm_maskz_dpwssds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
304		{
	299	_mm_maskz_dpwssds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) {
305	300	return (__m128i)__builtin_ia32_selectd_128(__U,
306	301	(__v4si)_mm_dpwssds_epi32(__S, __A, __B),
307	302	(__v4si)_mm_setzero_si128());

lib/include/avx512vnniintrin.h+32-35

...	...	@@ -15,102 +15,99 @@
15	15	#define __AVX512VNNIINTRIN_H
16	16
17	17	/* Define the default attributes for the functions in this file. */
	18	#if defined(__cplusplus) && (__cplusplus >= 201103L)
	19	#define __DEFAULT_FN_ATTRS \
	20	__attribute__((__always_inline__, __nodebug__, __target__("avx512vnni"), \
	21	__min_vector_width__(512))) constexpr
	22	#else
18	23	#define __DEFAULT_FN_ATTRS \
19	24	__attribute__((__always_inline__, __nodebug__, __target__("avx512vnni"), \
20	25	__min_vector_width__(512)))
	26	#endif
21	27
22		static __inline__ __m512i __DEFAULT_FN_ATTRS
23		_mm512_dpbusd_epi32(__m512i __S, __m512i __A, __m512i __B)
24		{
	28	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_dpbusd_epi32(__m512i __S,
	29	__m512i __A,
	30	__m512i __B) {
25	31	return (__m512i)__builtin_ia32_vpdpbusd512((__v16si)__S, (__v64qu)__A,
26	32	(__v64qi)__B);
27	33	}
28	34
29	35	static __inline__ __m512i __DEFAULT_FN_ATTRS
30		_mm512_mask_dpbusd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
31		{
	36	_mm512_mask_dpbusd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B) {
32	37	return (__m512i)__builtin_ia32_selectd_512(__U,
33	38	(__v16si)_mm512_dpbusd_epi32(__S, __A, __B),
34	39	(__v16si)__S);
35	40	}
36	41
37		static __inline__ __m512i __DEFAULT_FN_ATTRS
38		_mm512_maskz_dpbusd_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
39		{
	42	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_maskz_dpbusd_epi32(
	43	__mmask16 __U, __m512i __S, __m512i __A, __m512i __B) {
40	44	return (__m512i)__builtin_ia32_selectd_512(__U,
41	45	(__v16si)_mm512_dpbusd_epi32(__S, __A, __B),
42	46	(__v16si)_mm512_setzero_si512());
43	47	}
44	48
45		static __inline__ __m512i __DEFAULT_FN_ATTRS
46		_mm512_dpbusds_epi32(__m512i __S, __m512i __A, __m512i __B)
47		{
	49	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_dpbusds_epi32(__m512i __S,
	50	__m512i __A,
	51	__m512i __B) {
48	52	return (__m512i)__builtin_ia32_vpdpbusds512((__v16si)__S, (__v64qu)__A,
49	53	(__v64qi)__B);
50	54	}
51	55
52		static __inline__ __m512i __DEFAULT_FN_ATTRS
53		_mm512_mask_dpbusds_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
54		{
	56	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_mask_dpbusds_epi32(
	57	__m512i __S, __mmask16 __U, __m512i __A, __m512i __B) {
55	58	return (__m512i)__builtin_ia32_selectd_512(__U,
56	59	(__v16si)_mm512_dpbusds_epi32(__S, __A, __B),
57	60	(__v16si)__S);
58	61	}
59	62
60		static __inline__ __m512i __DEFAULT_FN_ATTRS
61		_mm512_maskz_dpbusds_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
62		{
	63	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_maskz_dpbusds_epi32(
	64	__mmask16 __U, __m512i __S, __m512i __A, __m512i __B) {
63	65	return (__m512i)__builtin_ia32_selectd_512(__U,
64	66	(__v16si)_mm512_dpbusds_epi32(__S, __A, __B),
65	67	(__v16si)_mm512_setzero_si512());
66	68	}
67	69
68		static __inline__ __m512i __DEFAULT_FN_ATTRS
69		_mm512_dpwssd_epi32(__m512i __S, __m512i __A, __m512i __B)
70		{
	70	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_dpwssd_epi32(__m512i __S,
	71	__m512i __A,
	72	__m512i __B) {
71	73	return (__m512i)__builtin_ia32_vpdpwssd512((__v16si)__S, (__v32hi)__A,
72	74	(__v32hi)__B);
73	75	}
74	76
75	77	static __inline__ __m512i __DEFAULT_FN_ATTRS
76		_mm512_mask_dpwssd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
77		{
	78	_mm512_mask_dpwssd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B) {
78	79	return (__m512i)__builtin_ia32_selectd_512(__U,
79	80	(__v16si)_mm512_dpwssd_epi32(__S, __A, __B),
80	81	(__v16si)__S);
81	82	}
82	83
83		static __inline__ __m512i __DEFAULT_FN_ATTRS
84		_mm512_maskz_dpwssd_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
85		{
	84	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_maskz_dpwssd_epi32(
	85	__mmask16 __U, __m512i __S, __m512i __A, __m512i __B) {
86	86	return (__m512i)__builtin_ia32_selectd_512(__U,
87	87	(__v16si)_mm512_dpwssd_epi32(__S, __A, __B),
88	88	(__v16si)_mm512_setzero_si512());
89	89	}
90	90
91		static __inline__ __m512i __DEFAULT_FN_ATTRS
92		_mm512_dpwssds_epi32(__m512i __S, __m512i __A, __m512i __B)
93		{
	91	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_dpwssds_epi32(__m512i __S,
	92	__m512i __A,
	93	__m512i __B) {
94	94	return (__m512i)__builtin_ia32_vpdpwssds512((__v16si)__S, (__v32hi)__A,
95	95	(__v32hi)__B);
96	96	}
97	97
98		static __inline__ __m512i __DEFAULT_FN_ATTRS
99		_mm512_mask_dpwssds_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
100		{
	98	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_mask_dpwssds_epi32(
	99	__m512i __S, __mmask16 __U, __m512i __A, __m512i __B) {
101	100	return (__m512i)__builtin_ia32_selectd_512(__U,
102	101	(__v16si)_mm512_dpwssds_epi32(__S, __A, __B),
103	102	(__v16si)__S);
104	103	}
105	104
106		static __inline__ __m512i __DEFAULT_FN_ATTRS
107		_mm512_maskz_dpwssds_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
108		{
	105	static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_maskz_dpwssds_epi32(
	106	__mmask16 __U, __m512i __S, __m512i __A, __m512i __B) {
109	107	return (__m512i)__builtin_ia32_selectd_512(__U,
110	108	(__v16si)_mm512_dpwssds_epi32(__S, __A, __B),
111	109	(__v16si)_mm512_setzero_si512());
112	110	}
113	111
114	112	#undef __DEFAULT_FN_ATTRS
115
116	113	#endif

lib/include/avx512vp2intersectintrin.h+1-1

...	...	@@ -22,7 +22,7 @@
22	22	*===-----------------------------------------------------------------------===
23	23	*/
24	24	#ifndef __IMMINTRIN_H
25		#error "Never use <avx512vp2intersect.h> directly; include <immintrin.h> instead."
	25	#error "Never use <avx512vp2intersectintrin.h> directly; include <immintrin.h> instead."
26	26	#endif
27	27
28	28	#ifndef _AVX512VP2INTERSECT_H

lib/include/avxvnniintrin.h+23-18

...	...	@@ -40,8 +40,21 @@
40	40
41	41	/* Intrinsics with _avx_ prefix are for compatibility with msvc. */
42	42	/* Define the default attributes for the functions in this file. */
43		#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, __target__("avxvnni"), __min_vector_width__(256)))
44		#define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avxvnni"), __min_vector_width__(128)))
	43	#if defined(__cplusplus) && (__cplusplus >= 201103L)
	44	#define __DEFAULT_FN_ATTRS256 \
	45	__attribute__((__always_inline__, __nodebug__, __target__("avxvnni"), \
	46	__min_vector_width__(256))) constexpr
	47	#define __DEFAULT_FN_ATTRS128 \
	48	__attribute__((__always_inline__, __nodebug__, __target__("avxvnni"), \
	49	__min_vector_width__(128))) constexpr
	50	#else
	51	#define __DEFAULT_FN_ATTRS256 \
	52	__attribute__((__always_inline__, __nodebug__, __target__("avxvnni"), \
	53	__min_vector_width__(256)))
	54	#define __DEFAULT_FN_ATTRS128 \
	55	__attribute__((__always_inline__, __nodebug__, __target__("avxvnni"), \
	56	__min_vector_width__(128)))
	57	#endif
45	58
46	59	/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
47	60	/// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
...	...	@@ -61,8 +74,7 @@
61	74	/// DST[MAX:256] := 0
62	75	/// \endcode
63	76	static __inline__ __m256i __DEFAULT_FN_ATTRS256
64		_mm256_dpbusd_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
65		{
	77	_mm256_dpbusd_avx_epi32(__m256i __S, __m256i __A, __m256i __B) {
66	78	return (__m256i)__builtin_ia32_vpdpbusd256((__v8si)__S, (__v32qu)__A,
67	79	(__v32qi)__B);
68	80	}
...	...	@@ -85,8 +97,7 @@ _mm256_dpbusd_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
85	97	/// DST[MAX:256] := 0
86	98	/// \endcode
87	99	static __inline__ __m256i __DEFAULT_FN_ATTRS256
88		_mm256_dpbusds_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
89		{
	100	_mm256_dpbusds_avx_epi32(__m256i __S, __m256i __A, __m256i __B) {
90	101	return (__m256i)__builtin_ia32_vpdpbusds256((__v8si)__S, (__v32qu)__A,
91	102	(__v32qi)__B);
92	103	}
...	...	@@ -107,8 +118,7 @@ _mm256_dpbusds_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
107	118	/// DST[MAX:256] := 0
108	119	/// \endcode
109	120	static __inline__ __m256i __DEFAULT_FN_ATTRS256
110		_mm256_dpwssd_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
111		{
	121	_mm256_dpwssd_avx_epi32(__m256i __S, __m256i __A, __m256i __B) {
112	122	return (__m256i)__builtin_ia32_vpdpwssd256((__v8si)__S, (__v16hi)__A,
113	123	(__v16hi)__B);
114	124	}
...	...	@@ -129,8 +139,7 @@ _mm256_dpwssd_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
129	139	/// DST[MAX:256] := 0
130	140	/// \endcode
131	141	static __inline__ __m256i __DEFAULT_FN_ATTRS256
132		_mm256_dpwssds_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
133		{
	142	_mm256_dpwssds_avx_epi32(__m256i __S, __m256i __A, __m256i __B) {
134	143	return (__m256i)__builtin_ia32_vpdpwssds256((__v8si)__S, (__v16hi)__A,
135	144	(__v16hi)__B);
136	145	}
...	...	@@ -153,8 +162,7 @@ _mm256_dpwssds_avx_epi32(__m256i __S, __m256i __A, __m256i __B)
153	162	/// DST[MAX:128] := 0
154	163	/// \endcode
155	164	static __inline__ __m128i __DEFAULT_FN_ATTRS128
156		_mm_dpbusd_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
157		{
	165	_mm_dpbusd_avx_epi32(__m128i __S, __m128i __A, __m128i __B) {
158	166	return (__m128i)__builtin_ia32_vpdpbusd128((__v4si)__S, (__v16qu)__A,
159	167	(__v16qi)__B);
160	168	}
...	...	@@ -177,8 +185,7 @@ _mm_dpbusd_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
177	185	/// DST[MAX:128] := 0
178	186	/// \endcode
179	187	static __inline__ __m128i __DEFAULT_FN_ATTRS128
180		_mm_dpbusds_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
181		{
	188	_mm_dpbusds_avx_epi32(__m128i __S, __m128i __A, __m128i __B) {
182	189	return (__m128i)__builtin_ia32_vpdpbusds128((__v4si)__S, (__v16qu)__A,
183	190	(__v16qi)__B);
184	191	}
...	...	@@ -199,8 +206,7 @@ _mm_dpbusds_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
199	206	/// DST[MAX:128] := 0
200	207	/// \endcode
201	208	static __inline__ __m128i __DEFAULT_FN_ATTRS128
202		_mm_dpwssd_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
203		{
	209	_mm_dpwssd_avx_epi32(__m128i __S, __m128i __A, __m128i __B) {
204	210	return (__m128i)__builtin_ia32_vpdpwssd128((__v4si)__S, (__v8hi)__A,
205	211	(__v8hi)__B);
206	212	}
...	...	@@ -221,8 +227,7 @@ _mm_dpwssd_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
221	227	/// DST[MAX:128] := 0
222	228	/// \endcode
223	229	static __inline__ __m128i __DEFAULT_FN_ATTRS128
224		_mm_dpwssds_avx_epi32(__m128i __S, __m128i __A, __m128i __B)
225		{
	230	_mm_dpwssds_avx_epi32(__m128i __S, __m128i __A, __m128i __B) {
226	231	return (__m128i)__builtin_ia32_vpdpwssds128((__v4si)__S, (__v8hi)__A,
227	232	(__v8hi)__B);
228	233	}

lib/include/crc32intrin.h+10-8

...	...	@@ -10,8 +10,14 @@
10	10	#ifndef __CRC32INTRIN_H
11	11	#define __CRC32INTRIN_H
12	12
	13	/// We only declare crc32 as a constexpr if we are compiling C++ code
	14	#if defined(__cplusplus) && (__cplusplus >= 201103L)
	15	#define __DEFAULT_FN_ATTRS \
	16	__attribute__((__always_inline__, __nodebug__, __target__("crc32"))) constexpr
	17	#else
13	18	#define __DEFAULT_FN_ATTRS \
14	19	__attribute__((__always_inline__, __nodebug__, __target__("crc32")))
	20	#endif
15	21
16	22	/// Adds the unsigned integer operand to the CRC-32C checksum of the
17	23	/// unsigned char operand.
...	...	@@ -28,8 +34,7 @@
28	34	/// \returns The result of adding operand \a __C to the CRC-32C checksum of
29	35	/// operand \a __D.
30	36	static __inline__ unsigned int __DEFAULT_FN_ATTRS
31		_mm_crc32_u8(unsigned int __C, unsigned char __D)
32		{
	37	_mm_crc32_u8(unsigned int __C, unsigned char __D) {
33	38	return __builtin_ia32_crc32qi(__C, __D);
34	39	}
35	40
...	...	@@ -48,8 +53,7 @@ _mm_crc32_u8(unsigned int __C, unsigned char __D)
48	53	/// \returns The result of adding operand \a __C to the CRC-32C checksum of
49	54	/// operand \a __D.
50	55	static __inline__ unsigned int __DEFAULT_FN_ATTRS
51		_mm_crc32_u16(unsigned int __C, unsigned short __D)
52		{
	56	_mm_crc32_u16(unsigned int __C, unsigned short __D) {
53	57	return __builtin_ia32_crc32hi(__C, __D);
54	58	}
55	59
...	...	@@ -68,8 +72,7 @@ _mm_crc32_u16(unsigned int __C, unsigned short __D)
68	72	/// \returns The result of adding operand \a __C to the CRC-32C checksum of
69	73	/// operand \a __D.
70	74	static __inline__ unsigned int __DEFAULT_FN_ATTRS
71		_mm_crc32_u32(unsigned int __C, unsigned int __D)
72		{
	75	_mm_crc32_u32(unsigned int __C, unsigned int __D) {
73	76	return __builtin_ia32_crc32si(__C, __D);
74	77	}
75	78
...	...	@@ -89,8 +92,7 @@ _mm_crc32_u32(unsigned int __C, unsigned int __D)
89	92	/// \returns The result of adding operand \a __C to the CRC-32C checksum of
90	93	/// operand \a __D.
91	94	static __inline__ unsigned long long __DEFAULT_FN_ATTRS
92		_mm_crc32_u64(unsigned long long __C, unsigned long long __D)
93		{
	95	_mm_crc32_u64(unsigned long long __C, unsigned long long __D) {
94	96	return __builtin_ia32_crc32di(__C, __D);
95	97	}
96	98	#endif /* __x86_64__ */

lib/include/emmintrin.h+8-8

...	...	@@ -279,8 +279,8 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS _mm_sqrt_pd(__m128d __a) {
279	279	/// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
280	280	/// minimum value between both operands. The upper 64 bits are copied from
281	281	/// the upper 64 bits of the first source operand.
282		static __inline__ __m128d __DEFAULT_FN_ATTRS _mm_min_sd(__m128d __a,
283		__m128d __b) {
	282	static __inline__ __m128d __DEFAULT_FN_ATTRS_CONSTEXPR _mm_min_sd(__m128d __a,
	283	__m128d __b) {
284	284	return __builtin_ia32_minsd((__v2df)__a, (__v2df)__b);
285	285	}
286	286
...	...	@@ -325,8 +325,8 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS_CONSTEXPR _mm_min_pd(__m128d __a,
325	325	/// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
326	326	/// maximum value between both operands. The upper 64 bits are copied from
327	327	/// the upper 64 bits of the first source operand.
328		static __inline__ __m128d __DEFAULT_FN_ATTRS _mm_max_sd(__m128d __a,
329		__m128d __b) {
	328	static __inline__ __m128d __DEFAULT_FN_ATTRS_CONSTEXPR _mm_max_sd(__m128d __a,
	329	__m128d __b) {
330	330	return __builtin_ia32_maxsd((__v2df)__a, (__v2df)__b);
331	331	}
332	332
...	...	@@ -1343,7 +1343,7 @@ _mm_cvtepi32_pd(__m128i __a) {
1343	1343	/// \returns A 128-bit vector of [4 x i32] whose lower 64 bits contain the
1344	1344	/// converted values. The upper 64 bits are set to zero.
1345	1345	static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvtpd_epi32(__m128d __a) {
1346		return __builtin_ia32_cvtpd2dq((__v2df)__a);
	1346	return (__m128i)__builtin_ia32_cvtpd2dq((__v2df)__a);
1347	1347	}
1348	1348
1349	1349	/// Converts the low-order element of a 128-bit vector of [2 x double]
...	...	@@ -2481,9 +2481,9 @@ _mm_mul_epu32(__m128i __a, __m128i __b) {
2481	2481	/// A 128-bit integer vector containing one of the source operands.
2482	2482	/// \returns A [2 x i64] vector containing the sums of the sets of absolute
2483	2483	/// differences between both operands.
2484		static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sad_epu8(__m128i __a,
2485		__m128i __b) {
2486		return __builtin_ia32_psadbw128((__v16qi)__a, (__v16qi)__b);
	2484	static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR
	2485	_mm_sad_epu8(__m128i __a, __m128i __b) {
	2486	return __builtin_ia32_psadbw128((__v16qu)__a, (__v16qu)__b);
2487	2487	}
2488	2488
2489	2489	/// Subtracts the corresponding 8-bit integer values in the operands.

lib/include/endian.h created+91

...	...	@@ -0,0 +1,91 @@
	1	//===-- Definition of macros from endian.h --------------------------------===//
	2	//
	3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	4	// See https://llvm.org/LICENSE.txt for license information.
	5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	6	//
	7	//===----------------------------------------------------------------------===//
	8
	9	#ifndef __CLANG_ENDIAN_H
	10	#define __CLANG_ENDIAN_H
	11
	12	// If the system has an endian.h, let's use that instead.
	13	#if __has_include_next(<endian.h>)
	14	#include_next <endian.h>
	15	#else
	16
	17	#include <stdint.h>
	18
	19	// Implementation taken from llvm libc endian-macros.h.
	20	#ifdef __cplusplus
	21	#define __CLANG_ENDIAN_CAST(cast, type, value) (cast<type>(value))
	22	#else
	23	#define __CLANG_ENDIAN_CAST(cast, type, value) ((type)(value))
	24	#endif
	25
	26	#define LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
	27	#define BIG_ENDIAN __ORDER_BIG_ENDIAN__
	28	#define PDP_ENDIAN __ORDER_PDP_ENDIAN__
	29	#define BYTE_ORDER __BYTE_ORDER__
	30
	31	// Define some compatibility macros if they are not defined.
	32	#ifndef __BYTE_ORDER
	33	#define __BYTE_ORDER BYTE_ORDER
	34	#endif
	35	#ifndef __LITTLE_ENDIAN
	36	#define __LITTLE_ENDIAN LITTLE_ENDIAN
	37	#endif
	38	#ifndef __BIG_ENDIAN
	39	#define __BIG_ENDIAN BIG_ENDIAN
	40	#endif
	41	#ifndef __PDP_ENDIAN
	42	#define __PDP_ENDIAN PDP_ENDIAN
	43	#endif
	44
	45	#if BYTE_ORDER == LITTLE_ENDIAN
	46
	47	#define htobe16(x) \
	48	__builtin_bswap16(__CLANG_ENDIAN_CAST(static_cast, uint16_t, x))
	49	#define htobe32(x) \
	50	__builtin_bswap32(__CLANG_ENDIAN_CAST(static_cast, uint32_t, x))
	51	#define htobe64(x) \
	52	__builtin_bswap64(__CLANG_ENDIAN_CAST(static_cast, uint64_t, x))
	53	#define htole16(x) __CLANG_ENDIAN_CAST(static_cast, uint16_t, x)
	54	#define htole32(x) __CLANG_ENDIAN_CAST(static_cast, uint32_t, x)
	55	#define htole64(x) __CLANG_ENDIAN_CAST(static_cast, uint64_t, x)
	56	#define be16toh(x) \
	57	__builtin_bswap16(__CLANG_ENDIAN_CAST(static_cast, uint16_t, x))
	58	#define be32toh(x) \
	59	__builtin_bswap32(__CLANG_ENDIAN_CAST(static_cast, uint32_t, x))
	60	#define be64toh(x) \
	61	__builtin_bswap64(__CLANG_ENDIAN_CAST(static_cast, uint64_t, x))
	62	#define le16toh(x) __CLANG_ENDIAN_CAST(static_cast, uint16_t, x)
	63	#define le32toh(x) __CLANG_ENDIAN_CAST(static_cast, uint32_t, x)
	64	#define le64toh(x) __CLANG_ENDIAN_CAST(static_cast, uint64_t, x)
	65
	66	#elif BYTE_ORDER == BIG_ENDIAN
	67
	68	#define htobe16(x) __CLANG_ENDIAN_CAST(static_cast, uint16_t, x)
	69	#define htobe32(x) __CLANG_ENDIAN_CAST(static_cast, uint32_t, x)
	70	#define htobe64(x) __CLANG_ENDIAN_CAST(static_cast, uint64_t, x)
	71	#define htole16(x) \
	72	__builtin_bswap16(__CLANG_ENDIAN_CAST(static_cast, uint16_t, x))
	73	#define htole32(x) \
	74	__builtin_bswap32(__CLANG_ENDIAN_CAST(static_cast, uint32_t, x))
	75	#define htole64(x) \
	76	__builtin_bswap64(__CLANG_ENDIAN_CAST(static_cast, uint64_t, x))
	77	#define be16toh(x) __CLANG_ENDIAN_CAST(static_cast, uint16_t, x)
	78	#define be32toh(x) __CLANG_ENDIAN_CAST(static_cast, uint32_t, x)
	79	#define be64toh(x) __CLANG_ENDIAN_CAST(static_cast, uint64_t, x)
	80	#define le16toh(x) \
	81	__builtin_bswap16(__CLANG_ENDIAN_CAST(static_cast, uint16_t, x))
	82	#define le32toh(x) \
	83	__builtin_bswap32(__CLANG_ENDIAN_CAST(static_cast, uint32_t, x))
	84	#define le64toh(x) \
	85	__builtin_bswap64(__CLANG_ENDIAN_CAST(static_cast, uint64_t, x))
	86
	87	#else
	88	#error "Unsupported endianness"
	89	#endif
	90	#endif // __has_include_next
	91	#endif // __CLANG_ENDIAN_H

lib/include/hvx_hexagon_protos.h+102-80

...	...	@@ -4577,8 +4577,9 @@
4577	4577	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4578	4578	/* ==========================================================================
4579	4579	Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf)
4580		C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu,
4581		HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4580	C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
	4581	Instruction Type: CVI_VX_DV
	4582	Execution Slots: SLOT23
4582	4583	========================================================================== */
4583	4584
4584	4585	#define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \
...	...	@@ -4636,8 +4637,9 @@
4636	4637	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4637	4638	/* ==========================================================================
4638	4639	Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf)
4639		C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu,
4640		HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23
	4640	C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
	4641	Instruction Type: CVI_VX
	4642	Execution Slots: SLOT23
4641	4643	========================================================================== */
4642	4644
4643	4645	#define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \
...	...	@@ -4647,8 +4649,9 @@
4647	4649	#if __HVX_ARCH__ >= 73
4648	4650	/* ==========================================================================
4649	4651	Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf)
4650		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu,
4651		HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
	4652	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
	4653	Instruction Type: CVI_VA
	4654	Execution Slots: SLOT0123
4652	4655	========================================================================== */
4653	4656
4654	4657	#define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \
...	...	@@ -4659,9 +4662,9 @@
4659	4662	#if __HVX_ARCH__ >= 73
4660	4663	/* ==========================================================================
4661	4664	Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf)
4662		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred
4663		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
4664		Slots: SLOT0123
	4665	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	4666	Instruction Type: CVI_VA
	4667	Execution Slots: SLOT0123
4665	4668	========================================================================== */
4666	4669
4667	4670	#define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \
...	...	@@ -4675,9 +4678,9 @@
4675	4678	#if __HVX_ARCH__ >= 73
4676	4679	/* ==========================================================================
4677	4680	Assembly Syntax: Qx4\|=vcmp.gt(Vu32.bf,Vv32.bf)
4678		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred
4679		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
4680		Slots: SLOT0123
	4681	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	4682	Instruction Type: CVI_VA
	4683	Execution Slots: SLOT0123
4681	4684	========================================================================== */
4682	4685
4683	4686	#define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \
...	...	@@ -4691,9 +4694,9 @@
4691	4694	#if __HVX_ARCH__ >= 73
4692	4695	/* ==========================================================================
4693	4696	Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf)
4694		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred
4695		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
4696		Slots: SLOT0123
	4697	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	4698	Instruction Type: CVI_VA
	4699	Execution Slots: SLOT0123
4697	4700	========================================================================== */
4698	4701
4699	4702	#define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \
...	...	@@ -4707,8 +4710,9 @@
4707	4710	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4708	4711	/* ==========================================================================
4709	4712	Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf)
4710		C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu,
4711		HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23
	4713	C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
	4714	Instruction Type: CVI_VX_LATE
	4715	Execution Slots: SLOT23
4712	4716	========================================================================== */
4713	4717
4714	4718	#define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \
...	...	@@ -4718,8 +4722,9 @@
4718	4722	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4719	4723	/* ==========================================================================
4720	4724	Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf)
4721		C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu,
4722		HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23
	4725	C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
	4726	Instruction Type: CVI_VX_LATE
	4727	Execution Slots: SLOT23
4723	4728	========================================================================== */
4724	4729
4725	4730	#define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \
...	...	@@ -4729,8 +4734,9 @@
4729	4734	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4730	4735	/* ==========================================================================
4731	4736	Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf)
4732		C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu,
4733		HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4737	C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
	4738	Instruction Type: CVI_VX_DV
	4739	Execution Slots: SLOT23
4734	4740	========================================================================== */
4735	4741
4736	4742	#define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \
...	...	@@ -4740,9 +4746,9 @@
4740	4746	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4741	4747	/* ==========================================================================
4742	4748	Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf)
4743		C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair
4744		Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution
4745		Slots: SLOT23
	4749	C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
	4750	Instruction Type: CVI_VX_DV
	4751	Execution Slots: SLOT23
4746	4752	========================================================================== */
4747	4753
4748	4754	#define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \
...	...	@@ -4752,8 +4758,9 @@
4752	4758	#if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__
4753	4759	/* ==========================================================================
4754	4760	Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf)
4755		C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu,
4756		HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4761	C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, HVX_Vector Vv)
	4762	Instruction Type: CVI_VX_DV
	4763	Execution Slots: SLOT23
4757	4764	========================================================================== */
4758	4765
4759	4766	#define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \
...	...	@@ -4775,9 +4782,9 @@
4775	4782	#if __HVX_ARCH__ >= 79
4776	4783	/* ==========================================================================
4777	4784	Assembly Syntax: Vx32\|=vgetqfext(Vu32.x,Rt32)
4778		C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx,
4779		HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots:
4780		SLOT23
	4785	C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
	4786	Instruction Type: CVI_VX
	4787	Execution Slots: SLOT23
4781	4788	========================================================================== */
4782	4789
4783	4790	#define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \
...	...	@@ -4810,8 +4817,9 @@
4810	4817	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4811	4818	/* ==========================================================================
4812	4819	Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8)
4813		C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu,
4814		HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4820	C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, HVX_Vector Vv)
	4821	Instruction Type: CVI_VX_DV
	4822	Execution Slots: SLOT23
4815	4823	========================================================================== */
4816	4824
4817	4825	#define Q6_Whf_vadd_VV(Vu, Vv) \
...	...	@@ -4821,8 +4829,9 @@
4821	4829	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4822	4830	/* ==========================================================================
4823	4831	Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf)
4824		C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu,
4825		HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23
	4832	C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
	4833	Instruction Type: CVI_VX
	4834	Execution Slots: SLOT23
4826	4835	========================================================================== */
4827	4836
4828	4837	#define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \
...	...	@@ -4856,8 +4865,9 @@
4856	4865	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4857	4866	/* ==========================================================================
4858	4867	Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf)
4859		C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu,
4860		HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23
	4868	C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
	4869	Instruction Type: CVI_VX
	4870	Execution Slots: SLOT23
4861	4871	========================================================================== */
4862	4872
4863	4873	#define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \
...	...	@@ -4867,8 +4877,9 @@
4867	4877	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4868	4878	/* ==========================================================================
4869	4879	Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf)
4870		C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector
4871		Vv) Instruction Type: CVI_VX Execution Slots: SLOT23
	4880	C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
	4881	Instruction Type: CVI_VX
	4882	Execution Slots: SLOT23
4872	4883	========================================================================== */
4873	4884
4874	4885	#define Q6_V_vcvt_VhfVhf(Vu, Vv) \
...	...	@@ -4926,8 +4937,9 @@
4926	4937	#if __HVX_ARCH__ >= 79
4927	4938	/* ==========================================================================
4928	4939	Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w)
4929		C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector
4930		Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
	4940	C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector Vv)
	4941	Instruction Type: CVI_VS
	4942	Execution Slots: SLOT0123
4931	4943	========================================================================== */
4932	4944
4933	4945	#define Q6_V_vmerge_VVw(Vu, Vv) \
...	...	@@ -4937,8 +4949,9 @@
4937	4949	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4938	4950	/* ==========================================================================
4939	4951	Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8)
4940		C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu,
4941		HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4952	C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, HVX_Vector Vv)
	4953	Instruction Type: CVI_VX_DV
	4954	Execution Slots: SLOT23
4942	4955	========================================================================== */
4943	4956
4944	4957	#define Q6_Whf_vmpy_VV(Vu, Vv) \
...	...	@@ -4948,9 +4961,9 @@
4948	4961	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4949	4962	/* ==========================================================================
4950	4963	Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8)
4951		C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair
4952		Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution
4953		Slots: SLOT23
	4964	C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
	4965	Instruction Type: CVI_VX_DV
	4966	Execution Slots: SLOT23
4954	4967	========================================================================== */
4955	4968
4956	4969	#define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \
...	...	@@ -4960,8 +4973,9 @@
4960	4973	#if __HVX_ARCH__ >= 79
4961	4974	/* ==========================================================================
4962	4975	Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf)
4963		C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32
4964		Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4976	C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 Rt)
	4977	Instruction Type: CVI_VX_DV
	4978	Execution Slots: SLOT23
4965	4979	========================================================================== */
4966	4980
4967	4981	#define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \
...	...	@@ -4971,8 +4985,9 @@
4971	4985	#if __HVX_ARCH__ >= 79
4972	4986	/* ==========================================================================
4973	4987	Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf)
4974		C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu,
4975		Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	4988	C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, Word32 Rt)
	4989	Instruction Type: CVI_VX_DV
	4990	Execution Slots: SLOT23
4976	4991	========================================================================== */
4977	4992
4978	4993	#define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \
...	...	@@ -4982,8 +4997,9 @@
4982	4997	#if __HVX_ARCH__ >= 79
4983	4998	/* ==========================================================================
4984	4999	Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf)
4985		C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32
4986		Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	5000	C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 Rt)
	5001	Instruction Type: CVI_VX_DV
	5002	Execution Slots: SLOT23
4987	5003	========================================================================== */
4988	5004
4989	5005	#define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \
...	...	@@ -4993,8 +5009,9 @@
4993	5009	#if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__
4994	5010	/* ==========================================================================
4995	5011	Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8)
4996		C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu,
4997		HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23
	5012	C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, HVX_Vector Vv)
	5013	Instruction Type: CVI_VX_DV
	5014	Execution Slots: SLOT23
4998	5015	========================================================================== */
4999	5016
5000	5017	#define Q6_Whf_vsub_VV(Vu, Vv) \
...	...	@@ -5052,8 +5069,9 @@
5052	5069	#if __HVX_ARCH__ >= 81
5053	5070	/* ==========================================================================
5054	5071	Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8)
5055		C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector
5056		Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123
	5072	C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
	5073	Instruction Type: CVI_VA
	5074	Execution Slots: SLOT0123
5057	5075	========================================================================== */
5058	5076
5059	5077	#define Q6_V_valign4_VVR(Vu, Vv, Rt) \
...	...	@@ -5159,8 +5177,9 @@
5159	5177	#if __HVX_ARCH__ >= 81
5160	5178	/* ==========================================================================
5161	5179	Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
5162		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
5163		HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
	5180	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
	5181	Instruction Type: CVI_VA
	5182	Execution Slots: SLOT0123
5164	5183	========================================================================== */
5165	5184
5166	5185	#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \
...	...	@@ -5171,9 +5190,9 @@
5171	5190	#if __HVX_ARCH__ >= 81
5172	5191	/* ==========================================================================
5173	5192	Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
5174		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred
5175		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5176		Slots: SLOT0123
	5193	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	5194	Instruction Type: CVI_VA
	5195	Execution Slots: SLOT0123
5177	5196	========================================================================== */
5178	5197
5179	5198	#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \
...	...	@@ -5187,9 +5206,9 @@
5187	5206	#if __HVX_ARCH__ >= 81
5188	5207	/* ==========================================================================
5189	5208	Assembly Syntax: Qx4\|=vcmp.eq(Vu32.hf,Vv32.hf)
5190		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
5191		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5192		Slots: SLOT0123
	5209	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	5210	Instruction Type: CVI_VA
	5211	Execution Slots: SLOT0123
5193	5212	========================================================================== */
5194	5213
5195	5214	#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \
...	...	@@ -5203,9 +5222,9 @@
5203	5222	#if __HVX_ARCH__ >= 81
5204	5223	/* ==========================================================================
5205	5224	Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
5206		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred
5207		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5208		Slots: SLOT0123
	5225	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	5226	Instruction Type: CVI_VA
	5227	Execution Slots: SLOT0123
5209	5228	========================================================================== */
5210	5229
5211	5230	#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \
...	...	@@ -5219,8 +5238,9 @@
5219	5238	#if __HVX_ARCH__ >= 81
5220	5239	/* ==========================================================================
5221	5240	Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
5222		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
5223		HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
	5241	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
	5242	Instruction Type: CVI_VA
	5243	Execution Slots: SLOT0123
5224	5244	========================================================================== */
5225	5245
5226	5246	#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \
...	...	@@ -5231,9 +5251,9 @@
5231	5251	#if __HVX_ARCH__ >= 81
5232	5252	/* ==========================================================================
5233	5253	Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
5234		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred
5235		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5236		Slots: SLOT0123
	5254	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	5255	Instruction Type: CVI_VA
	5256	Execution Slots: SLOT0123
5237	5257	========================================================================== */
5238	5258
5239	5259	#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \
...	...	@@ -5247,9 +5267,9 @@
5247	5267	#if __HVX_ARCH__ >= 81
5248	5268	/* ==========================================================================
5249	5269	Assembly Syntax: Qx4\|=vcmp.eq(Vu32.sf,Vv32.sf)
5250		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
5251		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5252		Slots: SLOT0123
	5270	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	5271	Instruction Type: CVI_VA
	5272	Execution Slots: SLOT0123
5253	5273	========================================================================== */
5254	5274
5255	5275	#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \
...	...	@@ -5263,9 +5283,9 @@
5263	5283	#if __HVX_ARCH__ >= 81
5264	5284	/* ==========================================================================
5265	5285	Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
5266		C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred
5267		Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
5268		Slots: SLOT0123
	5286	C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
	5287	Instruction Type: CVI_VA
	5288	Execution Slots: SLOT0123
5269	5289	========================================================================== */
5270	5290
5271	5291	#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \
...	...	@@ -5375,8 +5395,9 @@
5375	5395	#if __HVX_ARCH__ >= 81
5376	5396	/* ==========================================================================
5377	5397	Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
5378		C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
5379		HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
	5398	C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, HVX_Vector Vv)
	5399	Instruction Type: CVI_VS
	5400	Execution Slots: SLOT0123
5380	5401	========================================================================== */
5381	5402
5382	5403	#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \
...	...	@@ -5386,8 +5407,9 @@
5386	5407	#if __HVX_ARCH__ >= 81
5387	5408	/* ==========================================================================
5388	5409	Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
5389		C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
5390		HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
	5410	C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, HVX_Vector Vv)
	5411	Instruction Type: CVI_VS
	5412	Execution Slots: SLOT0123
5391	5413	========================================================================== */
5392	5414
5393	5415	#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \

lib/include/immintrin.h+4-2

...	...	@@ -58,6 +58,10 @@
58	58
59	59	#include <avx512bitalgintrin.h>
60	60
	61	#include <avx512bmmintrin.h>
	62
	63	#include <avx512bmmvlintrin.h>
	64
61	65	#include <avx512cdintrin.h>
62	66
63	67	#include <avx512vpopcntdqintrin.h>
...	...	@@ -479,8 +483,6 @@ _storebe_i64(void * __P, long long __D) {
479	483
480	484	#include <amxavx512intrin.h>
481	485
482		#include <amxtf32intrin.h>
483
484	486	#include <avx512vp2intersectintrin.h>
485	487
486	488	#include <avx512vlvp2intersectintrin.h>

lib/include/intrin.h+20-10

...	...	@@ -44,8 +44,10 @@
44	44
45	45	#if __x86_64__
46	46	#define __LPTRINT_TYPE__ __int64
	47	#define __IPTRINT_TYPE__ __int64
47	48	#else
48	49	#define __LPTRINT_TYPE__ long
	50	#define __IPTRINT_TYPE__ int
49	51	#endif
50	52
51	53	#ifdef __cplusplus
...	...	@@ -95,12 +97,12 @@ void __outdword(unsigned short, unsigned long);
95	97	void __outdwordstring(unsigned short, unsigned long *, unsigned long);
96	98	void __outword(unsigned short, unsigned short);
97	99	void __outwordstring(unsigned short, unsigned short *, unsigned long);
98		unsigned long __readcr0(void);
99		unsigned long __readcr2(void);
	100	unsigned __LPTRINT_TYPE__ __readcr0(void);
	101	unsigned __LPTRINT_TYPE__ __readcr2(void);
100	102	unsigned __LPTRINT_TYPE__ __readcr3(void);
101	103	unsigned __LPTRINT_TYPE__ __readcr4(void);
102		unsigned __int64 __readcr8(void);
103		unsigned int __readdr(unsigned int);
	104	unsigned __LPTRINT_TYPE__ __readcr8(void);
	105	unsigned __IPTRINT_TYPE__ __readdr(unsigned int);
104	106	#ifdef __i386__
105	107	unsigned char __readfsbyte(unsigned long);
106	108	unsigned short __readfsword(unsigned long);
...	...	@@ -126,11 +128,12 @@ unsigned __int64 __ull_rshift(unsigned __int64, int);
126	128	void __vmx_off(void);
127	129	void __vmx_vmptrst(unsigned __int64 *);
128	130	void __wbinvd(void);
129		void __writecr0(unsigned int);
130		void __writecr3(unsigned __INTPTR_TYPE__);
131		void __writecr4(unsigned __INTPTR_TYPE__);
132		void __writecr8(unsigned __int64);
133		void __writedr(unsigned int, unsigned int);
	131	void __writecr0(unsigned __IPTRINT_TYPE__);
	132	void __writecr2(unsigned __IPTRINT_TYPE__);
	133	void __writecr3(unsigned __IPTRINT_TYPE__);
	134	void __writecr4(unsigned __IPTRINT_TYPE__);
	135	void __writecr8(unsigned __IPTRINT_TYPE__);
	136	void __writedr(unsigned int, unsigned __IPTRINT_TYPE__);
134	137	void __writefsbyte(unsigned long, unsigned char);
135	138	void __writefsdword(unsigned long, unsigned long);
136	139	void __writefsqword(unsigned long, unsigned __int64);
...	...	@@ -374,6 +377,9 @@ static __inline__ void __DEFAULT_FN_ATTRS __nop(void) {
374	377	\----------------------------------------------------------------------------/
375	378	#if defined(__aarch64__) \|\| defined(__arm64ec__)
376	379	unsigned __int64 __getReg(int);
	380	double __getRegFp(int _Reg);
	381	void __setReg(int, unsigned __int64);
	382	void __setRegFp(int, double);
377	383	unsigned char _interlockedbittestandreset_acq(long volatile *, long);
378	384	unsigned char _interlockedbittestandreset_nf(long volatile *, long);
379	385	unsigned char _interlockedbittestandreset_rel(long volatile *, long);
...	...	@@ -438,10 +444,13 @@ unsigned int _CountLeadingSigns(long);
438	444	unsigned int _CountLeadingSigns64(__int64);
439	445	unsigned int _CountOneBits(unsigned long);
440	446	unsigned int _CountOneBits64(unsigned __int64);
	447	unsigned int _CountTrailingZeros(unsigned long);
	448	unsigned int _CountTrailingZeros64(unsigned __int64);
441	449
442	450	unsigned int __hlt(unsigned int, ...);
443	451
444	452	void __cdecl __prefetch(const void *);
	453	void __cdecl __prefetch2(const void *, unsigned char);
445	454
446	455	#endif
447	456
...	...	@@ -474,7 +483,7 @@ static __inline__ unsigned __LPTRINT_TYPE__ __DEFAULT_FN_ATTRS __readcr3(void) {
474	483	}
475	484
476	485	static __inline__ void __DEFAULT_FN_ATTRS
477		__writecr3(unsigned __INTPTR_TYPE__ __cr3_val) {
	486	__writecr3(unsigned __IPTRINT_TYPE__ __cr3_val) {
478	487	__asm__ ("mov {%0, %%cr3\|cr3, %0}" : : "r"(__cr3_val) : "memory");
479	488	}
480	489	#endif
...	...	@@ -484,6 +493,7 @@ __writecr3(unsigned __INTPTR_TYPE__ __cr3_val) {
484	493	#endif
485	494
486	495	#undef __LPTRINT_TYPE__
	496	#undef __IPTRINT_TYPE__
487	497
488	498	#undef __DEFAULT_FN_ATTRS
489	499

lib/include/larchintrin.h+2

...	...	@@ -120,10 +120,12 @@ extern __inline int
120	120
121	121	#define __ibar(/ui15/ _1) __builtin_loongarch_ibar((_1))
122	122
	123	#ifdef __loongarch_hard_float
123	124	#define __movfcsr2gr(/ui5/ _1) __builtin_loongarch_movfcsr2gr((_1));
124	125
125	126	#define __movgr2fcsr(/ui5/ _1, _2) \
126	127	__builtin_loongarch_movgr2fcsr((_1), (unsigned int)_2);
	128	#endif
127	129
128	130	#define __syscall(/ui15/ _1) __builtin_loongarch_syscall((_1))
129	131

lib/include/llvm_libc_wrappers/ctype.h+3-2

...	...	@@ -9,13 +9,14 @@
9	9	#ifndef __CLANG_LLVM_LIBC_WRAPPERS_CTYPE_H__
10	10	#define __CLANG_LLVM_LIBC_WRAPPERS_CTYPE_H__
11	11
12		#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__)
	12	#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__) && \
	13	!defined(__SPIRV__)
13	14	#error "This file is for GPU offloading compilation only"
14	15	#endif
15	16
16	17	#include_next <ctype.h>
17	18
18		#if defined(__HIP__) \|\| defined(__CUDA__)
	19	#if defined(__HIP__) \|\| defined(__CUDA__) \|\| defined(__SPIRV__)
19	20	#define __LIBC_ATTRS __attribute__((device))
20	21	#else
21	22	#define __LIBC_ATTRS

lib/include/llvm_libc_wrappers/string.h+3-2

...	...	@@ -9,13 +9,14 @@
9	9	#ifndef __CLANG_LLVM_LIBC_WRAPPERS_STRING_H__
10	10	#define __CLANG_LLVM_LIBC_WRAPPERS_STRING_H__
11	11
12		#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__)
	12	#if !defined(_OPENMP) && !defined(__HIP__) && !defined(__CUDA__) && \
	13	!defined(__SPIRV__)
13	14	#error "This file is for GPU offloading compilation only"
14	15	#endif
15	16
16	17	#include_next <string.h>
17	18
18		#if defined(__HIP__) \|\| defined(__CUDA__)
	19	#if defined(__HIP__) \|\| defined(__CUDA__) \|\| defined(__SPIRV__)
19	20	#define __LIBC_ATTRS __attribute__((device))
20	21	#else
21	22	#define __LIBC_ATTRS

lib/include/module.modulemap+16-1

...	...	@@ -21,10 +21,19 @@ module _Builtin_intrinsics [system] [extern_c] {
21	21	export *
22	22	}
23	23
	24	explicit module bf16 {
	25	header "arm_bf16.h"
	26	export *
	27	}
	28
	29	explicit module fp16 {
	30	header "arm_fp16.h"
	31	export *
	32	}
	33
24	34	explicit module neon {
25	35	requires neon
26	36	header "arm_neon.h"
27		header "arm_fp16.h"
28	37	export *
29	38	}
30	39
...	...	@@ -41,6 +50,12 @@ module _Builtin_intrinsics [system] [extern_c] {
41	50
42	51	header "arm64intr.h"
43	52	export *
	53
	54	explicit module neon {
	55	requires neon
	56	header "arm64_neon.h"
	57	export *
	58	}
44	59	}
45	60
46	61	explicit module intel {

lib/include/openmp_wrappers/__clang_openmp_device_functions.h+14

...	...	@@ -55,6 +55,20 @@ extern "C" {
55	55	#pragma omp end declare variant
56	56	#endif
57	57
	58	#ifdef __SPIRV__
	59	#pragma omp begin declare variant match( \
	60	device = {arch(spirv64)}, implementation = {extension(match_any)})
	61
	62	#define __OPENMP_SPIRV__
	63
	64	/// Include declarations for libdevice functions.
	65	#include <__clang_spirv_libdevice_declares.h>
	66
	67	#undef __OPENMP_SPIRV__
	68
	69	#pragma omp end declare variant
	70	#endif
	71
58	72	#ifdef __cplusplus
59	73	} // extern "C"
60	74	#endif

lib/include/openmp_wrappers/complex+7-1

...	...	@@ -29,6 +29,12 @@
29	29	#undef __OPENMP_AMDGCN__
30	30	#endif // __AMDGCN__
31	31
	32	#ifdef __SPIRV__
	33	#define __OPENMP_SPIRV__
	34	#include <__clang_cuda_complex_builtins.h>
	35	#undef __OPENMP_SPIRV__
	36	#endif // __SPIRV__
	37
32	38	#endif
33	39
34	40	// Grab the host header too.
...	...	@@ -45,7 +51,7 @@
45	51	#ifndef _LIBCPP_STD_VER
46	52
47	53	#pragma omp begin declare variant match( \
48		device = {arch(amdgcn, nvptx, nvptx64)}, \
	54	device = {arch(amdgcn, nvptx, nvptx64, spirv64)}, \
49	55	implementation = {extension(match_any, allow_templates)})
50	56
51	57	#include <complex_cmath.h>

lib/include/openmp_wrappers/complex.h+6

...	...	@@ -29,6 +29,12 @@
29	29	#undef __OPENMP_AMDGCN__
30	30	#endif
31	31
	32	#ifdef __SPIRV__
	33	#define __OPENMP_SPIRV__
	34	#include <__clang_cuda_complex_builtins.h>
	35	#undef __OPENMP_SPIRV__
	36	#endif // __SPIRV__
	37
32	38	#endif
33	39
34	40	// Grab the host header too.

lib/include/openmp_wrappers/math.h+10

...	...	@@ -58,4 +58,14 @@
58	58	#pragma omp end declare variant
59	59	#endif
60	60
	61	#ifdef __SPIRV__
	62	#pragma omp begin declare variant match(device = {arch(spirv64)})
	63
	64	#define __OPENMP_SPIRV__
	65	#include <__clang_spirv_math.h>
	66	#undef __OPENMP_SPIRV__
	67
	68	#pragma omp end declare variant
	69	#endif
	70
61	71	#endif

lib/include/ptrauth.h+90-12

...	...	@@ -38,8 +38,7 @@ typedef enum {
38	38	The extra data is always 0. */
39	39	ptrauth_key_function_pointer = ptrauth_key_process_independent_code,
40	40
41		/* The key used to sign C++ v-table pointers.
42		The extra data is always 0. */
	41	/* The key used to sign pointers to C++ v-tables. */
43	42	ptrauth_key_cxx_vtable_pointer = ptrauth_key_process_independent_data,
44	43
45	44	/* The key used to sign metadata pointers to Objective-C method-lists. */
...	...	@@ -178,6 +177,56 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t;
178	177	__builtin_ptrauth_auth_and_resign(__value, __old_key, __old_data, __new_key, \
179	178	__new_data)
180	179
	180	/* Authenticate a pointer using a PC-based signature scheme and resign
	181	it using a different scheme.
	182
	183	If the result is subsequently authenticated using the new scheme, that
	184	authentication is guaranteed to fail if and only if the initial
	185	authentication failed.
	186
	187	The value must be an expression of pointer type.
	188	The key must be a constant expression of type ptrauth_key.
	189	The extra data must be an expression of pointer or integer type;
	190	if an integer, it will be coerced to ptrauth_extra_data_t.
	191	The oldpc must be an expression of pointer or integer type representing
	192	the PC value where the original signature was created.
	193	The result will have the same type as the original value.
	194
	195	This operation is guaranteed to not leave the intermediate value
	196	available for attack before it is re-signed.
	197
	198	Do not pass a null pointer to this function. A null pointer
	199	will not successfully authenticate. */
	200	#define ptrauth_auth_with_pc_and_resign(__value, __old_key, __old_data, \
	201	__old_pc, __new_key, __new_data) \
	202	__builtin_ptrauth_auth_with_pc_and_resign(__value, __old_key, __old_data, \
	203	__old_pc, __new_key, __new_data)
	204
	205	/* Authenticate a pointer using one scheme, load 32bit value at offset addend
	206	from the pointer, and add this value to the pointer, sign using specified
	207	scheme.
	208
	209	If the result is subsequently authenticated using the new scheme, that
	210	authentication is guaranteed to fail if and only if the initial
	211	authentication failed.
	212
	213	The value must be an expression of pointer type.
	214	The key must be a constant expression of type ptrauth_key.
	215	The extra data must be an expression of pointer or integer type;
	216	if an integer, it will be coerced to ptrauth_extra_data_t.
	217	The addend must be an immediate ptrdiff_t value.
	218	The result will have the same type as the original value.
	219
	220	This operation is guaranteed to not leave the intermediate value
	221	available for attack before it is re-signed.
	222
	223	Do not pass a null pointer to this function. A null pointer
	224	will not successfully authenticate. */
	225	#define ptrauth_auth_load_relative_and_sign(__value, __old_key, __old_data, \
	226	__new_key, __new_data, __offset) \
	227	__builtin_ptrauth_auth_load_relative_and_sign( \
	228	__value, __old_key, __old_data, __new_key, __new_data, __offset)
	229
181	230	/* Authenticate a pointer using one scheme and resign it as a C
182	231	function pointer.
183	232
...	...	@@ -324,30 +373,38 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t;
324	373	__ptrauth(ptrauth_key_objc_class_ro_pointer, 1, \
325	374	__ptrauth_objc_class_ro_discriminator)
326	375
	376	#if __has_feature(ptrauth_init_fini_address_discrimination)
	377	#define __ptrauth_init_fini_pointer \
	378	__ptrauth(ptrauth_key_init_fini_pointer, 1, __ptrauth_init_fini_discriminator)
	379	#else
	380	#define __ptrauth_init_fini_pointer \
	381	__ptrauth(ptrauth_key_init_fini_pointer, 0, __ptrauth_init_fini_discriminator)
	382	#endif
	383
327	384	#else
328	385
329	386	#define ptrauth_strip(__value, __key) \
330		({ \
	387	__extension__({ \
331	388	(void)__key; \
332	389	__value; \
333	390	})
334	391
335	392	#define ptrauth_blend_discriminator(__pointer, __integer) \
336		({ \
	393	__extension__({ \
337	394	(void)__pointer; \
338	395	(void)__integer; \
339	396	((ptrauth_extra_data_t)0); \
340	397	})
341	398
342	399	#define ptrauth_sign_constant(__value, __key, __data) \
343		({ \
	400	__extension__({ \
344	401	(void)__key; \
345	402	(void)__data; \
346	403	__value; \
347	404	})
348	405
349	406	#define ptrauth_sign_unauthenticated(__value, __key, __data) \
350		({ \
	407	__extension__({ \
351	408	(void)__key; \
352	409	(void)__data; \
353	410	__value; \
...	...	@@ -355,7 +412,7 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t;
355	412
356	413	#define ptrauth_auth_and_resign(__value, __old_key, __old_data, __new_key, \
357	414	__new_data) \
358		({ \
	415	__extension__({ \
359	416	(void)__old_key; \
360	417	(void)__old_data; \
361	418	(void)__new_key; \
...	...	@@ -363,22 +420,44 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t;
363	420	__value; \
364	421	})
365	422
	423	#define ptrauth_auth_with_pc_and_resign(__value, __old_key, __old_data, \
	424	__old_pc, __new_key, __new_data) \
	425	__extension__({ \
	426	(void)__old_key; \
	427	(void)__old_data; \
	428	(void)__old_pc; \
	429	(void)__new_key; \
	430	(void)__new_data; \
	431	__value; \
	432	})
	433
	434	#define ptrauth_auth_load_relative_and_sign(__value, __old_key, __old_data, \
	435	__new_key, __new_data, __offset) \
	436	__extension__({ \
	437	(void)__old_key; \
	438	(void)__old_data; \
	439	(void)__new_key; \
	440	(void)__new_data; \
	441	const char __value_tmp = (const char )(__value); \
	442	(void )(__value_tmp + (const int *)(__value_tmp + (__offset))); \
	443	})
	444
366	445	#define ptrauth_auth_function(__value, __old_key, __old_data) \
367		({ \
	446	__extension__({ \
368	447	(void)__old_key; \
369	448	(void)__old_data; \
370	449	__value; \
371	450	})
372	451
373	452	#define ptrauth_auth_data(__value, __old_key, __old_data) \
374		({ \
	453	__extension__({ \
375	454	(void)__old_key; \
376	455	(void)__old_data; \
377	456	__value; \
378	457	})
379	458
380	459	#define ptrauth_string_discriminator(__string) \
381		({ \
	460	__extension__({ \
382	461	(void)__string; \
383	462	((ptrauth_extra_data_t)0); \
384	463	})
...	...	@@ -388,13 +467,12 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t;
388	467	((ptrauth_extra_data_t)0)
389	468
390	469	#define ptrauth_sign_generic_data(__value, __data) \
391		({ \
	470	__extension__({ \
392	471	(void)__value; \
393	472	(void)__data; \
394	473	((ptrauth_generic_signature_t)0); \
395	474	})
396	475
397
398	476	#define ptrauth_cxx_vtable_pointer(key, address_discrimination, \
399	477	extra_discrimination...)
400	478

lib/include/riscv_bitmanip.h+7

...	...	@@ -16,6 +16,13 @@
16	16	extern "C" {
17	17	#endif
18	18
	19	#define __riscv_intrinsic_b 1
	20	#define __riscv_intrinsic_zbb 1
	21	#define __riscv_intrinsic_zbc 1
	22	#define __riscv_intrinsic_zbkb 1
	23	#define __riscv_intrinsic_zbkc 1
	24	#define __riscv_intrinsic_zbkx 1
	25
19	26	#if defined(__riscv_zbb)
20	27	static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
21	28	__riscv_orc_b_32(uint32_t __x) {

lib/include/riscv_corev_alu.h+2

...	...	@@ -16,6 +16,8 @@
16	16	extern "C" {
17	17	#endif
18	18
	19	#define __riscv_intrinsic_xcvalu 1
	20
19	21	#if defined(__riscv_xcvalu)
20	22
21	23	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))

lib/include/riscv_crypto.h+8

...	...	@@ -16,6 +16,14 @@
16	16	extern "C" {
17	17	#endif
18	18
	19	#define __riscv_intrinsic_zkn 1
	20	#define __riscv_intrinsic_zknd 1
	21	#define __riscv_intrinsic_zkne 1
	22	#define __riscv_intrinsic_zknh 1
	23	#define __riscv_intrinsic_zks 1
	24	#define __riscv_intrinsic_zksed 1
	25	#define __riscv_intrinsic_zksh 1
	26
19	27	#if defined(__riscv_zknd)
20	28	#if __riscv_xlen == 32
21	29	#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi(x, y, bs)

lib/include/riscv_mips.h+2

...	...	@@ -14,6 +14,8 @@
14	14	#error "This header is only meant to be used on riscv architecture"
15	15	#endif
16	16
	17	#define __riscv_intrinsic_xmipsexectl 1
	18
17	19	#define __DEFAULT_FN_ATTRS \
18	20	__attribute__((__always_inline__, __nodebug__, __target__("xmipsexectl")))
19	21

lib/include/riscv_nds.h+3

...	...	@@ -16,6 +16,9 @@
16	16	extern "C" {
17	17	#endif
18	18
	19	#define __riscv_intrinsic_xandesbfhcvt 1
	20	#define __riscv_intrinsic_xandesperf 1
	21
19	22	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
20	23
21	24	#if defined(__riscv_xandesperf)

lib/include/riscv_ntlh.h+2

...	...	@@ -10,6 +10,8 @@
10	10	#ifndef __RISCV_NTLH_H
11	11	#define __RISCV_NTLH_H
12	12
	13	#define __riscv_intrinsic_zihintntl 1
	14
13	15	#ifndef __riscv_zihintntl
14	16	#error "NTLH intrinsics require the NTLH extension."
15	17	#endif

lib/include/riscv_packed_simd.h created+644

...	...	@@ -0,0 +1,644 @@
	1	/*===---- riscv_packed_simd.h - RISC-V P intrinsics ------------------------===
	2	*
	3	* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
	4	* See https://llvm.org/LICENSE.txt for license information.
	5	* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
	6	*
	7	*===-----------------------------------------------------------------------===
	8	*/
	9
	10	#ifndef __RISCV_PACKED_SIMD_H
	11	#define __RISCV_PACKED_SIMD_H
	12
	13	#include <stdint.h>
	14
	15	#if defined(__cplusplus)
	16	extern "C" {
	17	#endif
	18
	19	/* Packed SIMD Types */
	20
	21	typedef int8_t int8x4_t __attribute__((__vector_size__(4)));
	22	typedef uint8_t uint8x4_t __attribute__((__vector_size__(4)));
	23	typedef int16_t int16x2_t __attribute__((__vector_size__(4)));
	24	typedef uint16_t uint16x2_t __attribute__((__vector_size__(4)));
	25
	26	typedef int8_t int8x8_t __attribute__((__vector_size__(8)));
	27	typedef uint8_t uint8x8_t __attribute__((__vector_size__(8)));
	28	typedef int16_t int16x4_t __attribute__((__vector_size__(8)));
	29	typedef uint16_t uint16x4_t __attribute__((__vector_size__(8)));
	30	typedef int32_t int32x2_t __attribute__((__vector_size__(8)));
	31	typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
	32
	33	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
	34
	35	#define __packed_splat2(ty, x) ((ty){(x), (x)})
	36	#define __packed_splat4(ty, x) ((ty){(x), (x), (x), (x)})
	37	#define __packed_splat8(ty, x) ((ty){(x), (x), (x), (x), (x), (x), (x), (x)})
	38
	39	#define __packed_splat(name, ty, scalar_ty, splat) \
	40	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(scalar_ty __x) { \
	41	return splat(ty, __x); \
	42	}
	43
	44	#define __packed_shift(name, ty, op, mask) \
	45	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	46	unsigned __rs2) { \
	47	return __rs1 op(__rs2 & (mask)); \
	48	}
	49	#define __packed_shift8(name, ty, op) __packed_shift(name, ty, op, 0x7)
	50	#define __packed_shift16(name, ty, op) __packed_shift(name, ty, op, 0xf)
	51	#define __packed_shift32(name, ty, op) __packed_shift(name, ty, op, 0x1f)
	52
	53	#define __packed_scalar_binary_op(name, ty, scalar_ty, op, splat) \
	54	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	55	scalar_ty __rs2) { \
	56	return __rs1 op splat(ty, __rs2); \
	57	}
	58
	59	#define __packed_binary_op(name, ty, op) \
	60	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
	61	return __rs1 op __rs2; \
	62	}
	63
	64	#define __packed_unary_op(name, ty, op) \
	65	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	66	return op __rs1; \
	67	}
	68
	69	#define __packed_binary_builtin(name, ty, builtin) \
	70	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
	71	return builtin(__rs1, __rs2); \
	72	}
	73
	74	#define __packed_sh1add(name, ty) \
	75	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
	76	return (__rs1 << 1) + __rs2; \
	77	}
	78
	79	/* TODO: switch to sadd_sat(__builtin_elementwise_shl_sat(a, 1), b) once a
	80	* generic elementwise shl_sat builtin exists. sadd_sat(a, a) is equivalent
	81	* for signed types and the backend's saturating_shl1 PatFrags matches both
	82	* shapes. */
	83	#define __packed_sh1sadd(name, ty) \
	84	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
	85	return __builtin_elementwise_add_sat( \
	86	__builtin_elementwise_add_sat(__rs1, __rs1), __rs2); \
	87	}
	88
	89	#define __packed_cmp(name, ty, rty, op) \
	90	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	91	ty __rs2) { \
	92	return (rty)(__rs1 op __rs2); \
	93	}
	94
	95	#define __packed_pabs(name, ty, rty) \
	96	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	97	return (rty)__builtin_elementwise_abs(__rs1); \
	98	}
	99
	100	#define __packed_binary_builtin_cast(name, ty, rty, builtin) \
	101	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	102	ty __rs2) { \
	103	return (rty)builtin(__rs1, __rs2); \
	104	}
	105
	106	#define __packed_reduction(name, rty, ty, builtin) \
	107	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	108	rty __rs2) { \
	109	return builtin(__rs1, __rs2); \
	110	}
	111
	112	#define __packed_merge_builtin(name, ty, mask_ty, builtin) \
	113	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2, \
	114	mask_ty __rd) { \
	115	return (ty)builtin(__rs1, __rs2, __rd); \
	116	}
	117
	118	#define __packed_psabs(name, ty, builtin) \
	119	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	120	return builtin(__rs1); \
	121	}
	122
	123	#define __packed_widen_convert(name, rty, ty) \
	124	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	125	return __builtin_convertvector(__rs1, rty); \
	126	}
	127	#define __packed_widen_high2(name, rty, ty) \
	128	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	129	return (rty)__builtin_shufflevector((ty){0}, __rs1, 0, 2, 1, 3); \
	130	}
	131	#define __packed_widen_high4(name, rty, ty) \
	132	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	133	return (rty)__builtin_shufflevector((ty){0}, __rs1, 0, 4, 1, 5, 2, 6, 3, \
	134	7); \
	135	}
	136
	137	/* Packed Reverse: reverse the order of the elements. Lowered to a single
	138	* rev8/rev16/ppairoe.* by the backend's packed reverse-shuffle handling. */
	139	#define __packed_reverse2(name, ty) \
	140	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	141	return __builtin_shufflevector(__rs1, __rs1, 1, 0); \
	142	}
	143	#define __packed_reverse4(name, ty) \
	144	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	145	return __builtin_shufflevector(__rs1, __rs1, 3, 2, 1, 0); \
	146	}
	147	#define __packed_reverse8(name, ty) \
	148	static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	149	return __builtin_shufflevector(__rs1, __rs1, 7, 6, 5, 4, 3, 2, 1, 0); \
	150	}
	151
	152	#define __packed_zip2(name, rty, ty) \
	153	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	154	ty __rs2) { \
	155	return __builtin_shufflevector(__rs1, __rs2, 0, 2, 1, 3); \
	156	}
	157	#define __packed_zip4(name, rty, ty) \
	158	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	159	ty __rs2) { \
	160	return __builtin_shufflevector(__rs1, __rs2, 0, 4, 1, 5, 2, 6, 3, 7); \
	161	}
	162	#define __packed_unzipe2(name, rty, ty) \
	163	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	164	return __builtin_shufflevector(__rs1, __rs1, 0, 2); \
	165	}
	166	#define __packed_unzipe4(name, rty, ty) \
	167	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	168	return __builtin_shufflevector(__rs1, __rs1, 0, 2, 4, 6); \
	169	}
	170	#define __packed_unzipo2(name, rty, ty) \
	171	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	172	return __builtin_shufflevector(__rs1, __rs1, 1, 3); \
	173	}
	174	#define __packed_unzipo4(name, rty, ty) \
	175	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1) { \
	176	return __builtin_shufflevector(__rs1, __rs1, 1, 3, 5, 7); \
	177	}
	178
	179	#define __packed_abdsum(name, rty, ty, builtin) \
	180	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
	181	ty __rs2) { \
	182	return builtin(__rs1, __rs2); \
	183	}
	184
	185	#define __packed_abdsum_acc(name, rty, ty, builtin) \
	186	static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(rty __rd, ty __rs1, \
	187	ty __rs2) { \
	188	return builtin(__rd, __rs1, __rs2); \
	189	}
	190
	191	// clang-format off: macro call sites have no trailing semicolons, which
	192	// confuses clang-format into a deeply nested expression.
	193
	194	/* Packed Splat (32-bit) */
	195	__packed_splat(pmv_s_u8x4, uint8x4_t, uint8_t, __packed_splat4)
	196	__packed_splat(pmv_s_i8x4, int8x4_t, int8_t, __packed_splat4)
	197	__packed_splat(pmv_s_u16x2, uint16x2_t, uint16_t, __packed_splat2)
	198	__packed_splat(pmv_s_i16x2, int16x2_t, int16_t, __packed_splat2)
	199
	200	/* Packed Splat (64-bit) */
	201	__packed_splat(pmv_s_u8x8, uint8x8_t, uint8_t, __packed_splat8)
	202	__packed_splat(pmv_s_i8x8, int8x8_t, int8_t, __packed_splat8)
	203	__packed_splat(pmv_s_u16x4, uint16x4_t, uint16_t, __packed_splat4)
	204	__packed_splat(pmv_s_i16x4, int16x4_t, int16_t, __packed_splat4)
	205	__packed_splat(pmv_s_u32x2, uint32x2_t, uint32_t, __packed_splat2)
	206	__packed_splat(pmv_s_i32x2, int32x2_t, int32_t, __packed_splat2)
	207
	208	/* Packed Addition and Subtraction (32-bit) */
	209	__packed_binary_op(padd_i8x4, int8x4_t, +)
	210	__packed_binary_op(padd_u8x4, uint8x4_t, +)
	211	__packed_binary_op(padd_i16x2, int16x2_t, +)
	212	__packed_binary_op(padd_u16x2, uint16x2_t, +)
	213	__packed_binary_op(psub_i8x4, int8x4_t, -)
	214	__packed_binary_op(psub_u8x4, uint8x4_t, -)
	215	__packed_binary_op(psub_i16x2, int16x2_t, -)
	216	__packed_binary_op(psub_u16x2, uint16x2_t, -)
	217	__packed_unary_op(pneg_i8x4, int8x4_t, -)
	218	__packed_unary_op(pneg_i16x2, int16x2_t, -)
	219
	220	/* Packed Addition and Subtraction (64-bit) */
	221	__packed_binary_op(padd_i8x8, int8x8_t, +)
	222	__packed_binary_op(padd_u8x8, uint8x8_t, +)
	223	__packed_binary_op(padd_i16x4, int16x4_t, +)
	224	__packed_binary_op(padd_u16x4, uint16x4_t, +)
	225	__packed_binary_op(padd_i32x2, int32x2_t, +)
	226	__packed_binary_op(padd_u32x2, uint32x2_t, +)
	227	__packed_binary_op(psub_i8x8, int8x8_t, -)
	228	__packed_binary_op(psub_u8x8, uint8x8_t, -)
	229	__packed_binary_op(psub_i16x4, int16x4_t, -)
	230	__packed_binary_op(psub_u16x4, uint16x4_t, -)
	231	__packed_binary_op(psub_i32x2, int32x2_t, -)
	232	__packed_binary_op(psub_u32x2, uint32x2_t, -)
	233	__packed_unary_op(pneg_i8x8, int8x8_t, -)
	234	__packed_unary_op(pneg_i16x4, int16x4_t, -)
	235	__packed_unary_op(pneg_i32x2, int32x2_t, -)
	236
	237	/* Packed Addition with Scalar (32-bit) */
	238	__packed_scalar_binary_op(padd_s_u8x4, uint8x4_t, uint8_t, +, __packed_splat4)
	239	__packed_scalar_binary_op(padd_s_i8x4, int8x4_t, int8_t, +, __packed_splat4)
	240	__packed_scalar_binary_op(padd_s_u16x2, uint16x2_t, uint16_t, +,
	241	__packed_splat2)
	242	__packed_scalar_binary_op(padd_s_i16x2, int16x2_t, int16_t, +,
	243	__packed_splat2)
	244
	245	/* Packed Addition with Scalar (64-bit) */
	246	__packed_scalar_binary_op(padd_s_u8x8, uint8x8_t, uint8_t, +, __packed_splat8)
	247	__packed_scalar_binary_op(padd_s_i8x8, int8x8_t, int8_t, +, __packed_splat8)
	248	__packed_scalar_binary_op(padd_s_u16x4, uint16x4_t, uint16_t, +,
	249	__packed_splat4)
	250	__packed_scalar_binary_op(padd_s_i16x4, int16x4_t, int16_t, +,
	251	__packed_splat4)
	252	__packed_scalar_binary_op(padd_s_u32x2, uint32x2_t, uint32_t, +,
	253	__packed_splat2)
	254	__packed_scalar_binary_op(padd_s_i32x2, int32x2_t, int32_t, +,
	255	__packed_splat2)
	256
	257	/* Packed Saturating Addition and Subtraction (32-bit) */
	258	__packed_binary_builtin(psadd_i8x4, int8x4_t, __builtin_elementwise_add_sat)
	259	__packed_binary_builtin(psadd_i16x2, int16x2_t, __builtin_elementwise_add_sat)
	260	__packed_binary_builtin(psaddu_u8x4, uint8x4_t, __builtin_elementwise_add_sat)
	261	__packed_binary_builtin(psaddu_u16x2, uint16x2_t, __builtin_elementwise_add_sat)
	262	__packed_binary_builtin(pssub_i8x4, int8x4_t, __builtin_elementwise_sub_sat)
	263	__packed_binary_builtin(pssub_i16x2, int16x2_t, __builtin_elementwise_sub_sat)
	264	__packed_binary_builtin(pssubu_u8x4, uint8x4_t, __builtin_elementwise_sub_sat)
	265	__packed_binary_builtin(pssubu_u16x2, uint16x2_t, __builtin_elementwise_sub_sat)
	266
	267	/* Packed Saturating Addition and Subtraction (64-bit) */
	268	__packed_binary_builtin(psadd_i8x8, int8x8_t, __builtin_elementwise_add_sat)
	269	__packed_binary_builtin(psadd_i16x4, int16x4_t, __builtin_elementwise_add_sat)
	270	__packed_binary_builtin(psadd_i32x2, int32x2_t, __builtin_elementwise_add_sat)
	271	__packed_binary_builtin(psaddu_u8x8, uint8x8_t, __builtin_elementwise_add_sat)
	272	__packed_binary_builtin(psaddu_u16x4, uint16x4_t, __builtin_elementwise_add_sat)
	273	__packed_binary_builtin(psaddu_u32x2, uint32x2_t, __builtin_elementwise_add_sat)
	274	__packed_binary_builtin(pssub_i8x8, int8x8_t, __builtin_elementwise_sub_sat)
	275	__packed_binary_builtin(pssub_i16x4, int16x4_t, __builtin_elementwise_sub_sat)
	276	__packed_binary_builtin(pssub_i32x2, int32x2_t, __builtin_elementwise_sub_sat)
	277	__packed_binary_builtin(pssubu_u8x8, uint8x8_t, __builtin_elementwise_sub_sat)
	278	__packed_binary_builtin(pssubu_u16x4, uint16x4_t, __builtin_elementwise_sub_sat)
	279	__packed_binary_builtin(pssubu_u32x2, uint32x2_t, __builtin_elementwise_sub_sat)
	280
	281	/* Packed Shift-Add (32-bit) */
	282	__packed_sh1add(psh1add_i16x2, int16x2_t)
	283	__packed_sh1add(psh1add_u16x2, uint16x2_t)
	284	__packed_sh1sadd(pssh1sadd_i16x2, int16x2_t)
	285
	286	/* Packed Shift-Add (64-bit) */
	287	__packed_sh1add(psh1add_i16x4, int16x4_t)
	288	__packed_sh1add(psh1add_u16x4, uint16x4_t)
	289	__packed_sh1add(psh1add_i32x2, int32x2_t)
	290	__packed_sh1add(psh1add_u32x2, uint32x2_t)
	291	__packed_sh1sadd(pssh1sadd_i16x4, int16x4_t)
	292	__packed_sh1sadd(pssh1sadd_i32x2, int32x2_t)
	293
	294	/* Packed Exchanged Addition and Subtraction (32-bit) */
	295	__packed_binary_builtin(pas_x_i16x2, int16x2_t, __builtin_riscv_pas_x_i16x2)
	296	__packed_binary_builtin(psa_x_i16x2, int16x2_t, __builtin_riscv_psa_x_i16x2)
	297	__packed_binary_builtin(psas_x_i16x2, int16x2_t, __builtin_riscv_psas_x_i16x2)
	298	__packed_binary_builtin(pssa_x_i16x2, int16x2_t, __builtin_riscv_pssa_x_i16x2)
	299	__packed_binary_builtin(paas_x_i16x2, int16x2_t, __builtin_riscv_paas_x_i16x2)
	300	__packed_binary_builtin(pasa_x_i16x2, int16x2_t, __builtin_riscv_pasa_x_i16x2)
	301
	302	/* Packed Exchanged Addition and Subtraction (64-bit) */
	303	__packed_binary_builtin(pas_x_i16x4, int16x4_t, __builtin_riscv_pas_x_i16x4)
	304	__packed_binary_builtin(psa_x_i16x4, int16x4_t, __builtin_riscv_psa_x_i16x4)
	305	__packed_binary_builtin(psas_x_i16x4, int16x4_t, __builtin_riscv_psas_x_i16x4)
	306	__packed_binary_builtin(pssa_x_i16x4, int16x4_t, __builtin_riscv_pssa_x_i16x4)
	307	__packed_binary_builtin(paas_x_i16x4, int16x4_t, __builtin_riscv_paas_x_i16x4)
	308	__packed_binary_builtin(pasa_x_i16x4, int16x4_t, __builtin_riscv_pasa_x_i16x4)
	309	__packed_binary_builtin(pas_x_i32x2, int32x2_t, __builtin_riscv_pas_x_i32x2)
	310	__packed_binary_builtin(psa_x_i32x2, int32x2_t, __builtin_riscv_psa_x_i32x2)
	311	__packed_binary_builtin(psas_x_i32x2, int32x2_t, __builtin_riscv_psas_x_i32x2)
	312	__packed_binary_builtin(pssa_x_i32x2, int32x2_t, __builtin_riscv_pssa_x_i32x2)
	313	__packed_binary_builtin(paas_x_i32x2, int32x2_t, __builtin_riscv_paas_x_i32x2)
	314	__packed_binary_builtin(pasa_x_i32x2, int32x2_t, __builtin_riscv_pasa_x_i32x2)
	315
	316	/* Packed Minimum and Maximum (32-bit) */
	317	__packed_binary_builtin(pmin_i8x4, int8x4_t, __builtin_elementwise_min)
	318	__packed_binary_builtin(pmin_i16x2, int16x2_t, __builtin_elementwise_min)
	319	__packed_binary_builtin(pminu_u8x4, uint8x4_t, __builtin_elementwise_min)
	320	__packed_binary_builtin(pminu_u16x2, uint16x2_t, __builtin_elementwise_min)
	321	__packed_binary_builtin(pmax_i8x4, int8x4_t, __builtin_elementwise_max)
	322	__packed_binary_builtin(pmax_i16x2, int16x2_t, __builtin_elementwise_max)
	323	__packed_binary_builtin(pmaxu_u8x4, uint8x4_t, __builtin_elementwise_max)
	324	__packed_binary_builtin(pmaxu_u16x2, uint16x2_t, __builtin_elementwise_max)
	325
	326	/* Packed Minimum and Maximum (64-bit) */
	327	__packed_binary_builtin(pmin_i8x8, int8x8_t, __builtin_elementwise_min)
	328	__packed_binary_builtin(pmin_i16x4, int16x4_t, __builtin_elementwise_min)
	329	__packed_binary_builtin(pmin_i32x2, int32x2_t, __builtin_elementwise_min)
	330	__packed_binary_builtin(pminu_u8x8, uint8x8_t, __builtin_elementwise_min)
	331	__packed_binary_builtin(pminu_u16x4, uint16x4_t, __builtin_elementwise_min)
	332	__packed_binary_builtin(pminu_u32x2, uint32x2_t, __builtin_elementwise_min)
	333	__packed_binary_builtin(pmax_i8x8, int8x8_t, __builtin_elementwise_max)
	334	__packed_binary_builtin(pmax_i16x4, int16x4_t, __builtin_elementwise_max)
	335	__packed_binary_builtin(pmax_i32x2, int32x2_t, __builtin_elementwise_max)
	336	__packed_binary_builtin(pmaxu_u8x8, uint8x8_t, __builtin_elementwise_max)
	337	__packed_binary_builtin(pmaxu_u16x4, uint16x4_t, __builtin_elementwise_max)
	338	__packed_binary_builtin(pmaxu_u32x2, uint32x2_t, __builtin_elementwise_max)
	339
	340	/* Packed Comparison (32-bit) */
	341	__packed_cmp(pmseq_i8x4_u8x4, int8x4_t, uint8x4_t, ==)
	342	__packed_cmp(pmseq_u8x4_u8x4, uint8x4_t, uint8x4_t, ==)
	343	__packed_cmp(pmsne_i8x4_u8x4, int8x4_t, uint8x4_t, !=)
	344	__packed_cmp(pmsne_u8x4_u8x4, uint8x4_t, uint8x4_t, !=)
	345	__packed_cmp(pmslt_u8x4, int8x4_t, uint8x4_t, <)
	346	__packed_cmp(pmsltu_u8x4, uint8x4_t, uint8x4_t, <)
	347	__packed_cmp(pmsgt_u8x4, int8x4_t, uint8x4_t, >)
	348	__packed_cmp(pmsgtu_u8x4, uint8x4_t, uint8x4_t, >)
	349	__packed_cmp(pmsge_u8x4, int8x4_t, uint8x4_t, >=)
	350	__packed_cmp(pmsgeu_u8x4, uint8x4_t, uint8x4_t, >=)
	351	__packed_cmp(pmsle_u8x4, int8x4_t, uint8x4_t, <=)
	352	__packed_cmp(pmsleu_u8x4, uint8x4_t, uint8x4_t, <=)
	353	__packed_cmp(pmseq_i16x2_u16x2, int16x2_t, uint16x2_t, ==)
	354	__packed_cmp(pmseq_u16x2_u16x2, uint16x2_t, uint16x2_t, ==)
	355	__packed_cmp(pmsne_i16x2_u16x2, int16x2_t, uint16x2_t, !=)
	356	__packed_cmp(pmsne_u16x2_u16x2, uint16x2_t, uint16x2_t, !=)
	357	__packed_cmp(pmslt_u16x2, int16x2_t, uint16x2_t, <)
	358	__packed_cmp(pmsltu_u16x2, uint16x2_t, uint16x2_t, <)
	359	__packed_cmp(pmsgt_u16x2, int16x2_t, uint16x2_t, >)
	360	__packed_cmp(pmsgtu_u16x2, uint16x2_t, uint16x2_t, >)
	361	__packed_cmp(pmsge_u16x2, int16x2_t, uint16x2_t, >=)
	362	__packed_cmp(pmsgeu_u16x2, uint16x2_t, uint16x2_t, >=)
	363	__packed_cmp(pmsle_u16x2, int16x2_t, uint16x2_t, <=)
	364	__packed_cmp(pmsleu_u16x2, uint16x2_t, uint16x2_t, <=)
	365
	366	/* Packed Comparison (64-bit) */
	367	__packed_cmp(pmseq_i8x8_u8x8, int8x8_t, uint8x8_t, ==)
	368	__packed_cmp(pmseq_u8x8_u8x8, uint8x8_t, uint8x8_t, ==)
	369	__packed_cmp(pmsne_i8x8_u8x8, int8x8_t, uint8x8_t, !=)
	370	__packed_cmp(pmsne_u8x8_u8x8, uint8x8_t, uint8x8_t, !=)
	371	__packed_cmp(pmslt_u8x8, int8x8_t, uint8x8_t, <)
	372	__packed_cmp(pmsltu_u8x8, uint8x8_t, uint8x8_t, <)
	373	__packed_cmp(pmsgt_u8x8, int8x8_t, uint8x8_t, >)
	374	__packed_cmp(pmsgtu_u8x8, uint8x8_t, uint8x8_t, >)
	375	__packed_cmp(pmsge_u8x8, int8x8_t, uint8x8_t, >=)
	376	__packed_cmp(pmsgeu_u8x8, uint8x8_t, uint8x8_t, >=)
	377	__packed_cmp(pmsle_u8x8, int8x8_t, uint8x8_t, <=)
	378	__packed_cmp(pmsleu_u8x8, uint8x8_t, uint8x8_t, <=)
	379	__packed_cmp(pmseq_i16x4_u16x4, int16x4_t, uint16x4_t, ==)
	380	__packed_cmp(pmseq_u16x4_u16x4, uint16x4_t, uint16x4_t, ==)
	381	__packed_cmp(pmsne_i16x4_u16x4, int16x4_t, uint16x4_t, !=)
	382	__packed_cmp(pmsne_u16x4_u16x4, uint16x4_t, uint16x4_t, !=)
	383	__packed_cmp(pmslt_u16x4, int16x4_t, uint16x4_t, <)
	384	__packed_cmp(pmsltu_u16x4, uint16x4_t, uint16x4_t, <)
	385	__packed_cmp(pmsgt_u16x4, int16x4_t, uint16x4_t, >)
	386	__packed_cmp(pmsgtu_u16x4, uint16x4_t, uint16x4_t, >)
	387	__packed_cmp(pmsge_u16x4, int16x4_t, uint16x4_t, >=)
	388	__packed_cmp(pmsgeu_u16x4, uint16x4_t, uint16x4_t, >=)
	389	__packed_cmp(pmsle_u16x4, int16x4_t, uint16x4_t, <=)
	390	__packed_cmp(pmsleu_u16x4, uint16x4_t, uint16x4_t, <=)
	391	__packed_cmp(pmseq_i32x2_u32x2, int32x2_t, uint32x2_t, ==)
	392	__packed_cmp(pmseq_u32x2_u32x2, uint32x2_t, uint32x2_t, ==)
	393	__packed_cmp(pmsne_i32x2_u32x2, int32x2_t, uint32x2_t, !=)
	394	__packed_cmp(pmsne_u32x2_u32x2, uint32x2_t, uint32x2_t, !=)
	395	__packed_cmp(pmslt_u32x2, int32x2_t, uint32x2_t, <)
	396	__packed_cmp(pmsltu_u32x2, uint32x2_t, uint32x2_t, <)
	397	__packed_cmp(pmsgt_u32x2, int32x2_t, uint32x2_t, >)
	398	__packed_cmp(pmsgtu_u32x2, uint32x2_t, uint32x2_t, >)
	399	__packed_cmp(pmsge_u32x2, int32x2_t, uint32x2_t, >=)
	400	__packed_cmp(pmsgeu_u32x2, uint32x2_t, uint32x2_t, >=)
	401	__packed_cmp(pmsle_u32x2, int32x2_t, uint32x2_t, <=)
	402	__packed_cmp(pmsleu_u32x2, uint32x2_t, uint32x2_t, <=)
	403
	404	/* Packed Shifts (32-bit) */
	405	__packed_shift8(psll_s_u8x4, uint8x4_t, <<)
	406	__packed_shift8(psll_s_i8x4, int8x4_t, <<)
	407	__packed_shift16(psll_s_u16x2, uint16x2_t, <<)
	408	__packed_shift16(psll_s_i16x2, int16x2_t, <<)
	409	__packed_shift8(psrl_s_u8x4, uint8x4_t, >>)
	410	__packed_shift16(psrl_s_u16x2, uint16x2_t, >>)
	411	__packed_shift8(psra_s_i8x4, int8x4_t, >>)
	412	__packed_shift16(psra_s_i16x2, int16x2_t, >>)
	413
	414	/* Packed Shifts (64-bit) */
	415	__packed_shift8(psll_s_u8x8, uint8x8_t, <<)
	416	__packed_shift8(psll_s_i8x8, int8x8_t, <<)
	417	__packed_shift16(psll_s_u16x4, uint16x4_t, <<)
	418	__packed_shift16(psll_s_i16x4, int16x4_t, <<)
	419	__packed_shift32(psll_s_u32x2, uint32x2_t, <<)
	420	__packed_shift32(psll_s_i32x2, int32x2_t, <<)
	421	__packed_shift8(psrl_s_u8x8, uint8x8_t, >>)
	422	__packed_shift16(psrl_s_u16x4, uint16x4_t, >>)
	423	__packed_shift32(psrl_s_u32x2, uint32x2_t, >>)
	424	__packed_shift8(psra_s_i8x8, int8x8_t, >>)
	425	__packed_shift16(psra_s_i16x4, int16x4_t, >>)
	426	__packed_shift32(psra_s_i32x2, int32x2_t, >>)
	427
	428	/* Packed Logical Operations (32-bit) */
	429	__packed_binary_op(pand_i8x4, int8x4_t, &)
	430	__packed_binary_op(pand_u8x4, uint8x4_t, &)
	431	__packed_binary_op(pand_i16x2, int16x2_t, &)
	432	__packed_binary_op(pand_u16x2, uint16x2_t, &)
	433	__packed_binary_op(por_i8x4, int8x4_t, \|)
	434	__packed_binary_op(por_u8x4, uint8x4_t, \|)
	435	__packed_binary_op(por_i16x2, int16x2_t, \|)
	436	__packed_binary_op(por_u16x2, uint16x2_t, \|)
	437	__packed_binary_op(pxor_i8x4, int8x4_t, ^)
	438	__packed_binary_op(pxor_u8x4, uint8x4_t, ^)
	439	__packed_binary_op(pxor_i16x2, int16x2_t, ^)
	440	__packed_binary_op(pxor_u16x2, uint16x2_t, ^)
	441	__packed_unary_op(pnot_i8x4, int8x4_t, ~)
	442	__packed_unary_op(pnot_u8x4, uint8x4_t, ~)
	443	__packed_unary_op(pnot_i16x2, int16x2_t, ~)
	444	__packed_unary_op(pnot_u16x2, uint16x2_t, ~)
	445
	446	/* Packed Logical Operations (64-bit) */
	447	__packed_binary_op(pand_i8x8, int8x8_t, &)
	448	__packed_binary_op(pand_u8x8, uint8x8_t, &)
	449	__packed_binary_op(pand_i16x4, int16x4_t, &)
	450	__packed_binary_op(pand_u16x4, uint16x4_t, &)
	451	__packed_binary_op(pand_i32x2, int32x2_t, &)
	452	__packed_binary_op(pand_u32x2, uint32x2_t, &)
	453	__packed_binary_op(por_i8x8, int8x8_t, \|)
	454	__packed_binary_op(por_u8x8, uint8x8_t, \|)
	455	__packed_binary_op(por_i16x4, int16x4_t, \|)
	456	__packed_binary_op(por_u16x4, uint16x4_t, \|)
	457	__packed_binary_op(por_i32x2, int32x2_t, \|)
	458	__packed_binary_op(por_u32x2, uint32x2_t, \|)
	459	__packed_binary_op(pxor_i8x8, int8x8_t, ^)
	460	__packed_binary_op(pxor_u8x8, uint8x8_t, ^)
	461	__packed_binary_op(pxor_i16x4, int16x4_t, ^)
	462	__packed_binary_op(pxor_u16x4, uint16x4_t, ^)
	463	__packed_binary_op(pxor_i32x2, int32x2_t, ^)
	464	__packed_binary_op(pxor_u32x2, uint32x2_t, ^)
	465	__packed_unary_op(pnot_i8x8, int8x8_t, ~)
	466	__packed_unary_op(pnot_u8x8, uint8x8_t, ~)
	467	__packed_unary_op(pnot_i16x4, int16x4_t, ~)
	468	__packed_unary_op(pnot_u16x4, uint16x4_t, ~)
	469	__packed_unary_op(pnot_i32x2, int32x2_t, ~)
	470	__packed_unary_op(pnot_u32x2, uint32x2_t, ~)
	471
	472	/* Packed Widening Convert */
	473	__packed_widen_convert(pwcvt_i16x4, int16x4_t, int8x4_t)
	474	__packed_widen_convert(pwcvt_i32x2, int32x2_t, int16x2_t)
	475	__packed_widen_convert(pwcvtu_u16x4, uint16x4_t, uint8x4_t)
	476	__packed_widen_convert(pwcvtu_u32x2, uint32x2_t, uint16x2_t)
	477	__packed_widen_high4(pwcvth_i16x4, int16x4_t, int8x4_t)
	478	__packed_widen_high4(pwcvth_u16x4, uint16x4_t, uint8x4_t)
	479	__packed_widen_high2(pwcvth_i32x2, int32x2_t, int16x2_t)
	480	__packed_widen_high2(pwcvth_u32x2, uint32x2_t, uint16x2_t)
	481
	482	/* Packed Reverse (32-bit) */
	483	__packed_reverse4(prev_i8x4, int8x4_t)
	484	__packed_reverse4(prev_u8x4, uint8x4_t)
	485	__packed_reverse2(prev_i16x2, int16x2_t)
	486	__packed_reverse2(prev_u16x2, uint16x2_t)
	487
	488	/* Packed Reverse (64-bit) */
	489	__packed_reverse8(prev_i8x8, int8x8_t)
	490	__packed_reverse8(prev_u8x8, uint8x8_t)
	491	__packed_reverse4(prev_i16x4, int16x4_t)
	492	__packed_reverse4(prev_u16x4, uint16x4_t)
	493	__packed_reverse2(prev_i32x2, int32x2_t)
	494	__packed_reverse2(prev_u32x2, uint32x2_t)
	495
	496	/* Packed Zip */
	497	__packed_zip4(pzip_i8x8, int8x8_t, int8x4_t)
	498	__packed_zip4(pzip_u8x8, uint8x8_t, uint8x4_t)
	499	__packed_zip2(pzip_i16x4, int16x4_t, int16x2_t)
	500	__packed_zip2(pzip_u16x4, uint16x4_t, uint16x2_t)
	501
	502	/* Packed Unzip */
	503	__packed_unzipe4(punzipe_i8x4, int8x4_t, int8x8_t)
	504	__packed_unzipo4(punzipo_i8x4, int8x4_t, int8x8_t)
	505	__packed_unzipe4(punzipe_u8x4, uint8x4_t, uint8x8_t)
	506	__packed_unzipo4(punzipo_u8x4, uint8x4_t, uint8x8_t)
	507	__packed_unzipe2(punzipe_i16x2, int16x2_t, int16x4_t)
	508	__packed_unzipo2(punzipo_i16x2, int16x2_t, int16x4_t)
	509	__packed_unzipe2(punzipe_u16x2, uint16x2_t, uint16x4_t)
	510	__packed_unzipo2(punzipo_u16x2, uint16x2_t, uint16x4_t)
	511
	512	/* Packed Averaging Addition and Subtraction (32-bit) */
	513	__packed_binary_builtin(paadd_i8x4, int8x4_t, __builtin_riscv_paadd_i8x4)
	514	__packed_binary_builtin(paadd_i16x2, int16x2_t, __builtin_riscv_paadd_i16x2)
	515	__packed_binary_builtin(paaddu_u8x4, uint8x4_t, __builtin_riscv_paaddu_u8x4)
	516	__packed_binary_builtin(paaddu_u16x2, uint16x2_t, __builtin_riscv_paaddu_u16x2)
	517	__packed_binary_builtin(pasub_i8x4, int8x4_t, __builtin_riscv_pasub_i8x4)
	518	__packed_binary_builtin(pasub_i16x2, int16x2_t, __builtin_riscv_pasub_i16x2)
	519	__packed_binary_builtin(pasubu_u8x4, uint8x4_t, __builtin_riscv_pasubu_u8x4)
	520	__packed_binary_builtin(pasubu_u16x2, uint16x2_t, __builtin_riscv_pasubu_u16x2)
	521
	522	/* Packed Averaging Addition and Subtraction (64-bit) */
	523	__packed_binary_builtin(paadd_i8x8, int8x8_t, __builtin_riscv_paadd_i8x8)
	524	__packed_binary_builtin(paadd_i16x4, int16x4_t, __builtin_riscv_paadd_i16x4)
	525	__packed_binary_builtin(paadd_i32x2, int32x2_t, __builtin_riscv_paadd_i32x2)
	526	__packed_binary_builtin(paaddu_u8x8, uint8x8_t, __builtin_riscv_paaddu_u8x8)
	527	__packed_binary_builtin(paaddu_u16x4, uint16x4_t, __builtin_riscv_paaddu_u16x4)
	528	__packed_binary_builtin(paaddu_u32x2, uint32x2_t, __builtin_riscv_paaddu_u32x2)
	529	__packed_binary_builtin(pasub_i8x8, int8x8_t, __builtin_riscv_pasub_i8x8)
	530	__packed_binary_builtin(pasub_i16x4, int16x4_t, __builtin_riscv_pasub_i16x4)
	531	__packed_binary_builtin(pasub_i32x2, int32x2_t, __builtin_riscv_pasub_i32x2)
	532	__packed_binary_builtin(pasubu_u8x8, uint8x8_t, __builtin_riscv_pasubu_u8x8)
	533	__packed_binary_builtin(pasubu_u16x4, uint16x4_t, __builtin_riscv_pasubu_u16x4)
	534	__packed_binary_builtin(pasubu_u32x2, uint32x2_t, __builtin_riscv_pasubu_u32x2)
	535
	536	/* Packed Absolute Value and Absolute Difference (32-bit) */
	537	__packed_pabs(pabs_i8x4, int8x4_t, uint8x4_t)
	538	__packed_pabs(pabs_i16x2, int16x2_t, uint16x2_t)
	539	__packed_binary_builtin_cast(pabd_i8x4, int8x4_t, uint8x4_t, __builtin_riscv_pabd_i8x4)
	540	__packed_binary_builtin_cast(pabd_i16x2, int16x2_t, uint16x2_t, __builtin_riscv_pabd_i16x2)
	541	__packed_binary_builtin_cast(pabdu_u8x4, uint8x4_t, uint8x4_t, __builtin_riscv_pabdu_u8x4)
	542	__packed_binary_builtin_cast(pabdu_u16x2, uint16x2_t, uint16x2_t, __builtin_riscv_pabdu_u16x2)
	543
	544	/* Packed Absolute Value and Absolute Difference (64-bit) */
	545	__packed_pabs(pabs_i8x8, int8x8_t, uint8x8_t)
	546	__packed_pabs(pabs_i16x4, int16x4_t, uint16x4_t)
	547	__packed_binary_builtin_cast(pabd_i8x8, int8x8_t, uint8x8_t, __builtin_riscv_pabd_i8x8)
	548	__packed_binary_builtin_cast(pabd_i16x4, int16x4_t, uint16x4_t, __builtin_riscv_pabd_i16x4)
	549	__packed_binary_builtin_cast(pabdu_u8x8, uint8x8_t, uint8x8_t, __builtin_riscv_pabdu_u8x8)
	550	__packed_binary_builtin_cast(pabdu_u16x4, uint16x4_t, uint16x4_t, __builtin_riscv_pabdu_u16x4)
	551
	552	/* Packed Reduction Sum (32-bit) */
	553	__packed_reduction(predsum_i8x4_i32, int32_t, int8x4_t, __builtin_riscv_predsum_i8x4_i32)
	554	__packed_reduction(predsumu_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_predsumu_u8x4_u32)
	555	__packed_reduction(predsum_i16x2_i32, int32_t, int16x2_t, __builtin_riscv_predsum_i16x2_i32)
	556	__packed_reduction(predsumu_u16x2_u32, uint32_t, uint16x2_t, __builtin_riscv_predsumu_u16x2_u32)
	557
	558	/* Packed Reduction Sum (64-bit) */
	559	__packed_reduction(predsum_i8x8_i32, int32_t, int8x8_t, __builtin_riscv_predsum_i8x8_i32)
	560	__packed_reduction(predsumu_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_predsumu_u8x8_u32)
	561	__packed_reduction(predsum_i16x4_i32, int32_t, int16x4_t, __builtin_riscv_predsum_i16x4_i32)
	562	__packed_reduction(predsumu_u16x4_u32, uint32_t, uint16x4_t, __builtin_riscv_predsumu_u16x4_u32)
	563	__packed_reduction(predsum_i8x8_i64, int64_t, int8x8_t, __builtin_riscv_predsum_i8x8_i64)
	564	__packed_reduction(predsumu_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_predsumu_u8x8_u64)
	565	__packed_reduction(predsum_i16x4_i64, int64_t, int16x4_t, __builtin_riscv_predsum_i16x4_i64)
	566	__packed_reduction(predsumu_u16x4_u64, uint64_t, uint16x4_t, __builtin_riscv_predsumu_u16x4_u64)
	567	__packed_reduction(predsum_i32x2_i64, int64_t, int32x2_t, __builtin_riscv_predsum_i32x2_i64)
	568	__packed_reduction(predsumu_u32x2_u64, uint64_t, uint32x2_t, __builtin_riscv_predsumu_u32x2_u64)
	569
	570	/* Packed Merge (32-bit) */
	571	__packed_merge_builtin(pmerge_u8x4, uint8x4_t, uint8x4_t, __builtin_riscv_pmerge_u8x4)
	572	__packed_merge_builtin(pmerge_i8x4, int8x4_t, uint8x4_t, __builtin_riscv_pmerge_i8x4)
	573	__packed_merge_builtin(pmerge_u16x2, uint16x2_t, uint16x2_t, __builtin_riscv_pmerge_u16x2)
	574	__packed_merge_builtin(pmerge_i16x2, int16x2_t, uint16x2_t, __builtin_riscv_pmerge_i16x2)
	575
	576	/* Packed Merge (64-bit) */
	577	__packed_merge_builtin(pmerge_u8x8, uint8x8_t, uint8x8_t, __builtin_riscv_pmerge_u8x8)
	578	__packed_merge_builtin(pmerge_i8x8, int8x8_t, uint8x8_t, __builtin_riscv_pmerge_i8x8)
	579	__packed_merge_builtin(pmerge_u16x4, uint16x4_t, uint16x4_t, __builtin_riscv_pmerge_u16x4)
	580	__packed_merge_builtin(pmerge_i16x4, int16x4_t, uint16x4_t, __builtin_riscv_pmerge_i16x4)
	581	__packed_merge_builtin(pmerge_u32x2, uint32x2_t, uint32x2_t, __builtin_riscv_pmerge_u32x2)
	582	__packed_merge_builtin(pmerge_i32x2, int32x2_t, uint32x2_t, __builtin_riscv_pmerge_i32x2)
	583
	584	/* Packed Absolute Difference Sum (32-bit) */
	585	__packed_abdsum(pabdsumu_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumu_u8x4_u32)
	586	__packed_abdsum_acc(pabdsumau_u8x4_u32, uint32_t, uint8x4_t, __builtin_riscv_pabdsumau_u8x4_u32)
	587
	588	/* Packed Absolute Difference Sum (64-bit) */
	589	__packed_abdsum(pabdsumu_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_pabdsumu_u8x8_u32)
	590	__packed_abdsum(pabdsumu_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_pabdsumu_u8x8_u64)
	591	__packed_abdsum_acc(pabdsumau_u8x8_u32, uint32_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u32)
	592	__packed_abdsum_acc(pabdsumau_u8x8_u64, uint64_t, uint8x8_t, __builtin_riscv_pabdsumau_u8x8_u64)
	593
	594	/* Packed Saturating Absolute Value (32-bit) */
	595	__packed_psabs(psabs_i8x4, int8x4_t, __builtin_riscv_psabs_i8x4)
	596	__packed_psabs(psabs_i16x2, int16x2_t, __builtin_riscv_psabs_i16x2)
	597
	598	/* Packed Saturating Absolute Value (64-bit) */
	599	__packed_psabs(psabs_i8x8, int8x8_t, __builtin_riscv_psabs_i8x8)
	600	__packed_psabs(psabs_i16x4, int16x4_t, __builtin_riscv_psabs_i16x4)
	601
	602	// clang-format on
	603
	604	#undef __packed_splat2
	605	#undef __packed_splat4
	606	#undef __packed_splat8
	607	#undef __packed_splat
	608	#undef __packed_shift
	609	#undef __packed_shift8
	610	#undef __packed_shift16
	611	#undef __packed_shift32
	612	#undef __packed_scalar_binary_op
	613	#undef __packed_binary_op
	614	#undef __packed_unary_op
	615	#undef __packed_binary_builtin
	616	#undef __packed_sh1add
	617	#undef __packed_sh1sadd
	618	#undef __packed_cmp
	619	#undef __packed_pabs
	620	#undef __packed_binary_builtin_cast
	621	#undef __packed_reduction
	622	#undef __packed_merge_builtin
	623	#undef __packed_psabs
	624	#undef __packed_widen_convert
	625	#undef __packed_widen_high2
	626	#undef __packed_widen_high4
	627	#undef __packed_reverse2
	628	#undef __packed_reverse4
	629	#undef __packed_reverse8
	630	#undef __packed_zip2
	631	#undef __packed_zip4
	632	#undef __packed_unzipe2
	633	#undef __packed_unzipe4
	634	#undef __packed_unzipo2
	635	#undef __packed_unzipo4
	636	#undef __packed_abdsum
	637	#undef __packed_abdsum_acc
	638	#undef __DEFAULT_FN_ATTRS
	639
	640	#if defined(__cplusplus)
	641	}
	642	#endif
	643
	644	#endif /* __RISCV_PACKED_SIMD_H */

lib/include/riscv_vector.h+43

...	...	@@ -20,6 +20,35 @@ extern "C" {
20	20
21	21	#pragma clang riscv intrinsic vector
22	22
	23	#define __riscv_intrinsic_v 1
	24	#define __riscv_intrinsic_zvabd 1
	25	#define __riscv_intrinsic_zvbb 1
	26	#define __riscv_intrinsic_zvbc 1
	27	#define __riscv_intrinsic_zvdot4a8i 1
	28	#define __riscv_intrinsic_zve32f 1
	29	#define __riscv_intrinsic_zve32x 1
	30	#define __riscv_intrinsic_zve64d 1
	31	#define __riscv_intrinsic_zve64f 1
	32	#define __riscv_intrinsic_zve64x 1
	33	#define __riscv_intrinsic_zvfbfa 1
	34	#define __riscv_intrinsic_zvfbfmin 1
	35	#define __riscv_intrinsic_zvfbfwma 1
	36	#define __riscv_intrinsic_zvfh 1
	37	#define __riscv_intrinsic_zvfhmin 1
	38	#define __riscv_intrinsic_zvfofp8min 1
	39	#define __riscv_intrinsic_zvkb 1
	40	#define __riscv_intrinsic_zvkg 1
	41	#define __riscv_intrinsic_zvkn 1
	42	#define __riscv_intrinsic_zvknc 1
	43	#define __riscv_intrinsic_zvkned 1
	44	#define __riscv_intrinsic_zvkng 1
	45	#define __riscv_intrinsic_zvknha 1
	46	#define __riscv_intrinsic_zvknhb 1
	47	#define __riscv_intrinsic_zvks 1
	48	#define __riscv_intrinsic_zvksc 1
	49	#define __riscv_intrinsic_zvksed 1
	50	#define __riscv_intrinsic_zvksg 1
	51	#define __riscv_intrinsic_zvksh 1
23	52
24	53	enum __RISCV_FRM {
25	54	__RISCV_FRM_RNE = 0,
...	...	@@ -415,6 +444,20 @@ typedef __rvv_bfloat16m2x4_t vbfloat16m2x4_t;
415	444	typedef __rvv_bfloat16m4_t vbfloat16m4_t;
416	445	typedef __rvv_bfloat16m4x2_t vbfloat16m4x2_t;
417	446	typedef __rvv_bfloat16m8_t vbfloat16m8_t;
	447	typedef __rvv_float8e4m3mf8_t vfloat8e4m3mf8_t;
	448	typedef __rvv_float8e4m3mf4_t vfloat8e4m3mf4_t;
	449	typedef __rvv_float8e4m3mf2_t vfloat8e4m3mf2_t;
	450	typedef __rvv_float8e4m3m1_t vfloat8e4m3m1_t;
	451	typedef __rvv_float8e4m3m2_t vfloat8e4m3m2_t;
	452	typedef __rvv_float8e4m3m4_t vfloat8e4m3m4_t;
	453	typedef __rvv_float8e4m3m8_t vfloat8e4m3m8_t;
	454	typedef __rvv_float8e5m2mf8_t vfloat8e5m2mf8_t;
	455	typedef __rvv_float8e5m2mf4_t vfloat8e5m2mf4_t;
	456	typedef __rvv_float8e5m2mf2_t vfloat8e5m2mf2_t;
	457	typedef __rvv_float8e5m2m1_t vfloat8e5m2m1_t;
	458	typedef __rvv_float8e5m2m2_t vfloat8e5m2m2_t;
	459	typedef __rvv_float8e5m2m4_t vfloat8e5m2m4_t;
	460	typedef __rvv_float8e5m2m8_t vfloat8e5m2m8_t;
418	461
419	462	#ifdef __cplusplus
420	463	}

lib/include/sifive_vector.h+18

...	...	@@ -13,6 +13,24 @@
13	13
14	14	#pragma clang riscv intrinsic sifive_vector
15	15
	16	#define __riscv_intrinsic_xsfmm32a16f 1
	17	#define __riscv_intrinsic_xsfmm32a32f 1
	18	#define __riscv_intrinsic_xsfmm32a8f 1
	19	#define __riscv_intrinsic_xsfmm32a8i 1
	20	#define __riscv_intrinsic_xsfmm32a 1
	21	#define __riscv_intrinsic_xsfmm64a64f 1
	22	#define __riscv_intrinsic_xsfmmbase 1
	23	#define __riscv_intrinsic_xsfvcp 1
	24	#define __riscv_intrinsic_xsfvfbfexp16e 1
	25	#define __riscv_intrinsic_xsfvfexp16e 1
	26	#define __riscv_intrinsic_xsfvfexp32e 1
	27	#define __riscv_intrinsic_xsfvfexpa 1
	28	#define __riscv_intrinsic_xsfvfexpa64e 1
	29	#define __riscv_intrinsic_xsfvfnrclipxfqf 1
	30	#define __riscv_intrinsic_xsfvfwmaccqqq 1
	31	#define __riscv_intrinsic_xsfvqmaccdod 1
	32	#define __riscv_intrinsic_xsfvqmaccqoq 1
	33
16	34	#define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \
17	35	__riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 6, vl)
18	36	#define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \

lib/include/spirvintrin.h+2-29

...	...	@@ -27,9 +27,6 @@ _Pragma("omp begin declare variant match(device = {arch(spirv64)})");
27	27	#define __gpu_global __attribute__((address_space(1)))
28	28	#define __gpu_generic __attribute__((address_space(4)))
29	29
30		// Attribute to declare a function as a kernel.
31		#define __gpu_kernel __attribute__((device_kernel, visibility("protected")))
32
33	30	// Returns the number of workgroups in the 'x' dimension of the grid.
34	31	_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
35	32	return __builtin_spirv_num_workgroups(0);
...	...	@@ -146,37 +143,13 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t __idx, uint32_t __x,
146	143	return __builtin_spirv_subgroup_shuffle(__x, __lane);
147	144	}
148	145
149		// Returns a bitmask marking all lanes that have the same value of __x.
150		_DEFAULT_FN_ATTRS static __inline__ uint64_t
151		__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
152		return __gpu_match_any_u32_impl(__lane_mask, __x);
153		}
154
155		// Returns a bitmask marking all lanes that have the same value of __x.
156		_DEFAULT_FN_ATTRS static __inline__ uint64_t
157		__gpu_match_any_u64(uint64_t __lane_mask, uint64_t __x) {
158		return __gpu_match_any_u64_impl(__lane_mask, __x);
159		}
160
161		// Returns the current lane mask if every lane contains __x.
162		_DEFAULT_FN_ATTRS static __inline__ uint64_t
163		__gpu_match_all_u32(uint64_t __lane_mask, uint32_t __x) {
164		return __gpu_match_all_u32_impl(__lane_mask, __x);
165		}
166
167		// Returns the current lane mask if every lane contains __x.
168		_DEFAULT_FN_ATTRS static __inline__ uint64_t
169		__gpu_match_all_u64(uint64_t __lane_mask, uint64_t __x) {
170		return __gpu_match_all_u64_impl(__lane_mask, __x);
171		}
172
173	146	// SPIR-V does not expose this, always return false.
174		_DEFAULT_FN_ATTRS static __inline__ bool __gpu_is_ptr_local(void *ptr) {
	147	_DEFAULT_FN_ATTRS static __inline__ bool __gpu_is_ptr_local(const void *ptr) {
175	148	return 0;
176	149	}
177	150
178	151	// SPIR-V does not expose this, always return false.
179		_DEFAULT_FN_ATTRS static __inline__ bool __gpu_is_ptr_private(void *ptr) {
	152	_DEFAULT_FN_ATTRS static __inline__ bool __gpu_is_ptr_private(const void *ptr) {
180	153	return 0;
181	154	}
182	155

lib/include/stdint.h+5-14

...	...	@@ -805,25 +805,16 @@ typedef __UINTMAX_TYPE__ uintmax_t;
805	805	#endif
806	806
807	807	/* C99 7.18.3 Limits of other integer types. */
808		#define SIG_ATOMIC_MIN __INTN_MIN(__SIG_ATOMIC_WIDTH__)
809		#define SIG_ATOMIC_MAX __INTN_MAX(__SIG_ATOMIC_WIDTH__)
810		#ifdef __WINT_UNSIGNED__
811		# define WINT_MIN __UINTN_C(__WINT_WIDTH__, 0)
812		# define WINT_MAX __UINTN_MAX(__WINT_WIDTH__)
813		#else
814		# define WINT_MIN __INTN_MIN(__WINT_WIDTH__)
815		# define WINT_MAX __INTN_MAX(__WINT_WIDTH__)
816		#endif
	808	#define SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__
	809	#define SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__
	810	#define WINT_MIN __WINT_MIN__
	811	#define WINT_MAX __WINT_MAX__
817	812
818	813	#ifndef WCHAR_MAX
819	814	# define WCHAR_MAX __WCHAR_MAX__
820	815	#endif
821	816	#ifndef WCHAR_MIN
822		# if __WCHAR_MAX__ == __INTN_MAX(__WCHAR_WIDTH__)
823		# define WCHAR_MIN __INTN_MIN(__WCHAR_WIDTH__)
824		# else
825		# define WCHAR_MIN __UINTN_C(__WCHAR_WIDTH__, 0)
826		# endif
	817	#define WCHAR_MIN __WCHAR_MIN__
827	818	#endif
828	819
829	820	/* 7.18.4.2 Macros for greatest-width integer constants. */

lib/include/vecintrin.h+1-1

...	...	@@ -207,7 +207,7 @@ vec_insert(unsigned long long __scalar, __vector unsigned long long __vec,
207	207	#if __ARCH__ >= 12
208	208	static inline __ATTRS_o_ai __vector float
209	209	vec_insert(float __scalar, __vector float __vec, int __index) {
210		__vec[__index & 1] = __scalar;
	210	__vec[__index & 3] = __scalar;
211	211	return __vec;
212	212	}
213	213	#endif

lib/include/wasm_simd128.h+17

...	...	@@ -45,6 +45,7 @@ typedef int __i32x2 __attribute__((__vector_size__(8), __aligned__(8)));
45	45	typedef unsigned int __u32x2
46	46	__attribute__((__vector_size__(8), __aligned__(8)));
47	47	typedef float __f32x2 __attribute__((__vector_size__(8), __aligned__(8)));
	48	typedef __fp16 __f16x4 __attribute__((__vector_size__(8), __aligned__(8)));
48	49
49	50	#define __DEFAULT_FN_ATTRS \
50	51	__attribute__((__always_inline__, __nodebug__, __target__("simd128"), \
...	...	@@ -2010,6 +2011,22 @@ static __inline__ v128_t __FP16_FN_ATTRS wasm_f16x8_convert_u16x8(v128_t __a) {
2010	2011	return (v128_t) __builtin_convertvector((__u16x8)__a, __f16x8);
2011	2012	}
2012	2013
	2014	static __inline__ v128_t __FP16_FN_ATTRS
	2015	wasm_f32x4_promote_low_f16x8(v128_t __a) {
	2016	return (v128_t) __builtin_convertvector(
	2017	(__f16x4){((__f16x8)__a)[0], ((__f16x8)__a)[1], ((__f16x8)__a)[2],
	2018	((__f16x8)__a)[3]},
	2019	__f32x4);
	2020	}
	2021
	2022	static __inline__ v128_t __FP16_FN_ATTRS
	2023	wasm_f16x8_demote_f32x4_zero(v128_t __a) {
	2024	return (v128_t) __builtin_convertvector(
	2025	__builtin_shufflevector((__f32x4)__a, (__f32x4){0, 0, 0, 0}, 0, 1, 2, 3,
	2026	4, 5, 6, 7),
	2027	__f16x8);
	2028	}
	2029
2013	2030	static __inline__ v128_t __FP16_FN_ATTRS wasm_f16x8_relaxed_madd(v128_t __a,
2014	2031	v128_t __b,
2015	2032	v128_t __c) {

lib/include/xmmintrin.h+8-7

...	...	@@ -341,7 +341,8 @@ _mm_rsqrt_ps(__m128 __a)
341	341	/// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the
342	342	/// minimum value between both operands. The upper 96 bits are copied from
343	343	/// the upper 96 bits of the first source operand.
344		static __inline__ __m128 __DEFAULT_FN_ATTRS _mm_min_ss(__m128 __a, __m128 __b) {
	344	static __inline__ __m128 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_min_ss(__m128 __a,
	345	__m128 __b) {
345	346	return __builtin_ia32_minss((__v4sf)__a, (__v4sf)__b);
346	347	}
347	348
...	...	@@ -384,7 +385,8 @@ static __inline__ __m128 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_min_ps(__m128 __a,
384	385	/// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the
385	386	/// maximum value between both operands. The upper 96 bits are copied from
386	387	/// the upper 96 bits of the first source operand.
387		static __inline__ __m128 __DEFAULT_FN_ATTRS _mm_max_ss(__m128 __a, __m128 __b) {
	388	static __inline__ __m128 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_max_ss(__m128 __a,
	389	__m128 __b) {
388	390	return __builtin_ia32_maxss((__v4sf)__a, (__v4sf)__b);
389	391	}
390	392
...	...	@@ -2569,11 +2571,10 @@ _mm_avg_pu16(__m64 __a, __m64 __b) {
2569	2571	/// \returns A 64-bit integer vector whose lower 16 bits contain the sums of the
2570	2572	/// sets of absolute differences between both operands. The upper bits are
2571	2573	/// cleared.
2572		static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2
2573		_mm_sad_pu8(__m64 __a, __m64 __b)
2574		{
2575		return __trunc64(__builtin_ia32_psadbw128((__v16qi)__zext128(__a),
2576		(__v16qi)__zext128(__b)));
	2574	static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR
	2575	_mm_sad_pu8(__m64 __a, __m64 __b) {
	2576	return __trunc64(__builtin_ia32_psadbw128((__v16qu)__zext128(__a),
	2577	(__v16qu)__zext128(__b)));
2577	2578	}
2578	2579
2579	2580	#if defined(__cplusplus)