authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-07 09:57:43+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-07 14:28:43+02:00
logf4c38a3686f190ec2b9c58cfeea1636d19e5c896
treeb496371b2b97292ebb330209f430166f5d134a3e
parentea6fa69ef558531300e67fd07abf81c92b86949c
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.openbsd: return aarch64 model even if registers are unavailable

1 files changed, 22 insertions(+), 16 deletions(-)

lib/std/zig/system/openbsd.zig+22-16
...@@ -113,32 +113,38 @@ const aarch64 = struct {...@@ -113,32 +113,38 @@ const aarch64 = struct {
113 }113 }
114114
115 fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {115 fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
116 const model: *const std.Target.Cpu.Model = blk: {116 const maybe_model: ?*const std.Target.Cpu.Model = blk: {
117 var buf: [64:0]u8 = undefined;117 var buf: [64:0]u8 = undefined;
118 const name = hwModelName(&buf) orelse return null;118 const name = hwModelName(&buf) orelse break :blk null;
119119
120 inline for (models) |pair| {120 inline for (models) |pair| {
121 if (std.mem.startsWith(u8, name, pair[0])) break :blk pair[1];121 if (std.mem.startsWith(u8, name, pair[0])) break :blk pair[1];
122 }122 }
123123
124 break :blk .generic(arch);124 break :blk null;
125 };125 };
126126
127 const registers = [11]u64{127 const registers = blk: {
128 sysctlReg(std.c.CPU.AA64PFR0) orelse return null,128 break :blk [11]u64{
129 sysctlReg(std.c.CPU.AA64PFR1) orelse return null,129 sysctlReg(std.c.CPU.AA64PFR0) orelse break :blk null,
130 0, // ID_AA64DFR0_EL1130 sysctlReg(std.c.CPU.AA64PFR1) orelse break :blk null,
131 0, // ID_AA64DFR1_EL1131 0, // ID_AA64DFR0_EL1
132 0, // ID_AA64AFR0_EL1132 0, // ID_AA64DFR1_EL1
133 0, // ID_AA64AFR1_EL1133 0, // ID_AA64AFR0_EL1
134 sysctlReg(std.c.CPU.ID_AA64ISAR0) orelse return null,134 0, // ID_AA64AFR1_EL1
135 sysctlReg(std.c.CPU.ID_AA64ISAR1) orelse return null,135 sysctlReg(std.c.CPU.ID_AA64ISAR0) orelse break :blk null,
136 sysctlReg(std.c.CPU.ID_AA64MMFR0) orelse return null,136 sysctlReg(std.c.CPU.ID_AA64ISAR1) orelse break :blk null,
137 sysctlReg(std.c.CPU.ID_AA64MMFR1) orelse return null,137 sysctlReg(std.c.CPU.ID_AA64MMFR0) orelse break :blk null,
138 sysctlReg(std.c.CPU.ID_AA64MMFR2) orelse return null,138 sysctlReg(std.c.CPU.ID_AA64MMFR1) orelse break :blk null,
139 sysctlReg(std.c.CPU.ID_AA64MMFR2) orelse break :blk null,
140 };
141 } orelse {
142 // Even if the registers are unavailable, we should still return the
143 // model if we managed to detect it.
144 return if (maybe_model) |m| m.toCpu(arch) else null;
139 };145 };
140146
141 return @import("arm.zig").aarch64.detectNativeFeatures(arch, model, registers);147 return @import("arm.zig").aarch64.detectNativeFeatures(arch, maybe_model orelse .generic(arch), registers);
142 }148 }
143};149};
144150