Commit f6f2708d8289e1cd6c24b954c261d478ee73ccfc | zig

author	Jacob Young <jacobly@ziglang.org> 2023-10-28 03:16:33-04:00
committer	Jacob Young <jacobly@ziglang.org> 2023-10-29 07:20:36-04:00
log	f6f2708d8289e1cd6c24b954c261d478ee73ccfc
tree	576863cc60c8626c8b89b01621d0538a4923a9ce
parent	1fecf86ebfa352927e2e3aedfd16b0755482e96e

x86_64: fix compiler rt test failures

30 files changed, 207 insertions(+), 202 deletions(-)

lib
- compiler_rt
- std
  - Thread
    Condition.zig
  - crypto
    phc_encoding.zig
  - dwarf
    expressions.zig
  - fmt.zig
  - hash
    auto_hash.zig
    wyhash.zig
  - io
    bit_reader.zig
    test.zig
  - leb128.zig
  - math
    big
    int_test.zig
    ilogb.zig
    ldexp.zig
src
- arch
  - x86_64
    CodeGen.zig
test
- behavior
- tests.zig

lib/compiler_rt/addf3_test.zig-4

...	...	@@ -35,8 +35,6 @@ fn test__addtf3(a: f128, b: f128, expected_hi: u64, expected_lo: u64) !void {
35	35	}
36	36
37	37	test "addtf3" {
38		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
39
40	38	try test__addtf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0);
41	39
42	40	// NaN + any = NaN
...	...	@@ -106,8 +104,6 @@ fn test__addxf3(a: f80, b: f80, expected: u80) !void {
106	104	}
107	105
108	106	test "addxf3" {
109		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
110
111	107	// NaN + any = NaN
112	108	try test__addxf3(qnan80, 0x1.23456789abcdefp+5, @as(u80, @bitCast(qnan80)));
113	109	try test__addxf3(@as(f80, @bitCast(@as(u80, 0x7fff_8000_8000_3000_0000))), 0x1.23456789abcdefp+5, @as(u80, @bitCast(qnan80)));

lib/compiler_rt/addoti4_test.zig-2

...	...	@@ -23,8 +23,6 @@ fn simple_addoti4(a: i128, b: i128, overflow: *c_int) i128 {
23	23	}
24	24
25	25	test "addoti4" {
26		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
27
28	26	const min: i128 = math.minInt(i128);
29	27	const max: i128 = math.maxInt(i128);
30	28	var i: i128 = 1;

lib/compiler_rt/comparef.zig-2

...	...	@@ -98,8 +98,6 @@ pub inline fn cmp_f80(comptime RT: type, a: f80, b: f80) RT {
98	98	}
99	99
100	100	test "cmp_f80" {
101		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
102
103	101	inline for (.{ LE, GE }) \|RT\| {
104	102	try std.testing.expect(cmp_f80(RT, 1.0, 1.0) == RT.Equal);
105	103	try std.testing.expect(cmp_f80(RT, 0.0, -0.0) == RT.Equal);

lib/compiler_rt/cos.zig-2

...	...	@@ -134,8 +134,6 @@ pub fn cosl(x: c_longdouble) callconv(.C) c_longdouble {
134	134	}
135	135
136	136	test "cos32" {
137		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
138
139	137	const epsilon = 0.00001;
140	138
141	139	try expect(math.approxEqAbs(f32, cosf(0.0), 1.0, epsilon));

lib/compiler_rt/divxf3_test.zig-2

...	...	@@ -39,8 +39,6 @@ fn test__divxf3(a: f80, b: f80) !void {
39	39	}
40	40
41	41	test "divxf3" {
42		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
43
44	42	// NaN / any = NaN
45	43	try expect__divxf3_result(math.nan(f80), 0x1.23456789abcdefp+5, 0x7fffC000000000000000);
46	44	// inf / any(except inf and nan) = inf

lib/compiler_rt/fmodx_test.zig-3

...	...	@@ -23,9 +23,6 @@ fn test_fmodx_infs() !void {
23	23	}
24	24
25	25	test "fmodx" {
26		if (builtin.zig_backend == .stage2_x86_64 and
27		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .lzcnt)) return error.SkipZigTest;
28
29	26	try test_fmodx(6.4, 4.0, 2.4);
30	27	try test_fmodx(6.4, -4.0, 2.4);
31	28	try test_fmodx(-6.4, 4.0, -2.4);

lib/compiler_rt/int_from_float_test.zig+1-36

...	...	@@ -41,8 +41,6 @@ fn test__fixunssfsi(a: f32, expected: u32) !void {
41	41	}
42	42
43	43	test "fixsfsi" {
44		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
45
46	44	try test__fixsfsi(-math.floatMax(f32), math.minInt(i32));
47	45
48	46	try test__fixsfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32));
...	...	@@ -71,6 +69,7 @@ test "fixsfsi" {
71	69	try test__fixsfsi(-1.0, -1);
72	70	try test__fixsfsi(-0.99, 0);
73	71	try test__fixsfsi(-0.5, 0);
	72
74	73	try test__fixsfsi(-math.floatMin(f32), 0);
75	74	try test__fixsfsi(0.0, 0);
76	75	try test__fixsfsi(math.floatMin(f32), 0);
...	...	@@ -106,8 +105,6 @@ test "fixsfsi" {
106	105	}
107	106
108	107	test "fixunssfsi" {
109		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
110
111	108	try test__fixunssfsi(0.0, 0);
112	109
113	110	try test__fixunssfsi(0.5, 0);
...	...	@@ -147,8 +144,6 @@ fn test__fixunssfdi(a: f32, expected: u64) !void {
147	144	}
148	145
149	146	test "fixsfdi" {
150		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
151
152	147	try test__fixsfdi(-math.floatMax(f32), math.minInt(i64));
153	148
154	149	try test__fixsfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64));
...	...	@@ -204,8 +199,6 @@ test "fixsfdi" {
204	199	}
205	200
206	201	test "fixunssfdi" {
207		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
208
209	202	try test__fixunssfdi(0.0, 0);
210	203
211	204	try test__fixunssfdi(0.5, 0);
...	...	@@ -244,8 +237,6 @@ fn test__fixunssfti(a: f32, expected: u128) !void {
244	237	}
245	238
246	239	test "fixsfti" {
247		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
248
249	240	try test__fixsfti(-math.floatMax(f32), math.minInt(i128));
250	241
251	242	try test__fixsfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128));
...	...	@@ -317,8 +308,6 @@ test "fixsfti" {
317	308	}
318	309
319	310	test "fixunssfti" {
320		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
321
322	311	try test__fixunssfti(0.0, 0);
323	312
324	313	try test__fixunssfti(0.5, 0);
...	...	@@ -365,8 +354,6 @@ fn test__fixunsdfsi(a: f64, expected: u32) !void {
365	354	}
366	355
367	356	test "fixdfsi" {
368		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
369
370	357	try test__fixdfsi(-math.floatMax(f64), math.minInt(i32));
371	358
372	359	try test__fixdfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32));
...	...	@@ -428,8 +415,6 @@ test "fixdfsi" {
428	415	}
429	416
430	417	test "fixunsdfsi" {
431		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
432
433	418	try test__fixunsdfsi(0.0, 0);
434	419
435	420	try test__fixunsdfsi(0.5, 0);
...	...	@@ -472,8 +457,6 @@ fn test__fixunsdfdi(a: f64, expected: u64) !void {
472	457	}
473	458
474	459	test "fixdfdi" {
475		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
476
477	460	try test__fixdfdi(-math.floatMax(f64), math.minInt(i64));
478	461
479	462	try test__fixdfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64));
...	...	@@ -527,8 +510,6 @@ test "fixdfdi" {
527	510	}
528	511
529	512	test "fixunsdfdi" {
530		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
531
532	513	try test__fixunsdfdi(0.0, 0);
533	514	try test__fixunsdfdi(0.5, 0);
534	515	try test__fixunsdfdi(0.99, 0);
...	...	@@ -571,8 +552,6 @@ fn test__fixunsdfti(a: f64, expected: u128) !void {
571	552	}
572	553
573	554	test "fixdfti" {
574		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
575
576	555	try test__fixdfti(-math.floatMax(f64), math.minInt(i128));
577	556
578	557	try test__fixdfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128));
...	...	@@ -626,8 +605,6 @@ test "fixdfti" {
626	605	}
627	606
628	607	test "fixunsdfti" {
629		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
630
631	608	try test__fixunsdfti(0.0, 0);
632	609
633	610	try test__fixunsdfti(0.5, 0);
...	...	@@ -677,8 +654,6 @@ fn test__fixunstfsi(a: f128, expected: u32) !void {
677	654	}
678	655
679	656	test "fixtfsi" {
680		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
681
682	657	try test__fixtfsi(-math.floatMax(f128), math.minInt(i32));
683	658
684	659	try test__fixtfsi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i32));
...	...	@@ -742,8 +717,6 @@ test "fixtfsi" {
742	717	}
743	718
744	719	test "fixunstfsi" {
745		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
746
747	720	try test__fixunstfsi(math.inf(f128), 0xffffffff);
748	721	try test__fixunstfsi(0, 0x0);
749	722	try test__fixunstfsi(0x1.23456789abcdefp+5, 0x24);
...	...	@@ -767,8 +740,6 @@ fn test__fixunstfdi(a: f128, expected: u64) !void {
767	740	}
768	741
769	742	test "fixtfdi" {
770		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
771
772	743	try test__fixtfdi(-math.floatMax(f128), math.minInt(i64));
773	744
774	745	try test__fixtfdi(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i64));
...	...	@@ -832,8 +803,6 @@ test "fixtfdi" {
832	803	}
833	804
834	805	test "fixunstfdi" {
835		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
836
837	806	try test__fixunstfdi(0.0, 0);
838	807
839	808	try test__fixunstfdi(0.5, 0);
...	...	@@ -886,8 +855,6 @@ fn test__fixunstfti(a: f128, expected: u128) !void {
886	855	}
887	856
888	857	test "fixtfti" {
889		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
890
891	858	try test__fixtfti(-math.floatMax(f128), math.minInt(i128));
892	859
893	860	try test__fixtfti(-0x1.FFFFFFFFFFFFFp+1023, math.minInt(i128));
...	...	@@ -969,8 +936,6 @@ fn test__fixunshfti(a: f16, expected: u128) !void {
969	936	}
970	937
971	938	test "fixunshfti for f16" {
972		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
973
974	939	try test__fixunshfti(math.inf(f16), math.maxInt(u128));
975	940	try test__fixunshfti(math.floatMax(f16), 65504);
976	941	}

lib/compiler_rt/negti2_test.zig-2

...	...	@@ -7,8 +7,6 @@ fn test__negti2(a: i128, expected: i128) !void {
7	7	}
8	8
9	9	test "negti2" {
10		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
11
12	10	// TODO ensuring that math.minInt(i128); returns error
13	11
14	12	try test__negti2(-3, 3);

lib/compiler_rt/powiXf2_test.zig-7

...	...	@@ -34,9 +34,6 @@ fn test__powixf2(a: f80, b: i32, expected: f80) !void {
34	34	}
35	35
36	36	test "powihf2" {
37		if (builtin.zig_backend == .stage2_x86_64 and
38		!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest;
39
40	37	const inf_f16 = math.inf(f16);
41	38	try test__powisf2(0, 0, 1);
42	39	try test__powihf2(1, 0, 1);
...	...	@@ -356,8 +353,6 @@ test "powidf2" {
356	353	}
357	354
358	355	test "powitf2" {
359		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
360
361	356	const inf_f128 = math.inf(f128);
362	357	try test__powitf2(0, 0, 1);
363	358	try test__powitf2(1, 0, 1);
...	...	@@ -463,8 +458,6 @@ test "powitf2" {
463	458	}
464	459
465	460	test "powixf2" {
466		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
467
468	461	const inf_f80 = math.inf(f80);
469	462	try test__powixf2(0, 0, 1);
470	463	try test__powixf2(1, 0, 1);

lib/compiler_rt/sin.zig-2

...	...	@@ -140,8 +140,6 @@ pub fn sinl(x: c_longdouble) callconv(.C) c_longdouble {
140	140	}
141	141
142	142	test "sin32" {
143		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
144
145	143	const epsilon = 0.00001;
146	144
147	145	try expect(math.approxEqAbs(f32, sinf(0.0), 0.0, epsilon));

lib/compiler_rt/suboti4_test.zig-2

...	...	@@ -27,8 +27,6 @@ pub fn simple_suboti4(a: i128, b: i128, overflow: *c_int) i128 {
27	27	}
28	28
29	29	test "suboti3" {
30		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
31
32	30	const min: i128 = math.minInt(i128);
33	31	const max: i128 = math.maxInt(i128);
34	32	var i: i128 = 1;

lib/compiler_rt/tan.zig-2

...	...	@@ -131,8 +131,6 @@ test "tan" {
131	131	}
132	132
133	133	test "tan32" {
134		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
135
136	134	const epsilon = 0.00001;
137	135
138	136	try expect(math.approxEqAbs(f32, tanf(0.0), 0.0, epsilon));

lib/std/Thread/Condition.zig+2

...	...	@@ -440,6 +440,8 @@ test "Condition - multi signal" {
440	440	return error.SkipZigTest;
441	441	}
442	442
	443	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
	444
443	445	const num_threads = 4;
444	446	const num_iterations = 4;
445	447

lib/std/crypto/phc_encoding.zig-2

...	...	@@ -363,8 +363,6 @@ test "phc format - hash without salt" {
363	363	}
364	364
365	365	test "phc format - calcSize" {
366		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
367
368	366	const s = "$scrypt$v=1$ln=15,r=8,p=1$c2FsdHNhbHQ$dGVzdHBhc3M";
369	367	const v = try deserialize(struct {
370	368	alg_id: []const u8,

lib/std/dwarf/expressions.zig-2

...	...	@@ -1054,8 +1054,6 @@ fn isOpcodeRegisterLocation(opcode: u8) bool {
1054	1054
1055	1055	const testing = std.testing;
1056	1056	test "DWARF expressions" {
1057		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1058
1059	1057	const allocator = std.testing.allocator;
1060	1058
1061	1059	const options = ExpressionOptions{};

lib/std/fmt.zig-2

...	...	@@ -2435,8 +2435,6 @@ test "float.hexadecimal" {
2435	2435	}
2436	2436
2437	2437	test "float.hexadecimal.precision" {
2438		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2439
2440	2438	try expectFmt("f16: 0x1.5p-2", "f16: {x:.1}", .{@as(f16, 1.0 / 3.0)});
2441	2439	try expectFmt("f32: 0x1.555p-2", "f32: {x:.3}", .{@as(f32, 1.0 / 3.0)});
2442	2440	try expectFmt("f64: 0x1.55555p-2", "f64: {x:.5}", .{@as(f64, 1.0 / 3.0)});

lib/std/hash/auto_hash.zig-21

...	...	@@ -1,6 +1,5 @@
1	1	const std = @import("std");
2	2	const assert = std.debug.assert;
3		const builtin = @import("builtin");
4	3	const mem = std.mem;
5	4	const meta = std.meta;
6	5
...	...	@@ -253,8 +252,6 @@ test "typeContainsSlice" {
253	252	}
254	253
255	254	test "hash pointer" {
256		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
257
258	255	const array = [_]u32{ 123, 123, 123 };
259	256	const a = &array[0];
260	257	const b = &array[1];
...	...	@@ -275,8 +272,6 @@ test "hash pointer" {
275	272	}
276	273
277	274	test "hash slice shallow" {
278		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
279
280	275	// Allocate one array dynamically so that we're assured it is not merged
281	276	// with the other by the optimization passes.
282	277	const array1 = try std.testing.allocator.create([6]u32);
...	...	@@ -295,8 +290,6 @@ test "hash slice shallow" {
295	290	}
296	291
297	292	test "hash slice deep" {
298		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
299
300	293	// Allocate one array dynamically so that we're assured it is not merged
301	294	// with the other by the optimization passes.
302	295	const array1 = try std.testing.allocator.create([6]u32);
...	...	@@ -313,8 +306,6 @@ test "hash slice deep" {
313	306	}
314	307
315	308	test "hash struct deep" {
316		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
317
318	309	const Foo = struct {
319	310	a: u32,
320	311	b: u16,
...	...	@@ -354,8 +345,6 @@ test "hash struct deep" {
354	345	}
355	346
356	347	test "testHash optional" {
357		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
358
359	348	const a: ?u32 = 123;
360	349	const b: ?u32 = null;
361	350	try testing.expectEqual(testHash(a), testHash(@as(u32, 123)));
...	...	@@ -364,8 +353,6 @@ test "testHash optional" {
364	353	}
365	354
366	355	test "testHash array" {
367		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
368
369	356	const a = [_]u32{ 1, 2, 3 };
370	357	const h = testHash(a);
371	358	var hasher = Wyhash.init(0);
...	...	@@ -382,8 +369,6 @@ test "testHash multi-dimensional array" {
382	369	}
383	370
384	371	test "testHash struct" {
385		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
386
387	372	const Foo = struct {
388	373	a: u32 = 1,
389	374	b: u32 = 2,
...	...	@@ -399,8 +384,6 @@ test "testHash struct" {
399	384	}
400	385
401	386	test "testHash union" {
402		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
403
404	387	const Foo = union(enum) {
405	388	A: u32,
406	389	B: bool,
...	...	@@ -425,8 +408,6 @@ test "testHash union" {
425	408	}
426	409
427	410	test "testHash vector" {
428		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
429
430	411	const a: @Vector(4, u32) = [_]u32{ 1, 2, 3, 4 };
431	412	const b: @Vector(4, u32) = [_]u32{ 1, 2, 3, 5 };
432	413	try testing.expect(testHash(a) == testHash(a));
...	...	@@ -439,8 +420,6 @@ test "testHash vector" {
439	420	}
440	421
441	422	test "testHash error union" {
442		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
443
444	423	const Errors = error{Test};
445	424	const Foo = struct {
446	425	a: u32 = 1,

lib/std/hash/wyhash.zig-2

...	...	@@ -242,8 +242,6 @@ test "smhasher" {
242	242	}
243	243
244	244	test "iterative api" {
245		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
246
247	245	const Test = struct {
248	246	fn do() !void {
249	247	try verify.iterativeApi(Wyhash);

lib/std/io/bit_reader.zig-2

...	...	@@ -164,8 +164,6 @@ pub fn bitReader(
164	164	}
165	165
166	166	test "api coverage" {
167		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
168
169	167	const mem_be = [_]u8{ 0b11001101, 0b00001011 };
170	168	const mem_le = [_]u8{ 0b00011101, 0b10010101 };
171	169

lib/std/io/test.zig+1-4

...	...	@@ -1,5 +1,4 @@
1	1	const std = @import("std");
2		const builtin = @import("builtin");
3	2	const io = std.io;
4	3	const meta = std.meta;
5	4	const trait = std.trait;
...	...	@@ -10,7 +9,7 @@ const expectError = std.testing.expectError;
10	9	const mem = std.mem;
11	10	const fs = std.fs;
12	11	const File = std.fs.File;
13		const native_endian = builtin.target.cpu.arch.endian();
	12	const native_endian = @import("builtin").target.cpu.arch.endian();
14	13
15	14	const tmpDir = std.testing.tmpDir;
16	15
...	...	@@ -61,8 +60,6 @@ test "write a file, read it, then delete it" {
61	60	}
62	61
63	62	test "BitStreams with File Stream" {
64		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
65
66	63	var tmp = tmpDir(.{});
67	64	defer tmp.cleanup();
68	65

lib/std/leb128.zig-5

...	...	@@ -1,4 +1,3 @@
1		const builtin = @import("builtin");
2	1	const std = @import("std");
3	2	const testing = std.testing;
4	3
...	...	@@ -215,8 +214,6 @@ fn test_read_uleb128_seq(comptime T: type, comptime N: usize, encoded: []const u
215	214	}
216	215
217	216	test "deserialize signed LEB128" {
218		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
219
220	217	// Truncated
221	218	try testing.expectError(error.EndOfStream, test_read_stream_ileb128(i64, "\x80"));
222	219
...	...	@@ -363,8 +360,6 @@ test "serialize unsigned LEB128" {
363	360	}
364	361
365	362	test "serialize signed LEB128" {
366		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
367
368	363	// explicitly test i0 because starting `t` at 0
369	364	// will break the while loop
370	365	try test_write_leb128(@as(i0, 0));

lib/std/math/big/int_test.zig-4

...	...	@@ -990,8 +990,6 @@ test "big.int mul 0*0" {
990	990	}
991	991
992	992	test "big.int mul large" {
993		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
994
995	993	var a = try Managed.initCapacity(testing.allocator, 50);
996	994	defer a.deinit();
997	995	var b = try Managed.initCapacity(testing.allocator, 100);
...	...	@@ -1075,8 +1073,6 @@ test "big.int mulWrap multi-multi signed" {
1075	1073	}
1076	1074
1077	1075	test "big.int mulWrap large" {
1078		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
1079
1080	1076	var a = try Managed.initCapacity(testing.allocator, 50);
1081	1077	defer a.deinit();
1082	1078	var b = try Managed.initCapacity(testing.allocator, 100);

lib/std/math/ilogb.zig-2

...	...	@@ -108,8 +108,6 @@ test "64" {
108	108	}
109	109
110	110	test "80" {
111		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
112
113	111	try expect(ilogbX(f80, 0.0) == fp_ilogb0);
114	112	try expect(ilogbX(f80, 0.5) == -1);
115	113	try expect(ilogbX(f80, 0.8923) == -1);

lib/std/math/ldexp.zig-2

...	...	@@ -67,8 +67,6 @@ pub fn ldexp(x: anytype, n: i32) @TypeOf(x) {
67	67	}
68	68
69	69	test "math.ldexp" {
70		if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
71
72	70	// subnormals
73	71	try expect(ldexp(@as(f16, 0x1.1FFp14), -14 - 9 - 15) == math.floatTrueMin(f16));
74	72	try expect(ldexp(@as(f32, 0x1.3FFFFFp-1), -126 - 22) == math.floatTrueMin(f32));

src/arch/x86_64/CodeGen.zig+203-76

...	...	@@ -3495,59 +3495,140 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
3495	3495	const mod = self.bin_file.options.module.?;
3496	3496	const bin_op = self.air.instructions.items(.data)[inst].bin_op;
3497	3497	const ty = self.typeOf(bin_op.lhs);
3498		if (ty.zigTypeTag(mod) == .Vector or ty.abiSize(mod) > 8) return self.fail(
3499		"TODO implement airMulSat for {}",
3500		.{ty.fmt(mod)},
3501		);
3502	3498
3503		try self.spillRegisters(&.{ .rax, .rdx });
3504		const reg_locks = self.register_manager.lockRegs(2, .{ .rax, .rdx });
3505		defer for (reg_locks) \|reg_lock\| if (reg_lock) \|lock\| self.register_manager.unlockReg(lock);
	3499	const result = result: {
	3500	if (ty.toIntern() == .i128_type) {
	3501	const ptr_c_int = try mod.singleMutPtrType(Type.c_int);
	3502	const overflow = try self.allocTempRegOrMem(Type.c_int, false);
	3503
	3504	const dst_mcv = try self.genCall(.{ .lib = .{
	3505	.return_type = .i128_type,
	3506	.param_types = &.{ .i128_type, .i128_type, ptr_c_int.toIntern() },
	3507	.callee = "__muloti4",
	3508	} }, &.{ Type.i128, Type.i128, ptr_c_int }, &.{
	3509	.{ .air_ref = bin_op.lhs },
	3510	.{ .air_ref = bin_op.rhs },
	3511	overflow.address(),
	3512	});
	3513	const dst_locks = self.register_manager.lockRegsAssumeUnused(2, dst_mcv.register_pair);
	3514	defer for (dst_locks) \|lock\| self.register_manager.unlockReg(lock);
3506	3515
3507		const lhs_mcv = try self.resolveInst(bin_op.lhs);
3508		const lhs_lock = switch (lhs_mcv) {
3509		.register => \|reg\| self.register_manager.lockRegAssumeUnused(reg),
3510		else => null,
3511		};
3512		defer if (lhs_lock) \|lock\| self.register_manager.unlockReg(lock);
	3516	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
	3517	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
	3518	defer self.register_manager.unlockReg(tmp_lock);
3513	3519
3514		const rhs_mcv = try self.resolveInst(bin_op.rhs);
3515		const rhs_lock = switch (rhs_mcv) {
3516		.register => \|reg\| self.register_manager.lockReg(reg),
3517		else => null,
3518		};
3519		defer if (rhs_lock) \|lock\| self.register_manager.unlockReg(lock);
	3520	const lhs_mcv = try self.resolveInst(bin_op.lhs);
	3521	const mat_lhs_mcv = switch (lhs_mcv) {
	3522	.load_symbol => mat_lhs_mcv: {
	3523	// TODO clean this up!
	3524	const addr_reg = try self.copyToTmpRegister(Type.usize, lhs_mcv.address());
	3525	break :mat_lhs_mcv MCValue{ .indirect = .{ .reg = addr_reg } };
	3526	},
	3527	else => lhs_mcv,
	3528	};
	3529	const mat_lhs_lock = switch (mat_lhs_mcv) {
	3530	.indirect => \|reg_off\| self.register_manager.lockReg(reg_off.reg),
	3531	else => null,
	3532	};
	3533	defer if (mat_lhs_lock) \|lock\| self.register_manager.unlockReg(lock);
	3534	if (mat_lhs_mcv.isMemory()) try self.asmRegisterMemory(
	3535	.{ ._, .mov },
	3536	tmp_reg,
	3537	mat_lhs_mcv.address().offset(8).deref().mem(.qword),
	3538	) else try self.asmRegisterRegister(
	3539	.{ ._, .mov },
	3540	tmp_reg,
	3541	mat_lhs_mcv.register_pair[1],
	3542	);
3520	3543
3521		const limit_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
3522		const limit_mcv = MCValue{ .register = limit_reg };
3523		const limit_lock = self.register_manager.lockRegAssumeUnused(limit_reg);
3524		defer self.register_manager.unlockReg(limit_lock);
	3544	const rhs_mcv = try self.resolveInst(bin_op.rhs);
	3545	const mat_rhs_mcv = switch (rhs_mcv) {
	3546	.load_symbol => mat_rhs_mcv: {
	3547	// TODO clean this up!
	3548	const addr_reg = try self.copyToTmpRegister(Type.usize, rhs_mcv.address());
	3549	break :mat_rhs_mcv MCValue{ .indirect = .{ .reg = addr_reg } };
	3550	},
	3551	else => rhs_mcv,
	3552	};
	3553	const mat_rhs_lock = switch (mat_rhs_mcv) {
	3554	.indirect => \|reg_off\| self.register_manager.lockReg(reg_off.reg),
	3555	else => null,
	3556	};
	3557	defer if (mat_rhs_lock) \|lock\| self.register_manager.unlockReg(lock);
	3558	if (mat_rhs_mcv.isMemory()) try self.asmRegisterMemory(
	3559	.{ ._, .xor },
	3560	tmp_reg,
	3561	mat_rhs_mcv.address().offset(8).deref().mem(.qword),
	3562	) else try self.asmRegisterRegister(
	3563	.{ ._, .xor },
	3564	tmp_reg,
	3565	mat_rhs_mcv.register_pair[1],
	3566	);
3525	3567
3526		const reg_bits = self.regBitSize(ty);
3527		const cc: Condition = if (ty.isSignedInt(mod)) cc: {
3528		try self.genSetReg(limit_reg, ty, lhs_mcv);
3529		try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, rhs_mcv);
3530		try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
3531		try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{
3532		.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,
3533		});
3534		break :cc .o;
3535		} else cc: {
3536		try self.genSetReg(limit_reg, ty, .{
3537		.immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - reg_bits),
3538		});
3539		break :cc .c;
3540		};
	3568	try self.asmRegisterImmediate(.{ ._r, .sa }, tmp_reg, Immediate.u(63));
	3569	try self.asmRegister(.{ ._, .not }, tmp_reg);
	3570	try self.asmMemoryImmediate(.{ ._, .cmp }, overflow.mem(.dword), Immediate.s(0));
	3571	try self.freeValue(overflow);
	3572	try self.asmCmovccRegisterRegister(.ne, dst_mcv.register_pair[0], tmp_reg);
	3573	try self.asmRegisterImmediate(.{ ._c, .bt }, tmp_reg, Immediate.u(63));
	3574	try self.asmCmovccRegisterRegister(.ne, dst_mcv.register_pair[1], tmp_reg);
	3575	break :result dst_mcv;
	3576	}
3541	3577
3542		const dst_mcv = try self.genMulDivBinOp(.mul, inst, ty, ty, lhs_mcv, rhs_mcv);
3543		const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2);
3544		try self.asmCmovccRegisterRegister(
3545		cc,
3546		registerAlias(dst_mcv.register, cmov_abi_size),
3547		registerAlias(limit_reg, cmov_abi_size),
3548		);
	3578	if (ty.zigTypeTag(mod) == .Vector or ty.abiSize(mod) > 8) return self.fail(
	3579	"TODO implement airMulSat for {}",
	3580	.{ty.fmt(mod)},
	3581	);
3549	3582
3550		return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
	3583	try self.spillRegisters(&.{ .rax, .rdx });
	3584	const reg_locks = self.register_manager.lockRegs(2, .{ .rax, .rdx });
	3585	defer for (reg_locks) \|reg_lock\| if (reg_lock) \|lock\| self.register_manager.unlockReg(lock);
	3586
	3587	const lhs_mcv = try self.resolveInst(bin_op.lhs);
	3588	const lhs_lock = switch (lhs_mcv) {
	3589	.register => \|reg\| self.register_manager.lockRegAssumeUnused(reg),
	3590	else => null,
	3591	};
	3592	defer if (lhs_lock) \|lock\| self.register_manager.unlockReg(lock);
	3593
	3594	const rhs_mcv = try self.resolveInst(bin_op.rhs);
	3595	const rhs_lock = switch (rhs_mcv) {
	3596	.register => \|reg\| self.register_manager.lockReg(reg),
	3597	else => null,
	3598	};
	3599	defer if (rhs_lock) \|lock\| self.register_manager.unlockReg(lock);
	3600
	3601	const limit_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
	3602	const limit_mcv = MCValue{ .register = limit_reg };
	3603	const limit_lock = self.register_manager.lockRegAssumeUnused(limit_reg);
	3604	defer self.register_manager.unlockReg(limit_lock);
	3605
	3606	const reg_bits = self.regBitSize(ty);
	3607	const cc: Condition = if (ty.isSignedInt(mod)) cc: {
	3608	try self.genSetReg(limit_reg, ty, lhs_mcv);
	3609	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, rhs_mcv);
	3610	try self.genShiftBinOpMir(.{ ._r, .sa }, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
	3611	try self.genBinOpMir(.{ ._, .xor }, ty, limit_mcv, .{
	3612	.immediate = (@as(u64, 1) << @intCast(reg_bits - 1)) - 1,
	3613	});
	3614	break :cc .o;
	3615	} else cc: {
	3616	try self.genSetReg(limit_reg, ty, .{
	3617	.immediate = @as(u64, math.maxInt(u64)) >> @intCast(64 - reg_bits),
	3618	});
	3619	break :cc .c;
	3620	};
	3621
	3622	const dst_mcv = try self.genMulDivBinOp(.mul, inst, ty, ty, lhs_mcv, rhs_mcv);
	3623	const cmov_abi_size = @max(@as(u32, @intCast(ty.abiSize(mod))), 2);
	3624	try self.asmCmovccRegisterRegister(
	3625	cc,
	3626	registerAlias(dst_mcv.register, cmov_abi_size),
	3627	registerAlias(limit_reg, cmov_abi_size),
	3628	);
	3629	break :result dst_mcv;
	3630	};
	3631	return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
3551	3632	}
3552	3633
3553	3634	fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
...	...	@@ -3701,10 +3782,13 @@ fn genSetFrameTruncatedOverflowCompare(
3701	3782	const ty = tuple_ty.structFieldType(0, mod);
3702	3783	const int_info = ty.intInfo(mod);
3703	3784
3704		const hi_limb_bits = (int_info.bits - 1) % 64 + 1;
3705		const hi_limb_ty = try mod.intType(int_info.signedness, hi_limb_bits);
	3785	const hi_bits = (int_info.bits - 1) % 64 + 1;
	3786	const hi_ty = try mod.intType(int_info.signedness, hi_bits);
3706	3787
3707		const rest_ty = try mod.intType(.unsigned, int_info.bits - hi_limb_bits);
	3788	const limb_bits: u16 = @intCast(if (int_info.bits <= 64) self.regBitSize(ty) else 64);
	3789	const limb_ty = try mod.intType(int_info.signedness, limb_bits);
	3790
	3791	const rest_ty = try mod.intType(.unsigned, int_info.bits - hi_bits);
3708	3792
3709	3793	const temp_regs =
3710	3794	try self.register_manager.allocRegs(3, .{ null, null, null }, abi.RegisterClass.gp);
...	...	@@ -3720,9 +3804,9 @@ fn genSetFrameTruncatedOverflowCompare(
3720	3804	src_mcv.address().offset(int_info.bits / 64 * 8).deref()
3721	3805	else
3722	3806	src_mcv;
3723		try self.genSetReg(scratch_reg, hi_limb_ty, hi_limb_mcv);
3724		try self.truncateRegister(hi_limb_ty, scratch_reg);
3725		try self.genBinOpMir(.{ ._, .cmp }, hi_limb_ty, .{ .register = scratch_reg }, hi_limb_mcv);
	3807	try self.genSetReg(scratch_reg, limb_ty, hi_limb_mcv);
	3808	try self.truncateRegister(hi_ty, scratch_reg);
	3809	try self.genBinOpMir(.{ ._, .cmp }, limb_ty, .{ .register = scratch_reg }, hi_limb_mcv);
3726	3810
3727	3811	const eq_reg = temp_regs[2];
3728	3812	if (overflow_cc) \|_\| {
...	...	@@ -3740,7 +3824,7 @@ fn genSetFrameTruncatedOverflowCompare(
3740	3824	try self.genSetMem(
3741	3825	.{ .frame = frame_index },
3742	3826	payload_off + hi_limb_off,
3743		hi_limb_ty,
	3827	limb_ty,
3744	3828	.{ .register = scratch_reg },
3745	3829	);
3746	3830	try self.genSetMem(
...	...	@@ -4084,6 +4168,7 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
4084	4168	}
4085	4169
4086	4170	fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {
	4171	const mod = self.bin_file.options.module.?;
4087	4172	const bin_op = self.air.instructions.items(.data)[inst].bin_op;
4088	4173
4089	4174	try self.spillRegisters(&.{.rcx});
...	...	@@ -4095,9 +4180,38 @@ fn airShlShrBinOp(self: *Self, inst: Air.Inst.Index) !void {
4095	4180	const lhs_ty = self.typeOf(bin_op.lhs);
4096	4181	const rhs_ty = self.typeOf(bin_op.rhs);
4097	4182
4098		const result = try self.genShiftBinOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
	4183	const dst_mcv = try self.genShiftBinOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
	4184	switch (tag) {
	4185	.shr, .shr_exact, .shl_exact => {},
	4186	.shl => switch (dst_mcv) {
	4187	.register => \|dst_reg\| try self.truncateRegister(lhs_ty, dst_reg),
	4188	.register_pair => \|dst_regs\| try self.truncateRegister(lhs_ty, dst_regs[1]),
	4189	.load_frame => \|frame_addr\| {
	4190	const tmp_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
	4191	const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
	4192	defer self.register_manager.unlockReg(tmp_lock);
4099	4193
4100		return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
	4194	const lhs_bits: u31 = @intCast(lhs_ty.bitSize(mod));
	4195	const tmp_ty = if (lhs_bits > 64) Type.usize else lhs_ty;
	4196	const off = frame_addr.off + lhs_bits / 64 * 8;
	4197	try self.genSetReg(
	4198	tmp_reg,
	4199	tmp_ty,
	4200	.{ .load_frame = .{ .index = frame_addr.index, .off = off } },
	4201	);
	4202	try self.truncateRegister(lhs_ty, tmp_reg);
	4203	try self.genSetMem(
	4204	.{ .frame = frame_addr.index },
	4205	off,
	4206	tmp_ty,
	4207	.{ .register = tmp_reg },
	4208	);
	4209	},
	4210	else => {},
	4211	},
	4212	else => unreachable,
	4213	}
	4214	return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
4101	4215	}
4102	4216
4103	4217	fn airShlSat(self: *Self, inst: Air.Inst.Index) !void {
...	...	@@ -4529,18 +4643,24 @@ fn airSlicePtr(self: *Self, inst: Air.Inst.Index) !void {
4529	4643	fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void {
4530	4644	const ty_op = self.air.instructions.items(.data)[inst].ty_op;
4531	4645
4532		const operand = try self.resolveInst(ty_op.operand);
4533		const dst_mcv: MCValue = blk: {
4534		switch (operand) {
4535		.load_frame => \|frame_addr\| break :blk .{ .load_frame = .{
4536		.index = frame_addr.index,
4537		.off = frame_addr.off + 8,
4538		} },
4539		else => return self.fail("TODO implement slice_len for {}", .{operand}),
	4646	const result: MCValue = result: {
	4647	const src_mcv = try self.resolveInst(ty_op.operand);
	4648	switch (src_mcv) {
	4649	.load_frame => \|frame_addr\| {
	4650	const len_mcv: MCValue = .{ .load_frame = .{
	4651	.index = frame_addr.index,
	4652	.off = frame_addr.off + 8,
	4653	} };
	4654	if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result len_mcv;
	4655
	4656	const dst_mcv = try self.allocRegOrMem(inst, true);
	4657	try self.genCopy(Type.usize, dst_mcv, len_mcv);
	4658	break :result dst_mcv;
	4659	},
	4660	else => return self.fail("TODO implement slice_len for {}", .{src_mcv}),
4540	4661	}
4541	4662	};
4542
4543		return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
	4663	return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
4544	4664	}
4545	4665
4546	4666	fn airPtrSliceLenPtr(self: *Self, inst: Air.Inst.Index) !void {
...	...	@@ -4933,13 +5053,19 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
4933	5053	const has_lzcnt = self.hasFeature(.lzcnt);
4934	5054	if (src_bits > 64 and !has_lzcnt) {
4935	5055	var callee_buf: ["__clz?i2".len]u8 = undefined;
4936		break :result try self.genCall(.{ .lib = .{
	5056	const result = try self.genCall(.{ .lib = .{
4937	5057	.return_type = .i32_type,
4938	5058	.param_types = &.{src_ty.toIntern()},
4939	5059	.callee = std.fmt.bufPrint(&callee_buf, "__clz{c}i2", .{
4940	5060	intCompilerRtAbiName(src_bits),
4941	5061	}) catch unreachable,
4942	5062	} }, &.{src_ty}, &.{.{ .air_ref = ty_op.operand }});
	5063	if (src_bits < 128) try self.asmRegisterImmediate(
	5064	.{ ._, .sub },
	5065	result.register,
	5066	Immediate.u(128 - src_bits),
	5067	);
	5068	break :result result;
4943	5069	}
4944	5070
4945	5071	const src_mcv = try self.resolveInst(ty_op.operand);
...	...	@@ -5590,7 +5716,7 @@ fn floatSign(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, ty: Type)
5590	5716	defer if (src_lock) \|lock\| self.register_manager.unlockReg(lock);
5591	5717
5592	5718	const dst_mcv: MCValue = .{ .register = .st0 };
5593		if (std.meta.eql(src_mcv, dst_mcv) and self.reuseOperand(inst, operand, 0, src_mcv))
	5719	if (!std.meta.eql(src_mcv, dst_mcv) or !self.reuseOperand(inst, operand, 0, src_mcv))
5594	5720	try self.register_manager.getReg(.st0, inst);
5595	5721
5596	5722	try self.genCopy(ty, dst_mcv, src_mcv);
...	...	@@ -7317,6 +7443,7 @@ fn genShiftBinOp(
7317	7443	});
7318	7444
7319	7445	assert(rhs_ty.abiSize(mod) == 1);
	7446	try self.spillEflagsIfOccupied();
7320	7447
7321	7448	const lhs_abi_size = lhs_ty.abiSize(mod);
7322	7449	if (lhs_abi_size > 16) return self.fail("TODO implement genShiftBinOp for {}", .{
...	...	@@ -7821,7 +7948,7 @@ fn genBinOp(
7821	7948	}) .{ .lhs = rhs_air, .rhs = lhs_air } else .{ .lhs = lhs_air, .rhs = rhs_air };
7822	7949
7823	7950	const lhs_mcv = try self.resolveInst(ordered_air.lhs);
7824		const rhs_mcv = try self.resolveInst(ordered_air.rhs);
	7951	var rhs_mcv = try self.resolveInst(ordered_air.rhs);
7825	7952	switch (lhs_mcv) {
7826	7953	.immediate => \|imm\| switch (imm) {
7827	7954	0 => switch (air_tag) {
...	...	@@ -7893,6 +8020,7 @@ fn genBinOp(
7893	8020	copied_to_dst = false
7894	8021	else
7895	8022	try self.genCopy(lhs_ty, dst_mcv, lhs_mcv);
	8023	rhs_mcv = try self.resolveInst(ordered_air.rhs);
7896	8024	break :dst dst_mcv;
7897	8025	};
7898	8026	const dst_locks: [2]?RegisterLock = switch (dst_mcv) {
...	...	@@ -9224,6 +9352,7 @@ fn genBinOpMir(
9224	9352	) !void {
9225	9353	const mod = self.bin_file.options.module.?;
9226	9354	const abi_size: u32 = @intCast(ty.abiSize(mod));
	9355	try self.spillEflagsIfOccupied();
9227	9356	switch (dst_mcv) {
9228	9357	.none,
9229	9358	.unreach,
...	...	@@ -11154,11 +11283,11 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {
11154	11283	const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
11155	11284	const loop = self.air.extraData(Air.Block, ty_pl.payload);
11156	11285	const body = self.air.extra[loop.end..][0..loop.data.body_len];
11157		const jmp_target: Mir.Inst.Index = @intCast(self.mir_instructions.len);
11158	11286
11159	11287	self.scope_generation += 1;
11160	11288	const state = try self.saveState();
11161	11289
	11290	const jmp_target: Mir.Inst.Index = @intCast(self.mir_instructions.len);
11162	11291	try self.genBody(body);
11163	11292	try self.restoreState(state, &.{}, .{
11164	11293	.emit_instructions = true,
...	...	@@ -11336,14 +11465,14 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void {
11336	11465	.close_scope = false,
11337	11466	});
11338	11467
11339		// Stop tracking block result without forgetting tracking info
11340		try self.freeValue(block_tracking.short);
11341
11342	11468	// Emit a jump with a relocation. It will be patched up after the block ends.
11343	11469	// Leave the jump offset undefined
11344	11470	const jmp_reloc = try self.asmJmpReloc(undefined);
11345	11471	try block_data.relocs.append(self.gpa, jmp_reloc);
11346	11472
	11473	// Stop tracking block result without forgetting tracking info
	11474	try self.freeValue(block_tracking.short);
	11475
11347	11476	self.finishAirBookkeeping();
11348	11477	}
11349	11478
...	...	@@ -12660,7 +12789,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
12660	12789	registerAlias(dst_reg, abi_size),
12661	12790	.{
12662	12791	.base = .{ .reg = addr_reg },
12663		.mod = .{ .rm = .{ .size = Memory.Size.fromSize(abi_size) } },
	12792	.mod = .{ .rm = .{ .size = self.memSize(ty) } },
12664	12793	},
12665	12794	);
12666	12795	},
...	...	@@ -15350,11 +15479,10 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
15350	15479	.signedness = .unsigned,
15351	15480	.bits = @intCast(ty.bitSize(mod)),
15352	15481	};
15353		const max_reg_bit_width = Register.rax.bitSize();
	15482	const shift = math.cast(u6, 64 - int_info.bits % 64) orelse return;
15354	15483	try self.spillEflagsIfOccupied();
15355	15484	switch (int_info.signedness) {
15356	15485	.signed => {
15357		const shift: u6 = @intCast(max_reg_bit_width - int_info.bits);
15358	15486	try self.genShiftBinOpMir(
15359	15487	.{ ._l, .sa },
15360	15488	Type.isize,
...	...	@@ -15369,7 +15497,6 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
15369	15497	);
15370	15498	},
15371	15499	.unsigned => {
15372		const shift: u6 = @intCast(max_reg_bit_width - int_info.bits);
15373	15500	const mask = ~@as(u64, 0) >> shift;
15374	15501	if (int_info.bits <= 32) {
15375	15502	try self.genBinOpMir(

test/behavior/export_builtin.zig-3

...	...	@@ -4,7 +4,6 @@ const expect = std.testing.expect;
4	4
5	5	test "exporting enum type and value" {
6	6	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
7		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
8	7	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
9	8	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
10	9	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
...	...	@@ -21,7 +20,6 @@ test "exporting enum type and value" {
21	20
22	21	test "exporting with internal linkage" {
23	22	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
24		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
25	23	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
26	24	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
27	25	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
...	...	@@ -37,7 +35,6 @@ test "exporting with internal linkage" {
37	35
38	36	test "exporting using field access" {
39	37	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
40		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
41	38	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
42	39	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
43	40	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;

test/behavior/fn.zig-1

...	...	@@ -577,7 +577,6 @@ test "pass and return comptime-only types" {
577	577
578	578	test "pointer to alias behaves same as pointer to function" {
579	579	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
580		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
581	580	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
582	581	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
583	582	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;

test/behavior/globals.zig-2

...	...	@@ -6,7 +6,6 @@ var pos = [2]f32{ 0.0, 0.0 };
6	6	test "store to global array" {
7	7	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
8	8	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
9		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
10	9	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
11	10	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
12	11	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
...	...	@@ -20,7 +19,6 @@ var vpos = @Vector(2, f32){ 0.0, 0.0 };
20	19	test "store to global vector" {
21	20	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
22	21	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
23		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
24	22	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
25	23	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
26	24	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;

test/behavior/nan.zig-1

...	...	@@ -23,7 +23,6 @@ const snan_f128: f128 = math.snan(f128);
23	23
24	24	test "nan memory equality" {
25	25	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
26		if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
27	26	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
28	27	if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
29	28	if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;

test/tests.zig-5

...	...	@@ -1241,11 +1241,6 @@ pub fn addCAbiTests(b: std.Build, skip_non_native: bool, skip_release: bool) S
1241	1241	continue;
1242	1242	}
1243	1243
1244		if (c_abi_target.use_llvm == false and optimize_mode == .ReleaseFast) {
1245		// panic: unrecognized command line argument
1246		continue;
1247		}
1248
1249	1244	const test_step = b.addTest(.{
1250	1245	.name = b.fmt("test-c-abi-{s}-{s}-{s}{s}{s}{s}", .{
1251	1246	c_abi_target.target.zigTriple(b.allocator) catch @panic("OOM"),