Commit f8163f7eaf45fa2b53a1f5ceac35088ad7d73e45 | zig

author	Joachim Schmidt <joachim.schmidt557@outlook.com> 2021-12-31 12:21:59+01:00
committer	Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-01-01 11:16:34+01:00
log	f8163f7eaf45fa2b53a1f5ceac35088ad7d73e45
tree	b6ad28892098ec62135103f177e82ea9582c55de
parent	b100e2ec2a06268623b119baf584e059440cb8f0
signature	Commit is signed but in an unrecognized format.

stage2 ARM: implement airCall for function pointers

2 files changed, 85 insertions(+), 28 deletions(-)

src
- arch
  - arm
    CodeGen.zig
test
- stage2
  - arm.zig

src/arch/arm/CodeGen.zig+37-28

 @@ -2238,10 +2238,16 @@ fn airFence(self: *Self) !void {
 fn airCall(self: *Self, inst: Air.Inst.Index) !void {
     const pl_op = self.air.instructions.items(.data)[inst].pl_op;
-    const fn_ty = self.air.typeOf(pl_op.operand);
     const callee = pl_op.operand;
     const extra = self.air.extraData(Air.Call, pl_op.payload);
     const args = @bitCast([]const Air.Inst.Ref, self.air.extra[extra.end..][0..extra.data.args_len]);
+    const ty = self.air.typeOf(callee);
+    const fn_ty = switch (ty.zigTypeTag()) {
+        .Fn => ty,
+        .Pointer => ty.childType(),
+        else => unreachable,
+    };
     var info = try self.resolveCallingConventionValues(fn_ty);
     defer info.deinit(self);
 @@ -2310,39 +2316,42 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
                     unreachable;
                 try self.genSetReg(Type.initTag(.usize), .lr, .{ .memory = got_addr });
-                // TODO: add Instruction.supportedOn
-                // function for ARM
-                if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
-                    _ = try self.addInst(.{
-                        .tag = .blx,
-                        .cond = .al,
-                        .data = .{ .reg = .lr },
-                    });
-                } else {
-                    return self.fail("TODO fix blx emulatio for ARM <v5", .{});
-                    // _ = try self.addInst(.{
-                    //     .tag = .mov,
-                    //     .cond = .al,
-                    //     .data = .{ .rr_op = .{
-                    //         .rd = .lr,
-                    //         .rn = .r0,
-                    //         .op = Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none),
-                    //     } },
-                    // });
-                    // _ = try self.addInst(.{
-                    //     .tag = .bx,
-                    //     .cond = .al,
-                    //     .data = .{ .reg = .lr },
-                    // });
-                }
             } else if (func_value.castTag(.extern_fn)) |_| {
                 return self.fail("TODO implement calling extern functions", .{});
             } else {
                 return self.fail("TODO implement calling bitcasted functions", .{});
             }
         } else {
-            return self.fail("TODO implement calling runtime known function pointer", .{});
+            assert(ty.zigTypeTag() == .Pointer);
+            const mcv = try self.resolveInst(callee);
+            try self.genSetReg(Type.initTag(.usize), .lr, mcv);
+        }
+        // TODO: add Instruction.supportedOn
+        // function for ARM
+        if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
+            _ = try self.addInst(.{
+                .tag = .blx,
+                .cond = .al,
+                .data = .{ .reg = .lr },
+            });
+        } else {
+            return self.fail("TODO fix blx emulation for ARM <v5", .{});
+            // _ = try self.addInst(.{
+            //     .tag = .mov,
+            //     .cond = .al,
+            //     .data = .{ .rr_op = .{
+            //         .rd = .lr,
+            //         .rn = .r0,
+            //         .op = Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none),
+            //     } },
+            // });
+            // _ = try self.addInst(.{
+            //     .tag = .bx,
+            //     .cond = .al,
+            //     .data = .{ .reg = .lr },
+            // });
         }
     } else if (self.bin_file.cast(link.File.MachO)) |_| {
         unreachable; // unsupported architecture for MachO

test/stage2/arm.zig+48

...	@@ -704,4 +704,52 @@ pub fn addCases(ctx: *TestContext) !void {	...	@@ -704,4 +704,52 @@ pub fn addCases(ctx: *TestContext) !void {
704	"",	704	"",
705	);	705	);
706	}	706	}
		707
		708	{
		709	var case = ctx.exe("function pointers", linux_arm);
		710	case.addCompareOutput(
		711	\\const PrintFn = fn () void;
		712	\\
		713	\\pub fn main() void {
		714	\\ var printFn: PrintFn = stopSayingThat;
		715	\\ var i: u32 = 0;
		716	\\ while (i < 4) : (i += 1) printFn();
		717	\\
		718	\\ printFn = moveEveryZig;
		719	\\ printFn();
		720	\\}
		721	\\
		722	\\fn stopSayingThat() void {
		723	\\ asm volatile ("svc #0"
		724	\\ :
		725	\\ : [number] "{r7}" (4),
		726	\\ [arg1] "{r0}" (1),
		727	\\ [arg2] "{r1}" (@ptrToInt("Hello, my name is Inigo Montoya; you killed my father, prepare to die.\n")),
		728	\\ [arg3] "{r2}" ("Hello, my name is Inigo Montoya; you killed my father, prepare to die.\n".len),
		729	\\ : "memory"
		730	\\ );
		731	\\ return;
		732	\\}
		733	\\
		734	\\fn moveEveryZig() void {
		735	\\ asm volatile ("svc #0"
		736	\\ :
		737	\\ : [number] "{r7}" (4),
		738	\\ [arg1] "{r0}" (1),
		739	\\ [arg2] "{r1}" (@ptrToInt("All your codebase are belong to us\n")),
		740	\\ [arg3] "{r2}" ("All your codebase are belong to us\n".len),
		741	\\ : "memory"
		742	\\ );
		743	\\ return;
		744	\\}
		745	,
		746	\\Hello, my name is Inigo Montoya; you killed my father, prepare to die.
		747	\\Hello, my name is Inigo Montoya; you killed my father, prepare to die.
		748	\\Hello, my name is Inigo Montoya; you killed my father, prepare to die.
		749	\\Hello, my name is Inigo Montoya; you killed my father, prepare to die.
		750	\\All your codebase are belong to us
		751	\\
		752	,
		753	);
		754	}
707	}	755	}