authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2019-10-09 13:22:16-04:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2019-10-09 13:22:16-04:00
logf929a58d5f69c26c25ced89f31f60d0a92ffc46a
tree498df11397ec8025c5cd8625954f0a14fcf1e1f5
parent0fc97015e2898bb2ae9de04dd087d5d3220faf71
parent6a687bda76a34775bde35ee386e59f53961341f7
signaturebadge-question-mark Signed by PGP key 4AEE18F83AFDEB23

Merge pull request #3389 from LemonBoy/win32

Win32

7 files changed, 176 insertions(+), 103 deletions(-)

lib/std/special/compiler_rt.zig+9
......@@ -248,8 +248,17 @@ comptime {
248248
249249 switch (builtin.arch) {
250250 .i386 => {
251 @export("_alldiv", @import("compiler_rt/aulldiv.zig")._alldiv, strong_linkage);
251252 @export("_aulldiv", @import("compiler_rt/aulldiv.zig")._aulldiv, strong_linkage);
253 @export("_allrem", @import("compiler_rt/aullrem.zig")._allrem, strong_linkage);
252254 @export("_aullrem", @import("compiler_rt/aullrem.zig")._aullrem, strong_linkage);
255
256 @export("__divti3", @import("compiler_rt/divti3.zig").__divti3, linkage);
257 @export("__modti3", @import("compiler_rt/modti3.zig").__modti3, linkage);
258 @export("__multi3", @import("compiler_rt/multi3.zig").__multi3, linkage);
259 @export("__udivti3", @import("compiler_rt/udivti3.zig").__udivti3, linkage);
260 @export("__udivmodti4", @import("compiler_rt/udivmodti4.zig").__udivmodti4, linkage);
261 @export("__umodti3", @import("compiler_rt/umodti3.zig").__umodti3, linkage);
253262 },
254263 .x86_64 => {
255264 // The "ti" functions must use @Vector(2, u64) parameter types to adhere to the ABI
lib/std/special/compiler_rt/aulldiv.zig+71-50
......@@ -1,55 +1,76 @@
1const builtin = @import("builtin");
2
3pub extern stdcallcc fn _alldiv(a: i64, b: i64) i64 {
4 @setRuntimeSafety(builtin.is_test);
5 const s_a = a >> (i64.bit_count - 1);
6 const s_b = b >> (i64.bit_count - 1);
7
8 const an = (a ^ s_a) -% s_a;
9 const bn = (b ^ s_b) -% s_b;
10
11 const r = @bitCast(u64, an) / @bitCast(u64, bn);
12 const s = s_a ^ s_b;
13 return (@bitCast(i64, r) ^ s) -% s;
14}
15
116pub nakedcc fn _aulldiv() void {
217 @setRuntimeSafety(false);
18
19 // The stack layout is:
20 // ESP+16 divisor (hi)
21 // ESP+12 divisor (low)
22 // ESP+8 dividend (hi)
23 // ESP+4 dividend (low)
24 // ESP return address
25
326 asm volatile (
4 \\.intel_syntax noprefix
5 \\
6 \\ push ebx
7 \\ push esi
8 \\ mov eax,dword ptr [esp+18h]
9 \\ or eax,eax
10 \\ jne L1
11 \\ mov ecx,dword ptr [esp+14h]
12 \\ mov eax,dword ptr [esp+10h]
13 \\ xor edx,edx
14 \\ div ecx
15 \\ mov ebx,eax
16 \\ mov eax,dword ptr [esp+0Ch]
17 \\ div ecx
18 \\ mov edx,ebx
19 \\ jmp L2
20 \\ L1:
21 \\ mov ecx,eax
22 \\ mov ebx,dword ptr [esp+14h]
23 \\ mov edx,dword ptr [esp+10h]
24 \\ mov eax,dword ptr [esp+0Ch]
25 \\ L3:
26 \\ shr ecx,1
27 \\ rcr ebx,1
28 \\ shr edx,1
29 \\ rcr eax,1
30 \\ or ecx,ecx
31 \\ jne L3
32 \\ div ebx
33 \\ mov esi,eax
34 \\ mul dword ptr [esp+18h]
35 \\ mov ecx,eax
36 \\ mov eax,dword ptr [esp+14h]
37 \\ mul esi
38 \\ add edx,ecx
39 \\ jb L4
40 \\ cmp edx,dword ptr [esp+10h]
41 \\ ja L4
42 \\ jb L5
43 \\ cmp eax,dword ptr [esp+0Ch]
44 \\ jbe L5
45 \\ L4:
46 \\ dec esi
47 \\ L5:
48 \\ xor edx,edx
49 \\ mov eax,esi
50 \\ L2:
51 \\ pop esi
52 \\ pop ebx
53 \\ ret 10h
27 \\ push %%ebx
28 \\ push %%esi
29 \\ mov 0x18(%%esp),%%eax
30 \\ or %%eax,%%eax
31 \\ jne 1f
32 \\ mov 0x14(%%esp),%%ecx
33 \\ mov 0x10(%%esp),%%eax
34 \\ xor %%edx,%%edx
35 \\ div %%ecx
36 \\ mov %%eax,%%ebx
37 \\ mov 0xc(%%esp),%%eax
38 \\ div %%ecx
39 \\ mov %%ebx,%%edx
40 \\ jmp 5f
41 \\ 1:
42 \\ mov %%eax,%%ecx
43 \\ mov 0x14(%%esp),%%ebx
44 \\ mov 0x10(%%esp),%%edx
45 \\ mov 0xc(%%esp),%%eax
46 \\ 2:
47 \\ shr %%ecx
48 \\ rcr %%ebx
49 \\ shr %%edx
50 \\ rcr %%eax
51 \\ or %%ecx,%%ecx
52 \\ jne 2b
53 \\ div %%ebx
54 \\ mov %%eax,%%esi
55 \\ mull 0x18(%%esp)
56 \\ mov %%eax,%%ecx
57 \\ mov 0x14(%%esp),%%eax
58 \\ mul %%esi
59 \\ add %%ecx,%%edx
60 \\ jb 3f
61 \\ cmp 0x10(%%esp),%%edx
62 \\ ja 3f
63 \\ jb 4f
64 \\ cmp 0xc(%%esp),%%eax
65 \\ jbe 4f
66 \\ 3:
67 \\ dec %%esi
68 \\ 4:
69 \\ xor %%edx,%%edx
70 \\ mov %%esi,%%eax
71 \\ 5:
72 \\ pop %%esi
73 \\ pop %%ebx
74 \\ ret $0x10
5475 );
5576}
lib/std/special/compiler_rt/aullrem.zig+72-51
......@@ -1,56 +1,77 @@
1const builtin = @import("builtin");
2
3pub extern stdcallcc fn _allrem(a: i64, b: i64) i64 {
4 @setRuntimeSafety(builtin.is_test);
5 const s_a = a >> (i64.bit_count - 1);
6 const s_b = b >> (i64.bit_count - 1);
7
8 const an = (a ^ s_a) -% s_a;
9 const bn = (b ^ s_b) -% s_b;
10
11 const r = @bitCast(u64, an) % @bitCast(u64, bn);
12 const s = s_a ^ s_b;
13 return (@bitCast(i64, r) ^ s) -% s;
14}
15
116pub nakedcc fn _aullrem() void {
217 @setRuntimeSafety(false);
18
19 // The stack layout is:
20 // ESP+16 divisor (hi)
21 // ESP+12 divisor (low)
22 // ESP+8 dividend (hi)
23 // ESP+4 dividend (low)
24 // ESP return address
25
326 asm volatile (
4 \\.intel_syntax noprefix
5 \\
6 \\ push ebx
7 \\ mov eax,dword ptr [esp+14h]
8 \\ or eax,eax
9 \\ jne L1a
10 \\ mov ecx,dword ptr [esp+10h]
11 \\ mov eax,dword ptr [esp+0Ch]
12 \\ xor edx,edx
13 \\ div ecx
14 \\ mov eax,dword ptr [esp+8]
15 \\ div ecx
16 \\ mov eax,edx
17 \\ xor edx,edx
18 \\ jmp L2a
19 \\ L1a:
20 \\ mov ecx,eax
21 \\ mov ebx,dword ptr [esp+10h]
22 \\ mov edx,dword ptr [esp+0Ch]
23 \\ mov eax,dword ptr [esp+8]
24 \\ L3a:
25 \\ shr ecx,1
26 \\ rcr ebx,1
27 \\ shr edx,1
28 \\ rcr eax,1
29 \\ or ecx,ecx
30 \\ jne L3a
31 \\ div ebx
32 \\ mov ecx,eax
33 \\ mul dword ptr [esp+14h]
34 \\ xchg eax,ecx
35 \\ mul dword ptr [esp+10h]
36 \\ add edx,ecx
37 \\ jb L4a
38 \\ cmp edx,dword ptr [esp+0Ch]
39 \\ ja L4a
40 \\ jb L5a
41 \\ cmp eax,dword ptr [esp+8]
42 \\ jbe L5a
43 \\ L4a:
44 \\ sub eax,dword ptr [esp+10h]
45 \\ sbb edx,dword ptr [esp+14h]
46 \\ L5a:
47 \\ sub eax,dword ptr [esp+8]
48 \\ sbb edx,dword ptr [esp+0Ch]
49 \\ neg edx
50 \\ neg eax
51 \\ sbb edx,0
52 \\ L2a:
53 \\ pop ebx
54 \\ ret 10h
27 \\ push %%ebx
28 \\ mov 0x14(%%esp),%%eax
29 \\ or %%eax,%%eax
30 \\ jne 1f
31 \\ mov 0x10(%%esp),%%ecx
32 \\ mov 0xc(%%esp),%%eax
33 \\ xor %%edx,%%edx
34 \\ div %%ecx
35 \\ mov 0x8(%%esp),%%eax
36 \\ div %%ecx
37 \\ mov %%edx,%%eax
38 \\ xor %%edx,%%edx
39 \\ jmp 6f
40 \\ 1:
41 \\ mov %%eax,%%ecx
42 \\ mov 0x10(%%esp),%%ebx
43 \\ mov 0xc(%%esp),%%edx
44 \\ mov 0x8(%%esp),%%eax
45 \\ 2:
46 \\ shr %%ecx
47 \\ rcr %%ebx
48 \\ shr %%edx
49 \\ rcr %%eax
50 \\ or %%ecx,%%ecx
51 \\ jne 2b
52 \\ div %%ebx
53 \\ mov %%eax,%%ecx
54 \\ mull 0x14(%%esp)
55 \\ xchg %%eax,%%ecx
56 \\ mull 0x10(%%esp)
57 \\ add %%ecx,%%edx
58 \\ jb 3f
59 \\ cmp 0xc(%%esp),%%edx
60 \\ ja 3f
61 \\ jb 4f
62 \\ cmp 0x8(%%esp),%%eax
63 \\ jbe 4f
64 \\ 3:
65 \\ sub 0x10(%%esp),%%eax
66 \\ sbb 0x14(%%esp),%%edx
67 \\ 4:
68 \\ sub 0x8(%%esp),%%eax
69 \\ sbb 0xc(%%esp),%%edx
70 \\ neg %%edx
71 \\ neg %%eax
72 \\ sbb $0x0,%%edx
73 \\ 6:
74 \\ pop %%ebx
75 \\ ret $0x10
5576 );
5677}
lib/std/special/compiler_rt/extendXfYf2_test.zig+5-1
......@@ -1,3 +1,4 @@
1const builtin = @import("builtin");
12const __extenddftf2 = @import("extendXfYf2.zig").__extenddftf2;
23const __extendhfsf2 = @import("extendXfYf2.zig").__extendhfsf2;
34const __extendsftf2 = @import("extendXfYf2.zig").__extendsftf2;
......@@ -87,7 +88,10 @@ test "extenddftf2" {
8788test "extendhfsf2" {
8889 test__extendhfsf2(0x7e00, 0x7fc00000); // qNaN
8990 test__extendhfsf2(0x7f00, 0x7fe00000); // sNaN
90 test__extendhfsf2(0x7c01, 0x7f802000); // sNaN
91 // On x86 the NaN becomes quiet because the return is pushed on the x87
92 // stack due to ABI requirements
93 if (builtin.arch != .i386 and builtin.os == .windows)
94 test__extendhfsf2(0x7c01, 0x7f802000); // sNaN
9195
9296 test__extendhfsf2(0, 0); // 0
9397 test__extendhfsf2(0x8000, 0x80000000); // -0
lib/std/special/start_windows_tls.zig+12
......@@ -1,4 +1,5 @@
11const std = @import("std");
2const builtin = @import("builtin");
23
34export var _tls_index: u32 = std.os.windows.TLS_OUT_OF_INDEXES;
45export var _tls_start: u8 linksection(".tls") = 0;
......@@ -6,6 +7,17 @@ export var _tls_end: u8 linksection(".tls$ZZZ") = 0;
67export var __xl_a: std.os.windows.PIMAGE_TLS_CALLBACK linksection(".CRT$XLA") = null;
78export var __xl_z: std.os.windows.PIMAGE_TLS_CALLBACK linksection(".CRT$XLZ") = null;
89
10comptime {
11 if (builtin.arch == .i386) {
12 // The __tls_array is the offset of the ThreadLocalStoragePointer field
13 // in the TEB block whose base address held in the %fs segment.
14 asm (
15 \\ .global __tls_array
16 \\ __tls_array = 0x2C
17 );
18 }
19}
20
921// TODO this is how I would like it to be expressed
1022// TODO also note, ReactOS has a +1 on StartAddressOfRawData and AddressOfCallBacks. Investigate
1123// why they do that.
src/analyze.cpp+4-1
......@@ -913,7 +913,10 @@ bool want_first_arg_sret(CodeGen *g, FnTypeId *fn_type_id) {
913913 if (type_is_c_abi_int(g, fn_type_id->return_type)) {
914914 return false;
915915 }
916 if (g->zig_target->arch == ZigLLVM_x86_64) {
916 if (g->zig_target->arch == ZigLLVM_x86) {
917 X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type);
918 return abi_class == X64CABIClass_MEMORY;
919 } else if (g->zig_target->arch == ZigLLVM_x86_64) {
917920 X64CABIClass abi_class = type_c_abi_x86_64_class(g, fn_type_id->return_type);
918921 return abi_class == X64CABIClass_MEMORY;
919922 } else if (target_is_arm(g->zig_target) || target_is_riscv(g->zig_target)) {
src/codegen.cpp+3
......@@ -8727,6 +8727,9 @@ static void init(CodeGen *g) {
87278727 // Be aware of https://github.com/ziglang/zig/issues/3275
87288728 target_specific_cpu_args = "";
87298729 target_specific_features = riscv_default_features;
8730 } else if (g->zig_target->arch == ZigLLVM_x86) {
8731 target_specific_cpu_args = "pentium4";
8732 target_specific_features = "";
87308733 } else {
87318734 target_specific_cpu_args = "";
87328735 target_specific_features = "";