| author |  Jakub Konka <kubkon@jakubkonka.com> 2023-03-11 16:32:30+01:00 |
| committer | Jakub Konka <kubkon@jakubkonka.com> 2023-03-11 20:05:50+01:00 |
| log | fb38e3d6b29f71834c7ea4ef21e4d3f607c03777 |
| tree | 468c8ba37e6fb648c0f138569fe8ea88c40342f3 |
| parent | 0a8b5c20aa2402361a4e5698100902e47bd2c7c6 |
x86_64: simplify immediate handling at MIR level
3 files changed, 128 insertions(+), 146 deletions(-)
src- arch
src/arch/x86_64/CodeGen.zig+34-43
| ... | @@ -460,15 +460,13 @@ fn asmRegister(self: *Self, tag: Mir.Inst.Tag, reg: Register) !void { | ... | @@ -460,15 +460,13 @@ fn asmRegister(self: *Self, tag: Mir.Inst.Tag, reg: Register) !void { |
| 460 | 460 | ||
| 461 | fn asmImmediate(self: *Self, tag: Mir.Inst.Tag, imm: Immediate) !void { | 461 | fn asmImmediate(self: *Self, tag: Mir.Inst.Tag, imm: Immediate) !void { |
| 462 | const ops: Mir.Inst.Ops = if (imm == .signed) .imm_s else .imm_u; | 462 | const ops: Mir.Inst.Ops = if (imm == .signed) .imm_s else .imm_u; |
| 463 | const data: Mir.Inst.Data = switch (ops) { | ||
| 464 | .imm_s => .{ .imm_s = imm.signed }, | ||
| 465 | .imm_u => .{ .imm_u = @intCast(u32, imm.unsigned) }, | ||
| 466 | else => unreachable, | ||
| 467 | }; | ||
| 468 | _ = try self.addInst(.{ | 463 | _ = try self.addInst(.{ |
| 469 | .tag = tag, | 464 | .tag = tag, |
| 470 | .ops = ops, | 465 | .ops = ops, |
| 471 | .data = data, | 466 | .data = .{ .imm = switch (imm) { |
| 467 | .signed => |x| @bitCast(u32, x), | ||
| 468 | .unsigned => |x| @intCast(u32, x), | ||
| 469 | } }, | ||
| 472 | }); | 470 | }); |
| 473 | } | 471 | } |
| 474 | 472 | ||
| ... | @@ -489,11 +487,11 @@ fn asmRegisterImmediate(self: *Self, tag: Mir.Inst.Tag, reg: Register, imm: Imme | ... | @@ -489,11 +487,11 @@ fn asmRegisterImmediate(self: *Self, tag: Mir.Inst.Tag, reg: Register, imm: Imme |
| 489 | .unsigned => |x| if (x <= math.maxInt(u32)) .ri_u else .ri64, | 487 | .unsigned => |x| if (x <= math.maxInt(u32)) .ri_u else .ri64, |
| 490 | }; | 488 | }; |
| 491 | const data: Mir.Inst.Data = switch (ops) { | 489 | const data: Mir.Inst.Data = switch (ops) { |
| 492 | .ri_s => .{ .ri_s = .{ | 490 | .ri_s => .{ .ri = .{ |
| 493 | .r1 = reg, | 491 | .r1 = reg, |
| 494 | .imm = imm.signed, | 492 | .imm = @bitCast(u32, imm.signed), |
| 495 | } }, | 493 | } }, |
| 496 | .ri_u => .{ .ri_u = .{ | 494 | .ri_u => .{ .ri = .{ |
| 497 | .r1 = reg, | 495 | .r1 = reg, |
| 498 | .imm = @intCast(u32, imm.unsigned), | 496 | .imm = @intCast(u32, imm.unsigned), |
| 499 | } }, | 497 | } }, |
| ... | @@ -522,12 +520,12 @@ fn asmRegisterRegisterImmediate( | ... | @@ -522,12 +520,12 @@ fn asmRegisterRegisterImmediate( |
| 522 | .unsigned => .rri_u, | 520 | .unsigned => .rri_u, |
| 523 | }; | 521 | }; |
| 524 | const data: Mir.Inst.Data = switch (ops) { | 522 | const data: Mir.Inst.Data = switch (ops) { |
| 525 | .rri_s => .{ .rri_s = .{ | 523 | .rri_s => .{ .rri = .{ |
| 526 | .r1 = reg1, | 524 | .r1 = reg1, |
| 527 | .r2 = reg2, | 525 | .r2 = reg2, |
| 528 | .imm = imm.signed, | 526 | .imm = @bitCast(u32, imm.signed), |
| 529 | } }, | 527 | } }, |
| 530 | .rri_u => .{ .rri_u = .{ | 528 | .rri_u => .{ .rri = .{ |
| 531 | .r1 = reg1, | 529 | .r1 = reg1, |
| 532 | .r2 = reg2, | 530 | .r2 = reg2, |
| 533 | .imm = @intCast(u32, imm.unsigned), | 531 | .imm = @intCast(u32, imm.unsigned), |
| ... | @@ -547,11 +545,11 @@ fn asmMemory(self: *Self, tag: Mir.Inst.Tag, m: Memory) !void { | ... | @@ -547,11 +545,11 @@ fn asmMemory(self: *Self, tag: Mir.Inst.Tag, m: Memory) !void { |
| 547 | .rip => .m_rip, | 545 | .rip => .m_rip, |
| 548 | else => unreachable, | 546 | else => unreachable, |
| 549 | }; | 547 | }; |
| 550 | const data: Mir.Inst.Data = switch (ops) { | 548 | const data: Mir.Inst.Data = .{ .payload = switch (ops) { |
| 551 | .m_sib => .{ .payload = try self.addExtra(Mir.MemorySib.encode(m)) }, | 549 | .m_sib => try self.addExtra(Mir.MemorySib.encode(m)), |
| 552 | .m_rip => .{ .payload = try self.addExtra(Mir.MemoryRip.encode(m)) }, | 550 | .m_rip => try self.addExtra(Mir.MemoryRip.encode(m)), |
| 553 | else => unreachable, | 551 | else => unreachable, |
| 554 | }; | 552 | } }; |
| 555 | _ = try self.addInst(.{ | 553 | _ = try self.addInst(.{ |
| 556 | .tag = tag, | 554 | .tag = tag, |
| 557 | .ops = ops, | 555 | .ops = ops, |
| ... | @@ -570,10 +568,11 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.Tag, m: Memory, imm: Immediate) | ... | @@ -570,10 +568,11 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.Tag, m: Memory, imm: Immediate) |
| 570 | .mi_s_rip, .mi_u_rip => try self.addExtra(Mir.MemoryRip.encode(m)), | 568 | .mi_s_rip, .mi_u_rip => try self.addExtra(Mir.MemoryRip.encode(m)), |
| 571 | else => unreachable, | 569 | else => unreachable, |
| 572 | }; | 570 | }; |
| 573 | const data: Mir.Inst.Data = switch (ops) { | 571 | const data: Mir.Inst.Data = .{ |
| 574 | .mi_s_sib, .mi_s_rip => .{ .xi_s = .{ .imm = imm.signed, .payload = payload } }, | 572 | .xi = .{ .payload = payload, .imm = switch (imm) { |
| 575 | .mi_u_sib, .mi_u_rip => .{ .xi_u = .{ .imm = @intCast(u32, imm.unsigned), .payload = payload } }, | 573 | .signed => |x| @bitCast(u32, x), |
| 576 | else => unreachable, | 574 | .unsigned => |x| @intCast(u32, x), |
| 575 | } }, | ||
| 577 | }; | 576 | }; |
| 578 | _ = try self.addInst(.{ | 577 | _ = try self.addInst(.{ |
| 579 | .tag = tag, | 578 | .tag = tag, |
| ... | @@ -588,16 +587,12 @@ fn asmRegisterMemory(self: *Self, tag: Mir.Inst.Tag, reg: Register, m: Memory) ! | ... | @@ -588,16 +587,12 @@ fn asmRegisterMemory(self: *Self, tag: Mir.Inst.Tag, reg: Register, m: Memory) ! |
| 588 | .rip => .rm_rip, | 587 | .rip => .rm_rip, |
| 589 | else => unreachable, | 588 | else => unreachable, |
| 590 | }; | 589 | }; |
| 591 | const data: Mir.Inst.Data = switch (ops) { | 590 | const data: Mir.Inst.Data = .{ |
| 592 | .rm_sib => .{ .rx = .{ | 591 | .rx = .{ .r1 = reg, .payload = switch (ops) { |
| 593 | .r1 = reg, | 592 | .rm_sib => try self.addExtra(Mir.MemorySib.encode(m)), |
| 594 | .payload = try self.addExtra(Mir.MemorySib.encode(m)), | 593 | .rm_rip => try self.addExtra(Mir.MemoryRip.encode(m)), |
| 595 | } }, | 594 | else => unreachable, |
| 596 | .rm_rip => .{ .rx = .{ | ||
| 597 | .r1 = reg, | ||
| 598 | .payload = try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 599 | } }, | 595 | } }, |
| 600 | else => unreachable, | ||
| 601 | }; | 596 | }; |
| 602 | _ = try self.addInst(.{ | 597 | _ = try self.addInst(.{ |
| 603 | .tag = tag, | 598 | .tag = tag, |
| ... | @@ -612,16 +607,12 @@ fn asmMemoryRegister(self: *Self, tag: Mir.Inst.Tag, m: Memory, reg: Register) ! | ... | @@ -612,16 +607,12 @@ fn asmMemoryRegister(self: *Self, tag: Mir.Inst.Tag, m: Memory, reg: Register) ! |
| 612 | .rip => .mr_rip, | 607 | .rip => .mr_rip, |
| 613 | else => unreachable, | 608 | else => unreachable, |
| 614 | }; | 609 | }; |
| 615 | const data: Mir.Inst.Data = switch (ops) { | 610 | const data: Mir.Inst.Data = .{ |
| 616 | .mr_sib => .{ .rx = .{ | 611 | .rx = .{ .r1 = reg, .payload = switch (ops) { |
| 617 | .r1 = reg, | 612 | .mr_sib => try self.addExtra(Mir.MemorySib.encode(m)), |
| 618 | .payload = try self.addExtra(Mir.MemorySib.encode(m)), | 613 | .mr_rip => try self.addExtra(Mir.MemoryRip.encode(m)), |
| 619 | } }, | 614 | else => unreachable, |
| 620 | .mr_rip => .{ .rx = .{ | ||
| 621 | .r1 = reg, | ||
| 622 | .payload = try self.addExtra(Mir.MemoryRip.encode(m)), | ||
| 623 | } }, | 615 | } }, |
| 624 | else => unreachable, | ||
| 625 | }; | 616 | }; |
| 626 | _ = try self.addInst(.{ | 617 | _ = try self.addInst(.{ |
| 627 | .tag = tag, | 618 | .tag = tag, |
| ... | @@ -733,7 +724,7 @@ fn gen(self: *Self) InnerError!void { | ... | @@ -733,7 +724,7 @@ fn gen(self: *Self) InnerError!void { |
| 733 | self.mir_instructions.set(backpatch_stack_sub, .{ | 724 | self.mir_instructions.set(backpatch_stack_sub, .{ |
| 734 | .tag = .sub, | 725 | .tag = .sub, |
| 735 | .ops = .ri_u, | 726 | .ops = .ri_u, |
| 736 | .data = .{ .ri_u = .{ | 727 | .data = .{ .ri = .{ |
| 737 | .r1 = .rsp, | 728 | .r1 = .rsp, |
| 738 | .imm = aligned_stack_end, | 729 | .imm = aligned_stack_end, |
| 739 | } }, | 730 | } }, |
| ... | @@ -741,7 +732,7 @@ fn gen(self: *Self) InnerError!void { | ... | @@ -741,7 +732,7 @@ fn gen(self: *Self) InnerError!void { |
| 741 | self.mir_instructions.set(backpatch_stack_add, .{ | 732 | self.mir_instructions.set(backpatch_stack_add, .{ |
| 742 | .tag = .add, | 733 | .tag = .add, |
| 743 | .ops = .ri_u, | 734 | .ops = .ri_u, |
| 744 | .data = .{ .ri_u = .{ | 735 | .data = .{ .ri = .{ |
| 745 | .r1 = .rsp, | 736 | .r1 = .rsp, |
| 746 | .imm = aligned_stack_end, | 737 | .imm = aligned_stack_end, |
| 747 | } }, | 738 | } }, |
| ... | @@ -5602,7 +5593,7 @@ fn genInlineMemcpy( | ... | @@ -5602,7 +5593,7 @@ fn genInlineMemcpy( |
| 5602 | const loop_start = try self.addInst(.{ | 5593 | const loop_start = try self.addInst(.{ |
| 5603 | .tag = .cmp, | 5594 | .tag = .cmp, |
| 5604 | .ops = .ri_u, | 5595 | .ops = .ri_u, |
| 5605 | .data = .{ .ri_u = .{ | 5596 | .data = .{ .ri = .{ |
| 5606 | .r1 = count_reg, | 5597 | .r1 = count_reg, |
| 5607 | .imm = 0, | 5598 | .imm = 0, |
| 5608 | } }, | 5599 | } }, |
| ... | @@ -5681,9 +5672,9 @@ fn genInlineMemset( | ... | @@ -5681,9 +5672,9 @@ fn genInlineMemset( |
| 5681 | const loop_start = try self.addInst(.{ | 5672 | const loop_start = try self.addInst(.{ |
| 5682 | .tag = .cmp, | 5673 | .tag = .cmp, |
| 5683 | .ops = .ri_s, | 5674 | .ops = .ri_s, |
| 5684 | .data = .{ .ri_s = .{ | 5675 | .data = .{ .ri = .{ |
| 5685 | .r1 = index_reg, | 5676 | .r1 = index_reg, |
| 5686 | .imm = -1, | 5677 | .imm = @bitCast(u32, @as(i32, -1)), |
| 5687 | } }, | 5678 | } }, |
| 5688 | }); | 5679 | }); |
| 5689 | const loop_reloc = try self.asmJccReloc(undefined, .e); | 5680 | const loop_reloc = try self.asmJccReloc(undefined, .e); |
src/arch/x86_64/Emit.zig+76-66
| ... | @@ -194,105 +194,115 @@ fn mirEncodeGeneric(emit: *Emit, tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerE | ... | @@ -194,105 +194,115 @@ fn mirEncodeGeneric(emit: *Emit, tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerE |
| 194 | const ops = emit.mir.instructions.items(.ops)[inst]; | 194 | const ops = emit.mir.instructions.items(.ops)[inst]; |
| 195 | const data = emit.mir.instructions.items(.data)[inst]; | 195 | const data = emit.mir.instructions.items(.data)[inst]; |
| 196 | 196 | ||
| 197 | var operands = [4]Instruction.Operand{ .none, .none, .none, .none }; | 197 | var op1: Instruction.Operand = .none; |
| 198 | var op2: Instruction.Operand = .none; | ||
| 199 | var op3: Instruction.Operand = .none; | ||
| 200 | var op4: Instruction.Operand = .none; | ||
| 201 | |||
| 198 | switch (ops) { | 202 | switch (ops) { |
| 199 | .none => {}, | 203 | .none => {}, |
| 200 | .imm_s => operands[0] = .{ .imm = Immediate.s(data.imm_s) }, | 204 | .imm_s => op1 = .{ .imm = Immediate.s(@bitCast(i32, data.imm)) }, |
| 201 | .imm_u => operands[0] = .{ .imm = Immediate.u(data.imm_u) }, | 205 | .imm_u => op1 = .{ .imm = Immediate.u(data.imm) }, |
| 202 | .r => operands[0] = .{ .reg = data.r }, | 206 | .r => op1 = .{ .reg = data.r }, |
| 203 | .rr => operands[0..2].* = .{ | 207 | .rr => { |
| 204 | .{ .reg = data.rr.r1 }, | 208 | op1 = .{ .reg = data.rr.r1 }; |
| 205 | .{ .reg = data.rr.r2 }, | 209 | op2 = .{ .reg = data.rr.r2 }; |
| 206 | }, | ||
| 207 | .ri_s => operands[0..2].* = .{ | ||
| 208 | .{ .reg = data.ri_s.r1 }, | ||
| 209 | .{ .imm = Immediate.s(data.ri_s.imm) }, | ||
| 210 | }, | 210 | }, |
| 211 | .ri_u => operands[0..2].* = .{ | 211 | .ri_s, .ri_u => { |
| 212 | .{ .reg = data.ri_u.r1 }, | 212 | const imm = switch (ops) { |
| 213 | .{ .imm = Immediate.u(data.ri_u.imm) }, | 213 | .ri_s => Immediate.s(@bitCast(i32, data.ri.imm)), |
| 214 | .ri_u => Immediate.u(data.ri.imm), | ||
| 215 | else => unreachable, | ||
| 216 | }; | ||
| 217 | op1 = .{ .reg = data.ri.r1 }; | ||
| 218 | op2 = .{ .imm = imm }; | ||
| 214 | }, | 219 | }, |
| 215 | .ri64 => { | 220 | .ri64 => { |
| 216 | const imm64 = emit.mir.extraData(Mir.Imm64, data.rx.payload).data; | 221 | const imm64 = emit.mir.extraData(Mir.Imm64, data.rx.payload).data; |
| 217 | operands[0..2].* = .{ | 222 | op1 = .{ .reg = data.rx.r1 }; |
| 218 | .{ .reg = data.rx.r1 }, | 223 | op2 = .{ .imm = Immediate.u(Mir.Imm64.decode(imm64)) }; |
| 219 | .{ .imm = Immediate.u(Mir.Imm64.decode(imm64)) }, | ||
| 220 | }; | ||
| 221 | }, | ||
| 222 | .rri_s => operands[0..3].* = .{ | ||
| 223 | .{ .reg = data.rri_s.r1 }, | ||
| 224 | .{ .reg = data.rri_s.r2 }, | ||
| 225 | .{ .imm = Immediate.s(data.rri_s.imm) }, | ||
| 226 | }, | 224 | }, |
| 227 | .rri_u => operands[0..3].* = .{ | 225 | .rri_s, .rri_u => { |
| 228 | .{ .reg = data.rri_u.r1 }, | 226 | const imm = switch (ops) { |
| 229 | .{ .reg = data.rri_u.r2 }, | 227 | .rri_s => Immediate.s(@bitCast(i32, data.rri.imm)), |
| 230 | .{ .imm = Immediate.u(data.rri_u.imm) }, | 228 | .rri_u => Immediate.u(data.rri.imm), |
| 229 | else => unreachable, | ||
| 230 | }; | ||
| 231 | op1 = .{ .reg = data.rri.r1 }; | ||
| 232 | op2 = .{ .reg = data.rri.r2 }; | ||
| 233 | op3 = .{ .imm = imm }; | ||
| 231 | }, | 234 | }, |
| 232 | .m_sib => { | 235 | .m_sib => { |
| 233 | const msib = emit.mir.extraData(Mir.MemorySib, data.payload).data; | 236 | const msib = emit.mir.extraData(Mir.MemorySib, data.payload).data; |
| 234 | operands[0] = .{ .mem = Mir.MemorySib.decode(msib) }; | 237 | op1 = .{ .mem = Mir.MemorySib.decode(msib) }; |
| 235 | }, | 238 | }, |
| 236 | .m_rip => { | 239 | .m_rip => { |
| 237 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.payload).data; | 240 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.payload).data; |
| 238 | operands[0] = .{ .mem = Mir.MemoryRip.decode(mrip) }; | 241 | op1 = .{ .mem = Mir.MemoryRip.decode(mrip) }; |
| 239 | }, | ||
| 240 | .mi_u_sib => { | ||
| 241 | const msib = emit.mir.extraData(Mir.MemorySib, data.xi_u.payload).data; | ||
| 242 | operands[0..2].* = .{ | ||
| 243 | .{ .mem = Mir.MemorySib.decode(msib) }, | ||
| 244 | .{ .imm = Immediate.u(data.xi_u.imm) }, | ||
| 245 | }; | ||
| 246 | }, | ||
| 247 | .mi_s_sib => { | ||
| 248 | const msib = emit.mir.extraData(Mir.MemorySib, data.xi_s.payload).data; | ||
| 249 | operands[0..2].* = .{ | ||
| 250 | .{ .mem = Mir.MemorySib.decode(msib) }, | ||
| 251 | .{ .imm = Immediate.s(data.xi_s.imm) }, | ||
| 252 | }; | ||
| 253 | }, | 242 | }, |
| 254 | .mi_u_rip => { | 243 | .mi_s_sib, .mi_u_sib => { |
| 255 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.xi_u.payload).data; | 244 | const msib = emit.mir.extraData(Mir.MemorySib, data.xi.payload).data; |
| 256 | operands[0..2].* = .{ | 245 | const imm = switch (ops) { |
| 257 | .{ .mem = Mir.MemoryRip.decode(mrip) }, | 246 | .mi_s_sib => Immediate.s(@bitCast(i32, data.xi.imm)), |
| 258 | .{ .imm = Immediate.u(data.xi_u.imm) }, | 247 | .mi_u_sib => Immediate.u(data.xi.imm), |
| 248 | else => unreachable, | ||
| 259 | }; | 249 | }; |
| 250 | op1 = .{ .mem = Mir.MemorySib.decode(msib) }; | ||
| 251 | op2 = .{ .imm = imm }; | ||
| 260 | }, | 252 | }, |
| 261 | .mi_s_rip => { | 253 | .mi_u_rip, .mi_s_rip => { |
| 262 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.xi_s.payload).data; | 254 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.xi.payload).data; |
| 263 | operands[0..2].* = .{ | 255 | const imm = switch (ops) { |
| 264 | .{ .mem = Mir.MemoryRip.decode(mrip) }, | 256 | .mi_s_rip => Immediate.s(@bitCast(i32, data.xi.imm)), |
| 265 | .{ .imm = Immediate.s(data.xi_s.imm) }, | 257 | .mi_u_rip => Immediate.u(data.xi.imm), |
| 258 | else => unreachable, | ||
| 266 | }; | 259 | }; |
| 260 | op1 = .{ .mem = Mir.MemoryRip.decode(mrip) }; | ||
| 261 | op2 = .{ .imm = imm }; | ||
| 267 | }, | 262 | }, |
| 268 | .rm_sib, .mr_sib => { | 263 | .rm_sib, .mr_sib => { |
| 269 | const msib = emit.mir.extraData(Mir.MemorySib, data.rx.payload).data; | 264 | const msib = emit.mir.extraData(Mir.MemorySib, data.rx.payload).data; |
| 270 | const op1 = .{ .reg = data.rx.r1 }; | 265 | const op_r = .{ .reg = data.rx.r1 }; |
| 271 | const op2 = .{ .mem = Mir.MemorySib.decode(msib) }; | 266 | const op_m = .{ .mem = Mir.MemorySib.decode(msib) }; |
| 272 | switch (ops) { | 267 | switch (ops) { |
| 273 | .rm_sib => operands[0..2].* = .{ op1, op2 }, | 268 | .rm_sib => { |
| 274 | .mr_sib => operands[0..2].* = .{ op2, op1 }, | 269 | op1 = op_r; |
| 270 | op2 = op_m; | ||
| 271 | }, | ||
| 272 | .mr_sib => { | ||
| 273 | op1 = op_m; | ||
| 274 | op2 = op_r; | ||
| 275 | }, | ||
| 275 | else => unreachable, | 276 | else => unreachable, |
| 276 | } | 277 | } |
| 277 | }, | 278 | }, |
| 278 | .rm_rip, .mr_rip => { | 279 | .rm_rip, .mr_rip => { |
| 279 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.rx.payload).data; | 280 | const mrip = emit.mir.extraData(Mir.MemoryRip, data.rx.payload).data; |
| 280 | const op1 = .{ .reg = data.rx.r1 }; | 281 | const op_r = .{ .reg = data.rx.r1 }; |
| 281 | const op2 = .{ .mem = Mir.MemoryRip.decode(mrip) }; | 282 | const op_m = .{ .mem = Mir.MemoryRip.decode(mrip) }; |
| 282 | switch (ops) { | 283 | switch (ops) { |
| 283 | .rm_rip => operands[0..2].* = .{ op1, op2 }, | 284 | .rm_sib => { |
| 284 | .mr_rip => operands[0..2].* = .{ op2, op1 }, | 285 | op1 = op_r; |
| 286 | op2 = op_m; | ||
| 287 | }, | ||
| 288 | .mr_sib => { | ||
| 289 | op1 = op_m; | ||
| 290 | op2 = op_r; | ||
| 291 | }, | ||
| 285 | else => unreachable, | 292 | else => unreachable, |
| 286 | } | 293 | } |
| 287 | }, | 294 | }, |
| 288 | else => unreachable, // TODO | 295 | else => return emit.fail("TODO handle generic encoding: {s}, {s}", .{ |
| 296 | @tagName(mnemonic), | ||
| 297 | @tagName(ops), | ||
| 298 | }), | ||
| 289 | } | 299 | } |
| 290 | 300 | ||
| 291 | return emit.encode(mnemonic, .{ | 301 | return emit.encode(mnemonic, .{ |
| 292 | .op1 = operands[0], | 302 | .op1 = op1, |
| 293 | .op2 = operands[1], | 303 | .op2 = op2, |
| 294 | .op3 = operands[2], | 304 | .op3 = op3, |
| 295 | .op4 = operands[3], | 305 | .op4 = op4, |
| 296 | }); | 306 | }); |
| 297 | } | 307 | } |
| 298 | 308 |
src/arch/x86_64/Mir.zig+18-37
| ... | @@ -182,10 +182,10 @@ pub const Inst = struct { | ... | @@ -182,10 +182,10 @@ pub const Inst = struct { |
| 182 | /// Uses `rrr` payload. | 182 | /// Uses `rrr` payload. |
| 183 | rrr, | 183 | rrr, |
| 184 | /// Register, register, immediate (sign-extended) operands. | 184 | /// Register, register, immediate (sign-extended) operands. |
| 185 | /// Uses `rri_s` payload. | 185 | /// Uses `rri` payload. |
| 186 | rri_s, | 186 | rri_s, |
| 187 | /// Register, register, immediate (unsigned) operands. | 187 | /// Register, register, immediate (unsigned) operands. |
| 188 | /// Uses `rri_u` payload. | 188 | /// Uses `rri` payload. |
| 189 | rri_u, | 189 | rri_u, |
| 190 | /// Register with condition code (CC). | 190 | /// Register with condition code (CC). |
| 191 | /// Uses `r_c` payload. | 191 | /// Uses `r_c` payload. |
| ... | @@ -194,22 +194,22 @@ pub const Inst = struct { | ... | @@ -194,22 +194,22 @@ pub const Inst = struct { |
| 194 | /// Uses `rr_c` payload. | 194 | /// Uses `rr_c` payload. |
| 195 | rr_c, | 195 | rr_c, |
| 196 | /// Register, immediate (sign-extended) operands. | 196 | /// Register, immediate (sign-extended) operands. |
| 197 | /// Uses `ri_s` payload. | 197 | /// Uses `ri` payload. |
| 198 | ri_s, | 198 | ri_s, |
| 199 | /// Register, immediate (unsigned) operands. | 199 | /// Register, immediate (unsigned) operands. |
| 200 | /// Uses `ri_u` payload. | 200 | /// Uses `ri` payload. |
| 201 | ri_u, | 201 | ri_u, |
| 202 | /// Register, 64-bit unsigned immediate operands. | 202 | /// Register, 64-bit unsigned immediate operands. |
| 203 | /// Uses `rx` payload with payload type `Imm64`. | 203 | /// Uses `rx` payload with payload type `Imm64`. |
| 204 | ri64, | 204 | ri64, |
| 205 | /// Immediate (sign-extended) operand. | 205 | /// Immediate (sign-extended) operand. |
| 206 | /// Uses `imm_s` payload. | 206 | /// Uses `imm` payload. |
| 207 | imm_s, | 207 | imm_s, |
| 208 | /// Immediate (unsigned) operand. | 208 | /// Immediate (unsigned) operand. |
| 209 | /// Uses `imm_u` payload. | 209 | /// Uses `imm` payload. |
| 210 | imm_u, | 210 | imm_u, |
| 211 | /// Relative displacement operand. | 211 | /// Relative displacement operand. |
| 212 | /// Uses `rel` payload. | 212 | /// Uses `imm` payload. |
| 213 | rel, | 213 | rel, |
| 214 | /// Register, memory (SIB) operands. | 214 | /// Register, memory (SIB) operands. |
| 215 | /// Uses `rx` payload. | 215 | /// Uses `rx` payload. |
| ... | @@ -224,16 +224,16 @@ pub const Inst = struct { | ... | @@ -224,16 +224,16 @@ pub const Inst = struct { |
| 224 | /// Uses `payload` with extra data of type `MemoryRip`. | 224 | /// Uses `payload` with extra data of type `MemoryRip`. |
| 225 | m_rip, | 225 | m_rip, |
| 226 | /// Memory (SIB), immediate (unsigned) operands. | 226 | /// Memory (SIB), immediate (unsigned) operands. |
| 227 | /// Uses `xi_u` payload with extra data of type `MemorySib`. | 227 | /// Uses `xi` payload with extra data of type `MemorySib`. |
| 228 | mi_u_sib, | 228 | mi_u_sib, |
| 229 | /// Memory (RIP), immediate (unsigned) operands. | 229 | /// Memory (RIP), immediate (unsigned) operands. |
| 230 | /// Uses `xi_u` payload with extra data of type `MemoryRip`. | 230 | /// Uses `xi` payload with extra data of type `MemoryRip`. |
| 231 | mi_u_rip, | 231 | mi_u_rip, |
| 232 | /// Memory (SIB), immediate (sign-extend) operands. | 232 | /// Memory (SIB), immediate (sign-extend) operands. |
| 233 | /// Uses `xi_s` payload with extra data of type `MemorySib`. | 233 | /// Uses `xi` payload with extra data of type `MemorySib`. |
| 234 | mi_s_sib, | 234 | mi_s_sib, |
| 235 | /// Memory (RIP), immediate (sign-extend) operands. | 235 | /// Memory (RIP), immediate (sign-extend) operands. |
| 236 | /// Uses `xi_s` payload with extra data of type `MemoryRip`. | 236 | /// Uses `xi` payload with extra data of type `MemoryRip`. |
| 237 | mi_s_rip, | 237 | mi_s_rip, |
| 238 | /// Memory (SIB), register operands. | 238 | /// Memory (SIB), register operands. |
| 239 | /// Uses `rx` payload with extra data of type `MemorySib`. | 239 | /// Uses `rx` payload with extra data of type `MemorySib`. |
| ... | @@ -281,12 +281,8 @@ pub const Inst = struct { | ... | @@ -281,12 +281,8 @@ pub const Inst = struct { |
| 281 | /// A condition code for use with EFLAGS register. | 281 | /// A condition code for use with EFLAGS register. |
| 282 | cc: bits.Condition, | 282 | cc: bits.Condition, |
| 283 | }, | 283 | }, |
| 284 | /// A 32-bit signed immediate value. | 284 | /// A 32-bit immediate value. |
| 285 | imm_s: i32, | 285 | imm: u32, |
| 286 | /// A 32-bit unsigned immediate value. | ||
| 287 | imm_u: u32, | ||
| 288 | /// A 32-bit signed relative offset value. | ||
| 289 | rel: i32, | ||
| 290 | r: Register, | 286 | r: Register, |
| 291 | rr: struct { | 287 | rr: struct { |
| 292 | r1: Register, | 288 | r1: Register, |
| ... | @@ -297,12 +293,7 @@ pub const Inst = struct { | ... | @@ -297,12 +293,7 @@ pub const Inst = struct { |
| 297 | r2: Register, | 293 | r2: Register, |
| 298 | r3: Register, | 294 | r3: Register, |
| 299 | }, | 295 | }, |
| 300 | rri_s: struct { | 296 | rri: struct { |
| 301 | r1: Register, | ||
| 302 | r2: Register, | ||
| 303 | imm: i32, | ||
| 304 | }, | ||
| 305 | rri_u: struct { | ||
| 306 | r1: Register, | 297 | r1: Register, |
| 307 | r2: Register, | 298 | r2: Register, |
| 308 | imm: u32, | 299 | imm: u32, |
| ... | @@ -318,13 +309,8 @@ pub const Inst = struct { | ... | @@ -318,13 +309,8 @@ pub const Inst = struct { |
| 318 | r2: Register, | 309 | r2: Register, |
| 319 | cc: bits.Condition, | 310 | cc: bits.Condition, |
| 320 | }, | 311 | }, |
| 321 | /// Register, signed immediate. | 312 | /// Register, immediate. |
| 322 | ri_s: struct { | 313 | ri: struct { |
| 323 | r1: Register, | ||
| 324 | imm: i32, | ||
| 325 | }, | ||
| 326 | /// Register, unsigned immediate. | ||
| 327 | ri_u: struct { | ||
| 328 | r1: Register, | 314 | r1: Register, |
| 329 | imm: u32, | 315 | imm: u32, |
| 330 | }, | 316 | }, |
| ... | @@ -333,16 +319,11 @@ pub const Inst = struct { | ... | @@ -333,16 +319,11 @@ pub const Inst = struct { |
| 333 | r1: Register, | 319 | r1: Register, |
| 334 | payload: u32, | 320 | payload: u32, |
| 335 | }, | 321 | }, |
| 336 | /// Custom payload followed by an unsigned immediate. | 322 | /// Custom payload followed by an immediate. |
| 337 | xi_u: struct { | 323 | xi: struct { |
| 338 | payload: u32, | 324 | payload: u32, |
| 339 | imm: u32, | 325 | imm: u32, |
| 340 | }, | 326 | }, |
| 341 | /// Custom payload followed by a signed immediate. | ||
| 342 | xi_s: struct { | ||
| 343 | payload: u32, | ||
| 344 | imm: i32, | ||
| 345 | }, | ||
| 346 | /// Relocation for the linker where: | 327 | /// Relocation for the linker where: |
| 347 | /// * `atom_index` is the index of the source | 328 | /// * `atom_index` is the index of the source |
| 348 | /// * `sym_index` is the index of the target | 329 | /// * `sym_index` is the index of the target |