authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-02-15 02:44:58+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-02-22 04:12:46+01:00
logfc7a0c4878dac2d721ec18cafe1b6bcff7faa771
tree5b9e4ef2d18e3daaf4bee34ae1bfe5af97916e8a
parentd31bda13cb1ece7dd2ba22339172a8704a84823c

Sema: Fix fnptr alignment safety checks to account for potential ISA tag.

As seen on e.g. Arm/Thumb and MIPS (MIPS16/microMIPS). Fixes #22888.

4 files changed, 53 insertions(+), 6 deletions(-)

src/Sema.zig+24-6
...@@ -23099,8 +23099,14 @@ fn zirPtrFromInt(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!...@@ -23099,8 +23099,14 @@ fn zirPtrFromInt(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!
23099 }23099 }
23100 if (ptr_align.compare(.gt, .@"1")) {23100 if (ptr_align.compare(.gt, .@"1")) {
23101 const align_bytes_minus_1 = ptr_align.toByteUnits().? - 1;23101 const align_bytes_minus_1 = ptr_align.toByteUnits().? - 1;
23102 const align_minus_1 = Air.internedToRef((try sema.splat(operand_ty, try pt.intValue(Type.usize, align_bytes_minus_1))).toIntern());23102 const align_mask = Air.internedToRef((try sema.splat(operand_ty, try pt.intValue(
23103 const remainder = try block.addBinOp(.bit_and, operand_coerced, align_minus_1);23103 Type.usize,
23104 if (elem_ty.fnPtrMaskOrNull(zcu)) |mask|
23105 align_bytes_minus_1 & mask
23106 else
23107 align_bytes_minus_1,
23108 ))).toIntern());
23109 const remainder = try block.addBinOp(.bit_and, operand_coerced, align_mask);
23104 const is_aligned = if (is_vector) all_aligned: {23110 const is_aligned = if (is_vector) all_aligned: {
23105 const splat_zero_usize = Air.internedToRef((try sema.splat(operand_ty, .zero_usize)).toIntern());23111 const splat_zero_usize = Air.internedToRef((try sema.splat(operand_ty, .zero_usize)).toIntern());
23106 const is_aligned = try block.addCmpVector(remainder, splat_zero_usize, .eq);23112 const is_aligned = try block.addCmpVector(remainder, splat_zero_usize, .eq);
...@@ -23129,8 +23135,14 @@ fn zirPtrFromInt(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!...@@ -23129,8 +23135,14 @@ fn zirPtrFromInt(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!
23129 }23135 }
23130 if (ptr_align.compare(.gt, .@"1")) {23136 if (ptr_align.compare(.gt, .@"1")) {
23131 const align_bytes_minus_1 = ptr_align.toByteUnits().? - 1;23137 const align_bytes_minus_1 = ptr_align.toByteUnits().? - 1;
23132 const align_minus_1 = Air.internedToRef((try pt.intValue(Type.usize, align_bytes_minus_1)).toIntern());23138 const align_mask = Air.internedToRef((try pt.intValue(
23133 const remainder = try block.addBinOp(.bit_and, elem_coerced, align_minus_1);23139 Type.usize,
23140 if (elem_ty.fnPtrMaskOrNull(zcu)) |mask|
23141 align_bytes_minus_1 & mask
23142 else
23143 align_bytes_minus_1,
23144 )).toIntern());
23145 const remainder = try block.addBinOp(.bit_and, elem_coerced, align_mask);
23134 const is_aligned = try block.addBinOp(.cmp_eq, remainder, .zero_usize);23146 const is_aligned = try block.addBinOp(.cmp_eq, remainder, .zero_usize);
23135 try sema.addSafetyCheck(block, src, is_aligned, .incorrect_alignment);23147 try sema.addSafetyCheck(block, src, is_aligned, .incorrect_alignment);
23136 }23148 }
...@@ -23710,13 +23722,19 @@ fn ptrCastFull(...@@ -23710,13 +23722,19 @@ fn ptrCastFull(
23710 try Type.fromInterned(dest_info.child).hasRuntimeBitsSema(pt))23722 try Type.fromInterned(dest_info.child).hasRuntimeBitsSema(pt))
23711 {23723 {
23712 const align_bytes_minus_1 = dest_align.toByteUnits().? - 1;23724 const align_bytes_minus_1 = dest_align.toByteUnits().? - 1;
23713 const align_minus_1 = Air.internedToRef((try pt.intValue(Type.usize, align_bytes_minus_1)).toIntern());23725 const align_mask = Air.internedToRef((try pt.intValue(
23726 Type.usize,
23727 if (Type.fromInterned(dest_info.child).fnPtrMaskOrNull(zcu)) |mask|
23728 align_bytes_minus_1 & mask
23729 else
23730 align_bytes_minus_1,
23731 )).toIntern());
23714 const actual_ptr = if (src_info.flags.size == .slice)23732 const actual_ptr = if (src_info.flags.size == .slice)
23715 try sema.analyzeSlicePtr(block, src, ptr, operand_ty)23733 try sema.analyzeSlicePtr(block, src, ptr, operand_ty)
23716 else23734 else
23717 ptr;23735 ptr;
23718 const ptr_int = try block.addBitCast(.usize, actual_ptr);23736 const ptr_int = try block.addBitCast(.usize, actual_ptr);
23719 const remainder = try block.addBinOp(.bit_and, ptr_int, align_minus_1);23737 const remainder = try block.addBinOp(.bit_and, ptr_int, align_mask);
23720 const is_aligned = try block.addBinOp(.cmp_eq, remainder, .zero_usize);23738 const is_aligned = try block.addBinOp(.cmp_eq, remainder, .zero_usize);
23721 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {23739 const ok = if (src_info.flags.size == .slice and dest_info.flags.size == .slice) ok: {
23722 const len = try sema.analyzeSliceLen(block, operand_src, ptr);23740 const len = try sema.analyzeSliceLen(block, operand_src, ptr);
src/Type.zig+7
...@@ -2541,6 +2541,13 @@ pub fn fnIsVarArgs(ty: Type, zcu: *const Zcu) bool {...@@ -2541,6 +2541,13 @@ pub fn fnIsVarArgs(ty: Type, zcu: *const Zcu) bool {
2541 return zcu.intern_pool.indexToKey(ty.toIntern()).func_type.is_var_args;2541 return zcu.intern_pool.indexToKey(ty.toIntern()).func_type.is_var_args;
2542}2542}
25432543
2544pub fn fnPtrMaskOrNull(ty: Type, zcu: *const Zcu) ?u64 {
2545 return switch (ty.zigTypeTag(zcu)) {
2546 .@"fn" => target_util.functionPointerMask(zcu.getTarget()),
2547 else => null,
2548 };
2549}
2550
2544pub fn isNumeric(ty: Type, zcu: *const Zcu) bool {2551pub fn isNumeric(ty: Type, zcu: *const Zcu) bool {
2545 return switch (ty.toIntern()) {2552 return switch (ty.toIntern()) {
2546 .f16_type,2553 .f16_type,
src/target.zig+11
...@@ -626,6 +626,17 @@ pub fn supportsFunctionAlignment(target: std.Target) bool {...@@ -626,6 +626,17 @@ pub fn supportsFunctionAlignment(target: std.Target) bool {
626 };626 };
627}627}
628628
629pub fn functionPointerMask(target: std.Target) ?u64 {
630 // 32-bit Arm uses the LSB to mean that the target function contains Thumb code.
631 // MIPS uses the LSB to mean that the target function contains MIPS16/microMIPS code.
632 return if (target.cpu.arch.isArm() or target.cpu.arch.isMIPS32())
633 ~@as(u32, 1)
634 else if (target.cpu.arch.isMIPS64())
635 ~@as(u64, 1)
636 else
637 null;
638}
639
629pub fn supportsTailCall(target: std.Target, backend: std.builtin.CompilerBackend) bool {640pub fn supportsTailCall(target: std.Target, backend: std.builtin.CompilerBackend) bool {
630 switch (backend) {641 switch (backend) {
631 .stage1, .stage2_llvm => return @import("codegen/llvm.zig").supportsTailCall(target),642 .stage1, .stage2_llvm => return @import("codegen/llvm.zig").supportsTailCall(target),
test/behavior/align.zig+11
...@@ -613,3 +613,14 @@ test "zero-bit fields in extern struct pad fields appropriately" {...@@ -613,3 +613,14 @@ test "zero-bit fields in extern struct pad fields appropriately" {
613 try expect(@intFromPtr(&s.y) == @intFromPtr(&s.a));613 try expect(@intFromPtr(&s.y) == @intFromPtr(&s.a));
614 try expect(@as(*S, @fieldParentPtr("a", &s.a)) == &s);614 try expect(@as(*S, @fieldParentPtr("a", &s.a)) == &s);
615}615}
616
617test "function pointer @intFromPtr/@ptrFromInt roundtrip" {
618 // This only succeeds on Thumb if we handle the Thumb bit correctly; if not, the `@ptrFromInt`
619 // will incorrectly trip an alignment safety check.
620
621 const nothing_ptr: *const fn () callconv(.c) void = &nothing;
622 const nothing_int: usize = @intFromPtr(nothing_ptr);
623 const nothing_ptr2: *const fn () callconv(.c) void = @ptrFromInt(nothing_int);
624
625 try std.testing.expectEqual(nothing_ptr, nothing_ptr2);
626}