| 1 | //===----------------------------------------------------------------------===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // Automatically generated file, do not edit! |
| 9 | //===----------------------------------------------------------------------===// |
| 10 | |
| 11 | |
| 12 | #ifndef _HVX_HEXAGON_PROTOS_H_ |
| 13 | #define _HVX_HEXAGON_PROTOS_H_ 1 |
| 14 | |
| 15 | #ifdef __HVX__ |
| 16 | #if __HVX_LENGTH__ == 128 |
| 17 | #define __BUILTIN_VECTOR_WRAP(a) a ## _128B |
| 18 | #else |
| 19 | #define __BUILTIN_VECTOR_WRAP(a) a |
| 20 | #endif |
| 21 | |
| 22 | /* ========================================================================== |
| 23 | Assembly Syntax: Rd32=vextract(Vu32,Rs32) |
| 24 | C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) |
| 25 | Instruction Type: LD |
| 26 | Execution Slots: SLOT0 |
| 27 | ========================================================================== */ |
| 28 | |
| 29 | #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) |
| 30 | |
| 31 | /* ========================================================================== |
| 32 | Assembly Syntax: Vd32=hi(Vss32) |
| 33 | C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) |
| 34 | Instruction Type: CVI_VA |
| 35 | Execution Slots: SLOT0123 |
| 36 | ========================================================================== */ |
| 37 | |
| 38 | #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) |
| 39 | |
| 40 | /* ========================================================================== |
| 41 | Assembly Syntax: Vd32=lo(Vss32) |
| 42 | C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) |
| 43 | Instruction Type: CVI_VA |
| 44 | Execution Slots: SLOT0123 |
| 45 | ========================================================================== */ |
| 46 | |
| 47 | #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) |
| 48 | |
| 49 | /* ========================================================================== |
| 50 | Assembly Syntax: Vd32=vsplat(Rt32) |
| 51 | C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) |
| 52 | Instruction Type: CVI_VX_LATE |
| 53 | Execution Slots: SLOT23 |
| 54 | ========================================================================== */ |
| 55 | |
| 56 | #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) |
| 57 | |
| 58 | /* ========================================================================== |
| 59 | Assembly Syntax: Qd4=and(Qs4,Qt4) |
| 60 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 61 | Instruction Type: CVI_VA_DV |
| 62 | Execution Slots: SLOT0123 |
| 63 | ========================================================================== */ |
| 64 | |
| 65 | #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 66 | |
| 67 | /* ========================================================================== |
| 68 | Assembly Syntax: Qd4=and(Qs4,!Qt4) |
| 69 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 70 | Instruction Type: CVI_VA_DV |
| 71 | Execution Slots: SLOT0123 |
| 72 | ========================================================================== */ |
| 73 | |
| 74 | #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 75 | |
| 76 | /* ========================================================================== |
| 77 | Assembly Syntax: Qd4=not(Qs4) |
| 78 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) |
| 79 | Instruction Type: CVI_VA |
| 80 | Execution Slots: SLOT0123 |
| 81 | ========================================================================== */ |
| 82 | |
| 83 | #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) |
| 84 | |
| 85 | /* ========================================================================== |
| 86 | Assembly Syntax: Qd4=or(Qs4,Qt4) |
| 87 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 88 | Instruction Type: CVI_VA_DV |
| 89 | Execution Slots: SLOT0123 |
| 90 | ========================================================================== */ |
| 91 | |
| 92 | #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 93 | |
| 94 | /* ========================================================================== |
| 95 | Assembly Syntax: Qd4=or(Qs4,!Qt4) |
| 96 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 97 | Instruction Type: CVI_VA_DV |
| 98 | Execution Slots: SLOT0123 |
| 99 | ========================================================================== */ |
| 100 | |
| 101 | #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 102 | |
| 103 | /* ========================================================================== |
| 104 | Assembly Syntax: Qd4=vsetq(Rt32) |
| 105 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) |
| 106 | Instruction Type: CVI_VP |
| 107 | Execution Slots: SLOT0123 |
| 108 | ========================================================================== */ |
| 109 | |
| 110 | #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) |
| 111 | |
| 112 | /* ========================================================================== |
| 113 | Assembly Syntax: Qd4=xor(Qs4,Qt4) |
| 114 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 115 | Instruction Type: CVI_VA_DV |
| 116 | Execution Slots: SLOT0123 |
| 117 | ========================================================================== */ |
| 118 | |
| 119 | #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 120 | |
| 121 | /* ========================================================================== |
| 122 | Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 |
| 123 | C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 124 | Instruction Type: CVI_VM_ST |
| 125 | Execution Slots: SLOT0 |
| 126 | ========================================================================== */ |
| 127 | |
| 128 | #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
| 129 | |
| 130 | /* ========================================================================== |
| 131 | Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 |
| 132 | C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 133 | Instruction Type: CVI_VM_ST |
| 134 | Execution Slots: SLOT0 |
| 135 | ========================================================================== */ |
| 136 | |
| 137 | #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
| 138 | |
| 139 | /* ========================================================================== |
| 140 | Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 |
| 141 | C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 142 | Instruction Type: CVI_VM_ST |
| 143 | Execution Slots: SLOT0 |
| 144 | ========================================================================== */ |
| 145 | |
| 146 | #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
| 147 | |
| 148 | /* ========================================================================== |
| 149 | Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 |
| 150 | C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 151 | Instruction Type: CVI_VM_ST |
| 152 | Execution Slots: SLOT0 |
| 153 | ========================================================================== */ |
| 154 | |
| 155 | #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
| 156 | |
| 157 | /* ========================================================================== |
| 158 | Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) |
| 159 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 160 | Instruction Type: CVI_VX |
| 161 | Execution Slots: SLOT23 |
| 162 | ========================================================================== */ |
| 163 | |
| 164 | #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) |
| 165 | |
| 166 | /* ========================================================================== |
| 167 | Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) |
| 168 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 169 | Instruction Type: CVI_VX |
| 170 | Execution Slots: SLOT23 |
| 171 | ========================================================================== */ |
| 172 | |
| 173 | #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) |
| 174 | |
| 175 | /* ========================================================================== |
| 176 | Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) |
| 177 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 178 | Instruction Type: CVI_VX |
| 179 | Execution Slots: SLOT23 |
| 180 | ========================================================================== */ |
| 181 | |
| 182 | #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) |
| 183 | |
| 184 | /* ========================================================================== |
| 185 | Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) |
| 186 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 187 | Instruction Type: CVI_VX |
| 188 | Execution Slots: SLOT23 |
| 189 | ========================================================================== */ |
| 190 | |
| 191 | #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) |
| 192 | |
| 193 | /* ========================================================================== |
| 194 | Assembly Syntax: Vd32.h=vabs(Vu32.h) |
| 195 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) |
| 196 | Instruction Type: CVI_VA |
| 197 | Execution Slots: SLOT0123 |
| 198 | ========================================================================== */ |
| 199 | |
| 200 | #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) |
| 201 | |
| 202 | /* ========================================================================== |
| 203 | Assembly Syntax: Vd32.h=vabs(Vu32.h):sat |
| 204 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) |
| 205 | Instruction Type: CVI_VA |
| 206 | Execution Slots: SLOT0123 |
| 207 | ========================================================================== */ |
| 208 | |
| 209 | #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) |
| 210 | |
| 211 | /* ========================================================================== |
| 212 | Assembly Syntax: Vd32.w=vabs(Vu32.w) |
| 213 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) |
| 214 | Instruction Type: CVI_VA |
| 215 | Execution Slots: SLOT0123 |
| 216 | ========================================================================== */ |
| 217 | |
| 218 | #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) |
| 219 | |
| 220 | /* ========================================================================== |
| 221 | Assembly Syntax: Vd32.w=vabs(Vu32.w):sat |
| 222 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) |
| 223 | Instruction Type: CVI_VA |
| 224 | Execution Slots: SLOT0123 |
| 225 | ========================================================================== */ |
| 226 | |
| 227 | #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) |
| 228 | |
| 229 | /* ========================================================================== |
| 230 | Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) |
| 231 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 232 | Instruction Type: CVI_VA |
| 233 | Execution Slots: SLOT0123 |
| 234 | ========================================================================== */ |
| 235 | |
| 236 | #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) |
| 237 | |
| 238 | /* ========================================================================== |
| 239 | Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) |
| 240 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 241 | Instruction Type: CVI_VA_DV |
| 242 | Execution Slots: SLOT0123 |
| 243 | ========================================================================== */ |
| 244 | |
| 245 | #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) |
| 246 | |
| 247 | /* ========================================================================== |
| 248 | Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b |
| 249 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 250 | Instruction Type: CVI_VA |
| 251 | Execution Slots: SLOT0123 |
| 252 | ========================================================================== */ |
| 253 | |
| 254 | #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 255 | |
| 256 | /* ========================================================================== |
| 257 | Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b |
| 258 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 259 | Instruction Type: CVI_VA |
| 260 | Execution Slots: SLOT0123 |
| 261 | ========================================================================== */ |
| 262 | |
| 263 | #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 264 | |
| 265 | /* ========================================================================== |
| 266 | Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) |
| 267 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 268 | Instruction Type: CVI_VA |
| 269 | Execution Slots: SLOT0123 |
| 270 | ========================================================================== */ |
| 271 | |
| 272 | #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) |
| 273 | |
| 274 | /* ========================================================================== |
| 275 | Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) |
| 276 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 277 | Instruction Type: CVI_VA_DV |
| 278 | Execution Slots: SLOT0123 |
| 279 | ========================================================================== */ |
| 280 | |
| 281 | #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) |
| 282 | |
| 283 | /* ========================================================================== |
| 284 | Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h |
| 285 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 286 | Instruction Type: CVI_VA |
| 287 | Execution Slots: SLOT0123 |
| 288 | ========================================================================== */ |
| 289 | |
| 290 | #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 291 | |
| 292 | /* ========================================================================== |
| 293 | Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h |
| 294 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 295 | Instruction Type: CVI_VA |
| 296 | Execution Slots: SLOT0123 |
| 297 | ========================================================================== */ |
| 298 | |
| 299 | #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 300 | |
| 301 | /* ========================================================================== |
| 302 | Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat |
| 303 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 304 | Instruction Type: CVI_VA |
| 305 | Execution Slots: SLOT0123 |
| 306 | ========================================================================== */ |
| 307 | |
| 308 | #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) |
| 309 | |
| 310 | /* ========================================================================== |
| 311 | Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat |
| 312 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 313 | Instruction Type: CVI_VA_DV |
| 314 | Execution Slots: SLOT0123 |
| 315 | ========================================================================== */ |
| 316 | |
| 317 | #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) |
| 318 | |
| 319 | /* ========================================================================== |
| 320 | Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) |
| 321 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 322 | Instruction Type: CVI_VX_DV |
| 323 | Execution Slots: SLOT23 |
| 324 | ========================================================================== */ |
| 325 | |
| 326 | #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) |
| 327 | |
| 328 | /* ========================================================================== |
| 329 | Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) |
| 330 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 331 | Instruction Type: CVI_VX_DV |
| 332 | Execution Slots: SLOT23 |
| 333 | ========================================================================== */ |
| 334 | |
| 335 | #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) |
| 336 | |
| 337 | /* ========================================================================== |
| 338 | Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat |
| 339 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 340 | Instruction Type: CVI_VA |
| 341 | Execution Slots: SLOT0123 |
| 342 | ========================================================================== */ |
| 343 | |
| 344 | #define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) |
| 345 | |
| 346 | /* ========================================================================== |
| 347 | Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat |
| 348 | C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 349 | Instruction Type: CVI_VA_DV |
| 350 | Execution Slots: SLOT0123 |
| 351 | ========================================================================== */ |
| 352 | |
| 353 | #define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) |
| 354 | |
| 355 | /* ========================================================================== |
| 356 | Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat |
| 357 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 358 | Instruction Type: CVI_VA |
| 359 | Execution Slots: SLOT0123 |
| 360 | ========================================================================== */ |
| 361 | |
| 362 | #define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) |
| 363 | |
| 364 | /* ========================================================================== |
| 365 | Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat |
| 366 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 367 | Instruction Type: CVI_VA_DV |
| 368 | Execution Slots: SLOT0123 |
| 369 | ========================================================================== */ |
| 370 | |
| 371 | #define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) |
| 372 | |
| 373 | /* ========================================================================== |
| 374 | Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) |
| 375 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 376 | Instruction Type: CVI_VX_DV |
| 377 | Execution Slots: SLOT23 |
| 378 | ========================================================================== */ |
| 379 | |
| 380 | #define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) |
| 381 | |
| 382 | /* ========================================================================== |
| 383 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) |
| 384 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 385 | Instruction Type: CVI_VA |
| 386 | Execution Slots: SLOT0123 |
| 387 | ========================================================================== */ |
| 388 | |
| 389 | #define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) |
| 390 | |
| 391 | /* ========================================================================== |
| 392 | Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) |
| 393 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 394 | Instruction Type: CVI_VA_DV |
| 395 | Execution Slots: SLOT0123 |
| 396 | ========================================================================== */ |
| 397 | |
| 398 | #define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) |
| 399 | |
| 400 | /* ========================================================================== |
| 401 | Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w |
| 402 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 403 | Instruction Type: CVI_VA |
| 404 | Execution Slots: SLOT0123 |
| 405 | ========================================================================== */ |
| 406 | |
| 407 | #define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 408 | |
| 409 | /* ========================================================================== |
| 410 | Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w |
| 411 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 412 | Instruction Type: CVI_VA |
| 413 | Execution Slots: SLOT0123 |
| 414 | ========================================================================== */ |
| 415 | |
| 416 | #define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 417 | |
| 418 | /* ========================================================================== |
| 419 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat |
| 420 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 421 | Instruction Type: CVI_VA |
| 422 | Execution Slots: SLOT0123 |
| 423 | ========================================================================== */ |
| 424 | |
| 425 | #define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) |
| 426 | |
| 427 | /* ========================================================================== |
| 428 | Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat |
| 429 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 430 | Instruction Type: CVI_VA_DV |
| 431 | Execution Slots: SLOT0123 |
| 432 | ========================================================================== */ |
| 433 | |
| 434 | #define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) |
| 435 | |
| 436 | /* ========================================================================== |
| 437 | Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) |
| 438 | C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 439 | Instruction Type: CVI_VP |
| 440 | Execution Slots: SLOT0123 |
| 441 | ========================================================================== */ |
| 442 | |
| 443 | #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) |
| 444 | |
| 445 | /* ========================================================================== |
| 446 | Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) |
| 447 | C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 448 | Instruction Type: CVI_VP |
| 449 | Execution Slots: SLOT0123 |
| 450 | ========================================================================== */ |
| 451 | |
| 452 | #define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) |
| 453 | |
| 454 | /* ========================================================================== |
| 455 | Assembly Syntax: Vd32=vand(Vu32,Vv32) |
| 456 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 457 | Instruction Type: CVI_VA |
| 458 | Execution Slots: SLOT0123 |
| 459 | ========================================================================== */ |
| 460 | |
| 461 | #define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) |
| 462 | |
| 463 | /* ========================================================================== |
| 464 | Assembly Syntax: Vd32=vand(Qu4,Rt32) |
| 465 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) |
| 466 | Instruction Type: CVI_VX_LATE |
| 467 | Execution Slots: SLOT23 |
| 468 | ========================================================================== */ |
| 469 | |
| 470 | #define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
| 471 | |
| 472 | /* ========================================================================== |
| 473 | Assembly Syntax: Vx32|=vand(Qu4,Rt32) |
| 474 | C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) |
| 475 | Instruction Type: CVI_VX_LATE |
| 476 | Execution Slots: SLOT23 |
| 477 | ========================================================================== */ |
| 478 | |
| 479 | #define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
| 480 | |
| 481 | /* ========================================================================== |
| 482 | Assembly Syntax: Qd4=vand(Vu32,Rt32) |
| 483 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) |
| 484 | Instruction Type: CVI_VX_LATE |
| 485 | Execution Slots: SLOT23 |
| 486 | ========================================================================== */ |
| 487 | |
| 488 | #define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) |
| 489 | |
| 490 | /* ========================================================================== |
| 491 | Assembly Syntax: Qx4|=vand(Vu32,Rt32) |
| 492 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) |
| 493 | Instruction Type: CVI_VX_LATE |
| 494 | Execution Slots: SLOT23 |
| 495 | ========================================================================== */ |
| 496 | |
| 497 | #define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) |
| 498 | |
| 499 | /* ========================================================================== |
| 500 | Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) |
| 501 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) |
| 502 | Instruction Type: CVI_VS |
| 503 | Execution Slots: SLOT0123 |
| 504 | ========================================================================== */ |
| 505 | |
| 506 | #define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) |
| 507 | |
| 508 | /* ========================================================================== |
| 509 | Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) |
| 510 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 511 | Instruction Type: CVI_VS |
| 512 | Execution Slots: SLOT0123 |
| 513 | ========================================================================== */ |
| 514 | |
| 515 | #define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) |
| 516 | |
| 517 | /* ========================================================================== |
| 518 | Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) |
| 519 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) |
| 520 | Instruction Type: CVI_VS |
| 521 | Execution Slots: SLOT0123 |
| 522 | ========================================================================== */ |
| 523 | |
| 524 | #define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) |
| 525 | |
| 526 | /* ========================================================================== |
| 527 | Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) |
| 528 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 529 | Instruction Type: CVI_VS |
| 530 | Execution Slots: SLOT0123 |
| 531 | ========================================================================== */ |
| 532 | |
| 533 | #define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) |
| 534 | |
| 535 | /* ========================================================================== |
| 536 | Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) |
| 537 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 538 | Instruction Type: CVI_VS |
| 539 | Execution Slots: SLOT0123 |
| 540 | ========================================================================== */ |
| 541 | |
| 542 | #define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) |
| 543 | |
| 544 | /* ========================================================================== |
| 545 | Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) |
| 546 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) |
| 547 | Instruction Type: CVI_VS |
| 548 | Execution Slots: SLOT0123 |
| 549 | ========================================================================== */ |
| 550 | |
| 551 | #define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) |
| 552 | |
| 553 | /* ========================================================================== |
| 554 | Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat |
| 555 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 556 | Instruction Type: CVI_VS |
| 557 | Execution Slots: SLOT0123 |
| 558 | ========================================================================== */ |
| 559 | |
| 560 | #define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) |
| 561 | |
| 562 | /* ========================================================================== |
| 563 | Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat |
| 564 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 565 | Instruction Type: CVI_VS |
| 566 | Execution Slots: SLOT0123 |
| 567 | ========================================================================== */ |
| 568 | |
| 569 | #define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) |
| 570 | |
| 571 | /* ========================================================================== |
| 572 | Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat |
| 573 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 574 | Instruction Type: CVI_VS |
| 575 | Execution Slots: SLOT0123 |
| 576 | ========================================================================== */ |
| 577 | |
| 578 | #define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) |
| 579 | |
| 580 | /* ========================================================================== |
| 581 | Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) |
| 582 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 583 | Instruction Type: CVI_VS |
| 584 | Execution Slots: SLOT0123 |
| 585 | ========================================================================== */ |
| 586 | |
| 587 | #define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) |
| 588 | |
| 589 | /* ========================================================================== |
| 590 | Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) |
| 591 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) |
| 592 | Instruction Type: CVI_VS |
| 593 | Execution Slots: SLOT0123 |
| 594 | ========================================================================== */ |
| 595 | |
| 596 | #define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) |
| 597 | |
| 598 | /* ========================================================================== |
| 599 | Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) |
| 600 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 601 | Instruction Type: CVI_VS |
| 602 | Execution Slots: SLOT0123 |
| 603 | ========================================================================== */ |
| 604 | |
| 605 | #define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) |
| 606 | |
| 607 | /* ========================================================================== |
| 608 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) |
| 609 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 610 | Instruction Type: CVI_VS |
| 611 | Execution Slots: SLOT0123 |
| 612 | ========================================================================== */ |
| 613 | |
| 614 | #define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) |
| 615 | |
| 616 | /* ========================================================================== |
| 617 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat |
| 618 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 619 | Instruction Type: CVI_VS |
| 620 | Execution Slots: SLOT0123 |
| 621 | ========================================================================== */ |
| 622 | |
| 623 | #define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) |
| 624 | |
| 625 | /* ========================================================================== |
| 626 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat |
| 627 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 628 | Instruction Type: CVI_VS |
| 629 | Execution Slots: SLOT0123 |
| 630 | ========================================================================== */ |
| 631 | |
| 632 | #define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) |
| 633 | |
| 634 | /* ========================================================================== |
| 635 | Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat |
| 636 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 637 | Instruction Type: CVI_VS |
| 638 | Execution Slots: SLOT0123 |
| 639 | ========================================================================== */ |
| 640 | |
| 641 | #define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) |
| 642 | |
| 643 | /* ========================================================================== |
| 644 | Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) |
| 645 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 646 | Instruction Type: CVI_VS |
| 647 | Execution Slots: SLOT0123 |
| 648 | ========================================================================== */ |
| 649 | |
| 650 | #define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) |
| 651 | |
| 652 | /* ========================================================================== |
| 653 | Assembly Syntax: Vd32=Vu32 |
| 654 | C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) |
| 655 | Instruction Type: CVI_VA |
| 656 | Execution Slots: SLOT0123 |
| 657 | ========================================================================== */ |
| 658 | |
| 659 | #define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) |
| 660 | |
| 661 | /* ========================================================================== |
| 662 | Assembly Syntax: Vdd32=Vuu32 |
| 663 | C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) |
| 664 | Instruction Type: CVI_VA_DV |
| 665 | Execution Slots: SLOT0123 |
| 666 | ========================================================================== */ |
| 667 | |
| 668 | #define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) |
| 669 | |
| 670 | /* ========================================================================== |
| 671 | Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) |
| 672 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 673 | Instruction Type: CVI_VA |
| 674 | Execution Slots: SLOT0123 |
| 675 | ========================================================================== */ |
| 676 | |
| 677 | #define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) |
| 678 | |
| 679 | /* ========================================================================== |
| 680 | Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd |
| 681 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 682 | Instruction Type: CVI_VA |
| 683 | Execution Slots: SLOT0123 |
| 684 | ========================================================================== */ |
| 685 | |
| 686 | #define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) |
| 687 | |
| 688 | /* ========================================================================== |
| 689 | Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) |
| 690 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 691 | Instruction Type: CVI_VA |
| 692 | Execution Slots: SLOT0123 |
| 693 | ========================================================================== */ |
| 694 | |
| 695 | #define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) |
| 696 | |
| 697 | /* ========================================================================== |
| 698 | Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd |
| 699 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 700 | Instruction Type: CVI_VA |
| 701 | Execution Slots: SLOT0123 |
| 702 | ========================================================================== */ |
| 703 | |
| 704 | #define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) |
| 705 | |
| 706 | /* ========================================================================== |
| 707 | Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) |
| 708 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 709 | Instruction Type: CVI_VA |
| 710 | Execution Slots: SLOT0123 |
| 711 | ========================================================================== */ |
| 712 | |
| 713 | #define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) |
| 714 | |
| 715 | /* ========================================================================== |
| 716 | Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd |
| 717 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 718 | Instruction Type: CVI_VA |
| 719 | Execution Slots: SLOT0123 |
| 720 | ========================================================================== */ |
| 721 | |
| 722 | #define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) |
| 723 | |
| 724 | /* ========================================================================== |
| 725 | Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) |
| 726 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 727 | Instruction Type: CVI_VA |
| 728 | Execution Slots: SLOT0123 |
| 729 | ========================================================================== */ |
| 730 | |
| 731 | #define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) |
| 732 | |
| 733 | /* ========================================================================== |
| 734 | Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd |
| 735 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 736 | Instruction Type: CVI_VA |
| 737 | Execution Slots: SLOT0123 |
| 738 | ========================================================================== */ |
| 739 | |
| 740 | #define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) |
| 741 | |
| 742 | /* ========================================================================== |
| 743 | Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) |
| 744 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) |
| 745 | Instruction Type: CVI_VS |
| 746 | Execution Slots: SLOT0123 |
| 747 | ========================================================================== */ |
| 748 | |
| 749 | #define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) |
| 750 | |
| 751 | /* ========================================================================== |
| 752 | Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) |
| 753 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) |
| 754 | Instruction Type: CVI_VS |
| 755 | Execution Slots: SLOT0123 |
| 756 | ========================================================================== */ |
| 757 | |
| 758 | #define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) |
| 759 | |
| 760 | /* ========================================================================== |
| 761 | Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) |
| 762 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 763 | Instruction Type: CVI_VA_DV |
| 764 | Execution Slots: SLOT0123 |
| 765 | ========================================================================== */ |
| 766 | |
| 767 | #define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) |
| 768 | |
| 769 | /* ========================================================================== |
| 770 | Assembly Syntax: Vd32=#0 |
| 771 | C Intrinsic Prototype: HVX_Vector Q6_V_vzero() |
| 772 | Instruction Type: CVI_VA |
| 773 | Execution Slots: SLOT0123 |
| 774 | ========================================================================== */ |
| 775 | |
| 776 | #define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() |
| 777 | |
| 778 | /* ========================================================================== |
| 779 | Assembly Syntax: Vd32.b=vdeal(Vu32.b) |
| 780 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) |
| 781 | Instruction Type: CVI_VP |
| 782 | Execution Slots: SLOT0123 |
| 783 | ========================================================================== */ |
| 784 | |
| 785 | #define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) |
| 786 | |
| 787 | /* ========================================================================== |
| 788 | Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) |
| 789 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 790 | Instruction Type: CVI_VP |
| 791 | Execution Slots: SLOT0123 |
| 792 | ========================================================================== */ |
| 793 | |
| 794 | #define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) |
| 795 | |
| 796 | /* ========================================================================== |
| 797 | Assembly Syntax: Vd32.h=vdeal(Vu32.h) |
| 798 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) |
| 799 | Instruction Type: CVI_VP |
| 800 | Execution Slots: SLOT0123 |
| 801 | ========================================================================== */ |
| 802 | |
| 803 | #define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) |
| 804 | |
| 805 | /* ========================================================================== |
| 806 | Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) |
| 807 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 808 | Instruction Type: CVI_VP_VS |
| 809 | Execution Slots: SLOT0123 |
| 810 | ========================================================================== */ |
| 811 | |
| 812 | #define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) |
| 813 | |
| 814 | /* ========================================================================== |
| 815 | Assembly Syntax: Vd32=vdelta(Vu32,Vv32) |
| 816 | C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 817 | Instruction Type: CVI_VP |
| 818 | Execution Slots: SLOT0123 |
| 819 | ========================================================================== */ |
| 820 | |
| 821 | #define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) |
| 822 | |
| 823 | /* ========================================================================== |
| 824 | Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) |
| 825 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
| 826 | Instruction Type: CVI_VX |
| 827 | Execution Slots: SLOT23 |
| 828 | ========================================================================== */ |
| 829 | |
| 830 | #define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) |
| 831 | |
| 832 | /* ========================================================================== |
| 833 | Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) |
| 834 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 835 | Instruction Type: CVI_VX |
| 836 | Execution Slots: SLOT23 |
| 837 | ========================================================================== */ |
| 838 | |
| 839 | #define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) |
| 840 | |
| 841 | /* ========================================================================== |
| 842 | Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) |
| 843 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
| 844 | Instruction Type: CVI_VX_DV |
| 845 | Execution Slots: SLOT23 |
| 846 | ========================================================================== */ |
| 847 | |
| 848 | #define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) |
| 849 | |
| 850 | /* ========================================================================== |
| 851 | Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) |
| 852 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 853 | Instruction Type: CVI_VX_DV |
| 854 | Execution Slots: SLOT23 |
| 855 | ========================================================================== */ |
| 856 | |
| 857 | #define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) |
| 858 | |
| 859 | /* ========================================================================== |
| 860 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) |
| 861 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) |
| 862 | Instruction Type: CVI_VX |
| 863 | Execution Slots: SLOT23 |
| 864 | ========================================================================== */ |
| 865 | |
| 866 | #define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) |
| 867 | |
| 868 | /* ========================================================================== |
| 869 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) |
| 870 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 871 | Instruction Type: CVI_VX |
| 872 | Execution Slots: SLOT23 |
| 873 | ========================================================================== */ |
| 874 | |
| 875 | #define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) |
| 876 | |
| 877 | /* ========================================================================== |
| 878 | Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) |
| 879 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 880 | Instruction Type: CVI_VX_DV |
| 881 | Execution Slots: SLOT23 |
| 882 | ========================================================================== */ |
| 883 | |
| 884 | #define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) |
| 885 | |
| 886 | /* ========================================================================== |
| 887 | Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) |
| 888 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 889 | Instruction Type: CVI_VX_DV |
| 890 | Execution Slots: SLOT23 |
| 891 | ========================================================================== */ |
| 892 | |
| 893 | #define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) |
| 894 | |
| 895 | /* ========================================================================== |
| 896 | Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat |
| 897 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) |
| 898 | Instruction Type: CVI_VX_DV |
| 899 | Execution Slots: SLOT23 |
| 900 | ========================================================================== */ |
| 901 | |
| 902 | #define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) |
| 903 | |
| 904 | /* ========================================================================== |
| 905 | Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat |
| 906 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) |
| 907 | Instruction Type: CVI_VX_DV |
| 908 | Execution Slots: SLOT23 |
| 909 | ========================================================================== */ |
| 910 | |
| 911 | #define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) |
| 912 | |
| 913 | /* ========================================================================== |
| 914 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat |
| 915 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) |
| 916 | Instruction Type: CVI_VX |
| 917 | Execution Slots: SLOT23 |
| 918 | ========================================================================== */ |
| 919 | |
| 920 | #define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) |
| 921 | |
| 922 | /* ========================================================================== |
| 923 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat |
| 924 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 925 | Instruction Type: CVI_VX |
| 926 | Execution Slots: SLOT23 |
| 927 | ========================================================================== */ |
| 928 | |
| 929 | #define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) |
| 930 | |
| 931 | /* ========================================================================== |
| 932 | Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat |
| 933 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) |
| 934 | Instruction Type: CVI_VX_DV |
| 935 | Execution Slots: SLOT23 |
| 936 | ========================================================================== */ |
| 937 | |
| 938 | #define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) |
| 939 | |
| 940 | /* ========================================================================== |
| 941 | Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat |
| 942 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) |
| 943 | Instruction Type: CVI_VX_DV |
| 944 | Execution Slots: SLOT23 |
| 945 | ========================================================================== */ |
| 946 | |
| 947 | #define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) |
| 948 | |
| 949 | /* ========================================================================== |
| 950 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat |
| 951 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) |
| 952 | Instruction Type: CVI_VX |
| 953 | Execution Slots: SLOT23 |
| 954 | ========================================================================== */ |
| 955 | |
| 956 | #define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) |
| 957 | |
| 958 | /* ========================================================================== |
| 959 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat |
| 960 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 961 | Instruction Type: CVI_VX |
| 962 | Execution Slots: SLOT23 |
| 963 | ========================================================================== */ |
| 964 | |
| 965 | #define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) |
| 966 | |
| 967 | /* ========================================================================== |
| 968 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat |
| 969 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 970 | Instruction Type: CVI_VX |
| 971 | Execution Slots: SLOT23 |
| 972 | ========================================================================== */ |
| 973 | |
| 974 | #define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) |
| 975 | |
| 976 | /* ========================================================================== |
| 977 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat |
| 978 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 979 | Instruction Type: CVI_VX_DV |
| 980 | Execution Slots: SLOT23 |
| 981 | ========================================================================== */ |
| 982 | |
| 983 | #define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) |
| 984 | |
| 985 | /* ========================================================================== |
| 986 | Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) |
| 987 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) |
| 988 | Instruction Type: CVI_VX_DV |
| 989 | Execution Slots: SLOT23 |
| 990 | ========================================================================== */ |
| 991 | |
| 992 | #define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) |
| 993 | |
| 994 | /* ========================================================================== |
| 995 | Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) |
| 996 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 997 | Instruction Type: CVI_VX_DV |
| 998 | Execution Slots: SLOT23 |
| 999 | ========================================================================== */ |
| 1000 | |
| 1001 | #define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) |
| 1002 | |
| 1003 | /* ========================================================================== |
| 1004 | Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) |
| 1005 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1006 | Instruction Type: CVI_VA |
| 1007 | Execution Slots: SLOT0123 |
| 1008 | ========================================================================== */ |
| 1009 | |
| 1010 | #define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) |
| 1011 | |
| 1012 | /* ========================================================================== |
| 1013 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) |
| 1014 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1015 | Instruction Type: CVI_VA |
| 1016 | Execution Slots: SLOT0123 |
| 1017 | ========================================================================== */ |
| 1018 | |
| 1019 | #define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1020 | |
| 1021 | /* ========================================================================== |
| 1022 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) |
| 1023 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1024 | Instruction Type: CVI_VA |
| 1025 | Execution Slots: SLOT0123 |
| 1026 | ========================================================================== */ |
| 1027 | |
| 1028 | #define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1029 | |
| 1030 | /* ========================================================================== |
| 1031 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) |
| 1032 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1033 | Instruction Type: CVI_VA |
| 1034 | Execution Slots: SLOT0123 |
| 1035 | ========================================================================== */ |
| 1036 | |
| 1037 | #define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1038 | |
| 1039 | /* ========================================================================== |
| 1040 | Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) |
| 1041 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1042 | Instruction Type: CVI_VA |
| 1043 | Execution Slots: SLOT0123 |
| 1044 | ========================================================================== */ |
| 1045 | |
| 1046 | #define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) |
| 1047 | |
| 1048 | /* ========================================================================== |
| 1049 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) |
| 1050 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1051 | Instruction Type: CVI_VA |
| 1052 | Execution Slots: SLOT0123 |
| 1053 | ========================================================================== */ |
| 1054 | |
| 1055 | #define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1056 | |
| 1057 | /* ========================================================================== |
| 1058 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) |
| 1059 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1060 | Instruction Type: CVI_VA |
| 1061 | Execution Slots: SLOT0123 |
| 1062 | ========================================================================== */ |
| 1063 | |
| 1064 | #define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1065 | |
| 1066 | /* ========================================================================== |
| 1067 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) |
| 1068 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1069 | Instruction Type: CVI_VA |
| 1070 | Execution Slots: SLOT0123 |
| 1071 | ========================================================================== */ |
| 1072 | |
| 1073 | #define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1074 | |
| 1075 | /* ========================================================================== |
| 1076 | Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) |
| 1077 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1078 | Instruction Type: CVI_VA |
| 1079 | Execution Slots: SLOT0123 |
| 1080 | ========================================================================== */ |
| 1081 | |
| 1082 | #define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) |
| 1083 | |
| 1084 | /* ========================================================================== |
| 1085 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) |
| 1086 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1087 | Instruction Type: CVI_VA |
| 1088 | Execution Slots: SLOT0123 |
| 1089 | ========================================================================== */ |
| 1090 | |
| 1091 | #define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1092 | |
| 1093 | /* ========================================================================== |
| 1094 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) |
| 1095 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1096 | Instruction Type: CVI_VA |
| 1097 | Execution Slots: SLOT0123 |
| 1098 | ========================================================================== */ |
| 1099 | |
| 1100 | #define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1101 | |
| 1102 | /* ========================================================================== |
| 1103 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) |
| 1104 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1105 | Instruction Type: CVI_VA |
| 1106 | Execution Slots: SLOT0123 |
| 1107 | ========================================================================== */ |
| 1108 | |
| 1109 | #define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1110 | |
| 1111 | /* ========================================================================== |
| 1112 | Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) |
| 1113 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1114 | Instruction Type: CVI_VA |
| 1115 | Execution Slots: SLOT0123 |
| 1116 | ========================================================================== */ |
| 1117 | |
| 1118 | #define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) |
| 1119 | |
| 1120 | /* ========================================================================== |
| 1121 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) |
| 1122 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1123 | Instruction Type: CVI_VA |
| 1124 | Execution Slots: SLOT0123 |
| 1125 | ========================================================================== */ |
| 1126 | |
| 1127 | #define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1128 | |
| 1129 | /* ========================================================================== |
| 1130 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) |
| 1131 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1132 | Instruction Type: CVI_VA |
| 1133 | Execution Slots: SLOT0123 |
| 1134 | ========================================================================== */ |
| 1135 | |
| 1136 | #define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1137 | |
| 1138 | /* ========================================================================== |
| 1139 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) |
| 1140 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1141 | Instruction Type: CVI_VA |
| 1142 | Execution Slots: SLOT0123 |
| 1143 | ========================================================================== */ |
| 1144 | |
| 1145 | #define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1146 | |
| 1147 | /* ========================================================================== |
| 1148 | Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) |
| 1149 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1150 | Instruction Type: CVI_VA |
| 1151 | Execution Slots: SLOT0123 |
| 1152 | ========================================================================== */ |
| 1153 | |
| 1154 | #define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) |
| 1155 | |
| 1156 | /* ========================================================================== |
| 1157 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) |
| 1158 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1159 | Instruction Type: CVI_VA |
| 1160 | Execution Slots: SLOT0123 |
| 1161 | ========================================================================== */ |
| 1162 | |
| 1163 | #define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1164 | |
| 1165 | /* ========================================================================== |
| 1166 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) |
| 1167 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1168 | Instruction Type: CVI_VA |
| 1169 | Execution Slots: SLOT0123 |
| 1170 | ========================================================================== */ |
| 1171 | |
| 1172 | #define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1173 | |
| 1174 | /* ========================================================================== |
| 1175 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) |
| 1176 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1177 | Instruction Type: CVI_VA |
| 1178 | Execution Slots: SLOT0123 |
| 1179 | ========================================================================== */ |
| 1180 | |
| 1181 | #define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1182 | |
| 1183 | /* ========================================================================== |
| 1184 | Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1185 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1186 | Instruction Type: CVI_VA |
| 1187 | Execution Slots: SLOT0123 |
| 1188 | ========================================================================== */ |
| 1189 | |
| 1190 | #define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) |
| 1191 | |
| 1192 | /* ========================================================================== |
| 1193 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1194 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1195 | Instruction Type: CVI_VA |
| 1196 | Execution Slots: SLOT0123 |
| 1197 | ========================================================================== */ |
| 1198 | |
| 1199 | #define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1200 | |
| 1201 | /* ========================================================================== |
| 1202 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1203 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1204 | Instruction Type: CVI_VA |
| 1205 | Execution Slots: SLOT0123 |
| 1206 | ========================================================================== */ |
| 1207 | |
| 1208 | #define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1209 | |
| 1210 | /* ========================================================================== |
| 1211 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1212 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1213 | Instruction Type: CVI_VA |
| 1214 | Execution Slots: SLOT0123 |
| 1215 | ========================================================================== */ |
| 1216 | |
| 1217 | #define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1218 | |
| 1219 | /* ========================================================================== |
| 1220 | Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1221 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1222 | Instruction Type: CVI_VA |
| 1223 | Execution Slots: SLOT0123 |
| 1224 | ========================================================================== */ |
| 1225 | |
| 1226 | #define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) |
| 1227 | |
| 1228 | /* ========================================================================== |
| 1229 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1230 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1231 | Instruction Type: CVI_VA |
| 1232 | Execution Slots: SLOT0123 |
| 1233 | ========================================================================== */ |
| 1234 | |
| 1235 | #define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1236 | |
| 1237 | /* ========================================================================== |
| 1238 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1239 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1240 | Instruction Type: CVI_VA |
| 1241 | Execution Slots: SLOT0123 |
| 1242 | ========================================================================== */ |
| 1243 | |
| 1244 | #define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1245 | |
| 1246 | /* ========================================================================== |
| 1247 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1248 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1249 | Instruction Type: CVI_VA |
| 1250 | Execution Slots: SLOT0123 |
| 1251 | ========================================================================== */ |
| 1252 | |
| 1253 | #define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1254 | |
| 1255 | /* ========================================================================== |
| 1256 | Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1257 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 1258 | Instruction Type: CVI_VA |
| 1259 | Execution Slots: SLOT0123 |
| 1260 | ========================================================================== */ |
| 1261 | |
| 1262 | #define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) |
| 1263 | |
| 1264 | /* ========================================================================== |
| 1265 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1266 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1267 | Instruction Type: CVI_VA |
| 1268 | Execution Slots: SLOT0123 |
| 1269 | ========================================================================== */ |
| 1270 | |
| 1271 | #define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1272 | |
| 1273 | /* ========================================================================== |
| 1274 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1275 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1276 | Instruction Type: CVI_VA |
| 1277 | Execution Slots: SLOT0123 |
| 1278 | ========================================================================== */ |
| 1279 | |
| 1280 | #define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1281 | |
| 1282 | /* ========================================================================== |
| 1283 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1284 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1285 | Instruction Type: CVI_VA |
| 1286 | Execution Slots: SLOT0123 |
| 1287 | ========================================================================== */ |
| 1288 | |
| 1289 | #define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1290 | |
| 1291 | /* ========================================================================== |
| 1292 | Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) |
| 1293 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1294 | Instruction Type: CVI_VA |
| 1295 | Execution Slots: SLOT0123 |
| 1296 | ========================================================================== */ |
| 1297 | |
| 1298 | #define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) |
| 1299 | |
| 1300 | /* ========================================================================== |
| 1301 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) |
| 1302 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1303 | Instruction Type: CVI_VA |
| 1304 | Execution Slots: SLOT0123 |
| 1305 | ========================================================================== */ |
| 1306 | |
| 1307 | #define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1308 | |
| 1309 | /* ========================================================================== |
| 1310 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) |
| 1311 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1312 | Instruction Type: CVI_VA |
| 1313 | Execution Slots: SLOT0123 |
| 1314 | ========================================================================== */ |
| 1315 | |
| 1316 | #define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1317 | |
| 1318 | /* ========================================================================== |
| 1319 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) |
| 1320 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1321 | Instruction Type: CVI_VA |
| 1322 | Execution Slots: SLOT0123 |
| 1323 | ========================================================================== */ |
| 1324 | |
| 1325 | #define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 1326 | |
| 1327 | /* ========================================================================== |
| 1328 | Assembly Syntax: Vx32.w=vinsert(Rt32) |
| 1329 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) |
| 1330 | Instruction Type: CVI_VX_LATE |
| 1331 | Execution Slots: SLOT23 |
| 1332 | ========================================================================== */ |
| 1333 | |
| 1334 | #define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) |
| 1335 | |
| 1336 | /* ========================================================================== |
| 1337 | Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) |
| 1338 | C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1339 | Instruction Type: CVI_VP |
| 1340 | Execution Slots: SLOT0123 |
| 1341 | ========================================================================== */ |
| 1342 | |
| 1343 | #define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) |
| 1344 | |
| 1345 | /* ========================================================================== |
| 1346 | Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) |
| 1347 | C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 1348 | Instruction Type: CVI_VP |
| 1349 | Execution Slots: SLOT0123 |
| 1350 | ========================================================================== */ |
| 1351 | |
| 1352 | #define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) |
| 1353 | |
| 1354 | /* ========================================================================== |
| 1355 | Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) |
| 1356 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) |
| 1357 | Instruction Type: CVI_VS |
| 1358 | Execution Slots: SLOT0123 |
| 1359 | ========================================================================== */ |
| 1360 | |
| 1361 | #define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) |
| 1362 | |
| 1363 | /* ========================================================================== |
| 1364 | Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) |
| 1365 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1366 | Instruction Type: CVI_VS |
| 1367 | Execution Slots: SLOT0123 |
| 1368 | ========================================================================== */ |
| 1369 | |
| 1370 | #define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) |
| 1371 | |
| 1372 | /* ========================================================================== |
| 1373 | Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) |
| 1374 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) |
| 1375 | Instruction Type: CVI_VS |
| 1376 | Execution Slots: SLOT0123 |
| 1377 | ========================================================================== */ |
| 1378 | |
| 1379 | #define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) |
| 1380 | |
| 1381 | /* ========================================================================== |
| 1382 | Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) |
| 1383 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1384 | Instruction Type: CVI_VS |
| 1385 | Execution Slots: SLOT0123 |
| 1386 | ========================================================================== */ |
| 1387 | |
| 1388 | #define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) |
| 1389 | |
| 1390 | /* ========================================================================== |
| 1391 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) |
| 1392 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1393 | Instruction Type: CVI_VP |
| 1394 | Execution Slots: SLOT0123 |
| 1395 | ========================================================================== */ |
| 1396 | |
| 1397 | #define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) |
| 1398 | |
| 1399 | /* ========================================================================== |
| 1400 | Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) |
| 1401 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1402 | Instruction Type: CVI_VP_VS |
| 1403 | Execution Slots: SLOT0123 |
| 1404 | ========================================================================== */ |
| 1405 | |
| 1406 | #define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) |
| 1407 | |
| 1408 | /* ========================================================================== |
| 1409 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) |
| 1410 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1411 | Instruction Type: CVI_VP_VS |
| 1412 | Execution Slots: SLOT0123 |
| 1413 | ========================================================================== */ |
| 1414 | |
| 1415 | #define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) |
| 1416 | |
| 1417 | /* ========================================================================== |
| 1418 | Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) |
| 1419 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1420 | Instruction Type: CVI_VP_VS |
| 1421 | Execution Slots: SLOT0123 |
| 1422 | ========================================================================== */ |
| 1423 | |
| 1424 | #define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) |
| 1425 | |
| 1426 | /* ========================================================================== |
| 1427 | Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) |
| 1428 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1429 | Instruction Type: CVI_VA |
| 1430 | Execution Slots: SLOT0123 |
| 1431 | ========================================================================== */ |
| 1432 | |
| 1433 | #define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) |
| 1434 | |
| 1435 | /* ========================================================================== |
| 1436 | Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) |
| 1437 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1438 | Instruction Type: CVI_VA |
| 1439 | Execution Slots: SLOT0123 |
| 1440 | ========================================================================== */ |
| 1441 | |
| 1442 | #define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) |
| 1443 | |
| 1444 | /* ========================================================================== |
| 1445 | Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) |
| 1446 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1447 | Instruction Type: CVI_VA |
| 1448 | Execution Slots: SLOT0123 |
| 1449 | ========================================================================== */ |
| 1450 | |
| 1451 | #define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) |
| 1452 | |
| 1453 | /* ========================================================================== |
| 1454 | Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) |
| 1455 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1456 | Instruction Type: CVI_VA |
| 1457 | Execution Slots: SLOT0123 |
| 1458 | ========================================================================== */ |
| 1459 | |
| 1460 | #define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) |
| 1461 | |
| 1462 | /* ========================================================================== |
| 1463 | Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) |
| 1464 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1465 | Instruction Type: CVI_VA |
| 1466 | Execution Slots: SLOT0123 |
| 1467 | ========================================================================== */ |
| 1468 | |
| 1469 | #define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) |
| 1470 | |
| 1471 | /* ========================================================================== |
| 1472 | Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) |
| 1473 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1474 | Instruction Type: CVI_VA |
| 1475 | Execution Slots: SLOT0123 |
| 1476 | ========================================================================== */ |
| 1477 | |
| 1478 | #define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) |
| 1479 | |
| 1480 | /* ========================================================================== |
| 1481 | Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) |
| 1482 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1483 | Instruction Type: CVI_VA |
| 1484 | Execution Slots: SLOT0123 |
| 1485 | ========================================================================== */ |
| 1486 | |
| 1487 | #define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) |
| 1488 | |
| 1489 | /* ========================================================================== |
| 1490 | Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) |
| 1491 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1492 | Instruction Type: CVI_VA |
| 1493 | Execution Slots: SLOT0123 |
| 1494 | ========================================================================== */ |
| 1495 | |
| 1496 | #define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) |
| 1497 | |
| 1498 | /* ========================================================================== |
| 1499 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) |
| 1500 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
| 1501 | Instruction Type: CVI_VX_DV |
| 1502 | Execution Slots: SLOT23 |
| 1503 | ========================================================================== */ |
| 1504 | |
| 1505 | #define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) |
| 1506 | |
| 1507 | /* ========================================================================== |
| 1508 | Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) |
| 1509 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1510 | Instruction Type: CVI_VX_DV |
| 1511 | Execution Slots: SLOT23 |
| 1512 | ========================================================================== */ |
| 1513 | |
| 1514 | #define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) |
| 1515 | |
| 1516 | /* ========================================================================== |
| 1517 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) |
| 1518 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 1519 | Instruction Type: CVI_VX_DV |
| 1520 | Execution Slots: SLOT23 |
| 1521 | ========================================================================== */ |
| 1522 | |
| 1523 | #define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) |
| 1524 | |
| 1525 | /* ========================================================================== |
| 1526 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) |
| 1527 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 1528 | Instruction Type: CVI_VX_DV |
| 1529 | Execution Slots: SLOT23 |
| 1530 | ========================================================================== */ |
| 1531 | |
| 1532 | #define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) |
| 1533 | |
| 1534 | /* ========================================================================== |
| 1535 | Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) |
| 1536 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 1537 | Instruction Type: CVI_VX_DV |
| 1538 | Execution Slots: SLOT23 |
| 1539 | ========================================================================== */ |
| 1540 | |
| 1541 | #define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) |
| 1542 | |
| 1543 | /* ========================================================================== |
| 1544 | Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) |
| 1545 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1546 | Instruction Type: CVI_VX_DV |
| 1547 | Execution Slots: SLOT23 |
| 1548 | ========================================================================== */ |
| 1549 | |
| 1550 | #define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) |
| 1551 | |
| 1552 | /* ========================================================================== |
| 1553 | Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) |
| 1554 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
| 1555 | Instruction Type: CVI_VX_DV |
| 1556 | Execution Slots: SLOT23 |
| 1557 | ========================================================================== */ |
| 1558 | |
| 1559 | #define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) |
| 1560 | |
| 1561 | /* ========================================================================== |
| 1562 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) |
| 1563 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 1564 | Instruction Type: CVI_VX_DV |
| 1565 | Execution Slots: SLOT23 |
| 1566 | ========================================================================== */ |
| 1567 | |
| 1568 | #define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) |
| 1569 | |
| 1570 | /* ========================================================================== |
| 1571 | Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) |
| 1572 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1573 | Instruction Type: CVI_VX_DV |
| 1574 | Execution Slots: SLOT23 |
| 1575 | ========================================================================== */ |
| 1576 | |
| 1577 | #define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) |
| 1578 | |
| 1579 | /* ========================================================================== |
| 1580 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) |
| 1581 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1582 | Instruction Type: CVI_VX_DV |
| 1583 | Execution Slots: SLOT23 |
| 1584 | ========================================================================== */ |
| 1585 | |
| 1586 | #define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) |
| 1587 | |
| 1588 | /* ========================================================================== |
| 1589 | Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) |
| 1590 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1591 | Instruction Type: CVI_VX_DV |
| 1592 | Execution Slots: SLOT23 |
| 1593 | ========================================================================== */ |
| 1594 | |
| 1595 | #define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) |
| 1596 | |
| 1597 | /* ========================================================================== |
| 1598 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) |
| 1599 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1600 | Instruction Type: CVI_VX_DV |
| 1601 | Execution Slots: SLOT23 |
| 1602 | ========================================================================== */ |
| 1603 | |
| 1604 | #define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) |
| 1605 | |
| 1606 | /* ========================================================================== |
| 1607 | Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) |
| 1608 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1609 | Instruction Type: CVI_VX_DV |
| 1610 | Execution Slots: SLOT23 |
| 1611 | ========================================================================== */ |
| 1612 | |
| 1613 | #define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) |
| 1614 | |
| 1615 | /* ========================================================================== |
| 1616 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) |
| 1617 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) |
| 1618 | Instruction Type: CVI_VX_DV |
| 1619 | Execution Slots: SLOT23 |
| 1620 | ========================================================================== */ |
| 1621 | |
| 1622 | #define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) |
| 1623 | |
| 1624 | /* ========================================================================== |
| 1625 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat |
| 1626 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 1627 | Instruction Type: CVI_VX_DV |
| 1628 | Execution Slots: SLOT23 |
| 1629 | ========================================================================== */ |
| 1630 | |
| 1631 | #define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) |
| 1632 | |
| 1633 | /* ========================================================================== |
| 1634 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat |
| 1635 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) |
| 1636 | Instruction Type: CVI_VX |
| 1637 | Execution Slots: SLOT23 |
| 1638 | ========================================================================== */ |
| 1639 | |
| 1640 | #define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) |
| 1641 | |
| 1642 | /* ========================================================================== |
| 1643 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat |
| 1644 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) |
| 1645 | Instruction Type: CVI_VX |
| 1646 | Execution Slots: SLOT23 |
| 1647 | ========================================================================== */ |
| 1648 | |
| 1649 | #define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) |
| 1650 | |
| 1651 | /* ========================================================================== |
| 1652 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) |
| 1653 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1654 | Instruction Type: CVI_VX_DV |
| 1655 | Execution Slots: SLOT23 |
| 1656 | ========================================================================== */ |
| 1657 | |
| 1658 | #define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) |
| 1659 | |
| 1660 | /* ========================================================================== |
| 1661 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) |
| 1662 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1663 | Instruction Type: CVI_VX_DV |
| 1664 | Execution Slots: SLOT23 |
| 1665 | ========================================================================== */ |
| 1666 | |
| 1667 | #define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) |
| 1668 | |
| 1669 | /* ========================================================================== |
| 1670 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) |
| 1671 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1672 | Instruction Type: CVI_VX_DV |
| 1673 | Execution Slots: SLOT23 |
| 1674 | ========================================================================== */ |
| 1675 | |
| 1676 | #define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) |
| 1677 | |
| 1678 | /* ========================================================================== |
| 1679 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) |
| 1680 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1681 | Instruction Type: CVI_VX_DV |
| 1682 | Execution Slots: SLOT23 |
| 1683 | ========================================================================== */ |
| 1684 | |
| 1685 | #define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) |
| 1686 | |
| 1687 | /* ========================================================================== |
| 1688 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat |
| 1689 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 1690 | Instruction Type: CVI_VX |
| 1691 | Execution Slots: SLOT23 |
| 1692 | ========================================================================== */ |
| 1693 | |
| 1694 | #define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) |
| 1695 | |
| 1696 | /* ========================================================================== |
| 1697 | Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) |
| 1698 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1699 | Instruction Type: CVI_VX |
| 1700 | Execution Slots: SLOT23 |
| 1701 | ========================================================================== */ |
| 1702 | |
| 1703 | #define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) |
| 1704 | |
| 1705 | /* ========================================================================== |
| 1706 | Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) |
| 1707 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 1708 | Instruction Type: CVI_VX_DV |
| 1709 | Execution Slots: SLOT23 |
| 1710 | ========================================================================== */ |
| 1711 | |
| 1712 | #define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) |
| 1713 | |
| 1714 | /* ========================================================================== |
| 1715 | Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) |
| 1716 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1717 | Instruction Type: CVI_VX_DV |
| 1718 | Execution Slots: SLOT23 |
| 1719 | ========================================================================== */ |
| 1720 | |
| 1721 | #define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) |
| 1722 | |
| 1723 | /* ========================================================================== |
| 1724 | Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) |
| 1725 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 1726 | Instruction Type: CVI_VX_DV |
| 1727 | Execution Slots: SLOT23 |
| 1728 | ========================================================================== */ |
| 1729 | |
| 1730 | #define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) |
| 1731 | |
| 1732 | /* ========================================================================== |
| 1733 | Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) |
| 1734 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1735 | Instruction Type: CVI_VX_DV |
| 1736 | Execution Slots: SLOT23 |
| 1737 | ========================================================================== */ |
| 1738 | |
| 1739 | #define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) |
| 1740 | |
| 1741 | /* ========================================================================== |
| 1742 | Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) |
| 1743 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 1744 | Instruction Type: CVI_VX_DV |
| 1745 | Execution Slots: SLOT23 |
| 1746 | ========================================================================== */ |
| 1747 | |
| 1748 | #define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) |
| 1749 | |
| 1750 | /* ========================================================================== |
| 1751 | Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) |
| 1752 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) |
| 1753 | Instruction Type: CVI_VX |
| 1754 | Execution Slots: SLOT23 |
| 1755 | ========================================================================== */ |
| 1756 | |
| 1757 | #define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) |
| 1758 | |
| 1759 | /* ========================================================================== |
| 1760 | Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) |
| 1761 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1762 | Instruction Type: CVI_VX |
| 1763 | Execution Slots: SLOT23 |
| 1764 | ========================================================================== */ |
| 1765 | |
| 1766 | #define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) |
| 1767 | |
| 1768 | /* ========================================================================== |
| 1769 | Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) |
| 1770 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1771 | Instruction Type: CVI_VX_DV |
| 1772 | Execution Slots: SLOT23 |
| 1773 | ========================================================================== */ |
| 1774 | |
| 1775 | #define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) |
| 1776 | |
| 1777 | /* ========================================================================== |
| 1778 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) |
| 1779 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) |
| 1780 | Instruction Type: CVI_VX |
| 1781 | Execution Slots: SLOT23 |
| 1782 | ========================================================================== */ |
| 1783 | |
| 1784 | #define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) |
| 1785 | |
| 1786 | /* ========================================================================== |
| 1787 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) |
| 1788 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1789 | Instruction Type: CVI_VX |
| 1790 | Execution Slots: SLOT23 |
| 1791 | ========================================================================== */ |
| 1792 | |
| 1793 | #define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) |
| 1794 | |
| 1795 | /* ========================================================================== |
| 1796 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) |
| 1797 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) |
| 1798 | Instruction Type: CVI_VX_DV |
| 1799 | Execution Slots: SLOT23 |
| 1800 | ========================================================================== */ |
| 1801 | |
| 1802 | #define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) |
| 1803 | |
| 1804 | /* ========================================================================== |
| 1805 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) |
| 1806 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1807 | Instruction Type: CVI_VX_DV |
| 1808 | Execution Slots: SLOT23 |
| 1809 | ========================================================================== */ |
| 1810 | |
| 1811 | #define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) |
| 1812 | |
| 1813 | /* ========================================================================== |
| 1814 | Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat |
| 1815 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 1816 | Instruction Type: CVI_VX_DV |
| 1817 | Execution Slots: SLOT23 |
| 1818 | ========================================================================== */ |
| 1819 | |
| 1820 | #define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) |
| 1821 | |
| 1822 | /* ========================================================================== |
| 1823 | Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat |
| 1824 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 1825 | Instruction Type: CVI_VX_DV |
| 1826 | Execution Slots: SLOT23 |
| 1827 | ========================================================================== */ |
| 1828 | |
| 1829 | #define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) |
| 1830 | |
| 1831 | /* ========================================================================== |
| 1832 | Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift |
| 1833 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 1834 | Instruction Type: CVI_VX_DV |
| 1835 | Execution Slots: SLOT23 |
| 1836 | ========================================================================== */ |
| 1837 | |
| 1838 | #define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) |
| 1839 | |
| 1840 | /* ========================================================================== |
| 1841 | Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift |
| 1842 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 1843 | Instruction Type: CVI_VX_DV |
| 1844 | Execution Slots: SLOT23 |
| 1845 | ========================================================================== */ |
| 1846 | |
| 1847 | #define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) |
| 1848 | |
| 1849 | /* ========================================================================== |
| 1850 | Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) |
| 1851 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) |
| 1852 | Instruction Type: CVI_VX_DV |
| 1853 | Execution Slots: SLOT23 |
| 1854 | ========================================================================== */ |
| 1855 | |
| 1856 | #define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) |
| 1857 | |
| 1858 | /* ========================================================================== |
| 1859 | Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) |
| 1860 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 1861 | Instruction Type: CVI_VX_DV |
| 1862 | Execution Slots: SLOT23 |
| 1863 | ========================================================================== */ |
| 1864 | |
| 1865 | #define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) |
| 1866 | |
| 1867 | /* ========================================================================== |
| 1868 | Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) |
| 1869 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1870 | Instruction Type: CVI_VX_DV |
| 1871 | Execution Slots: SLOT23 |
| 1872 | ========================================================================== */ |
| 1873 | |
| 1874 | #define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) |
| 1875 | |
| 1876 | /* ========================================================================== |
| 1877 | Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) |
| 1878 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1879 | Instruction Type: CVI_VX_DV |
| 1880 | Execution Slots: SLOT23 |
| 1881 | ========================================================================== */ |
| 1882 | |
| 1883 | #define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) |
| 1884 | |
| 1885 | /* ========================================================================== |
| 1886 | Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) |
| 1887 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) |
| 1888 | Instruction Type: CVI_VX_DV |
| 1889 | Execution Slots: SLOT23 |
| 1890 | ========================================================================== */ |
| 1891 | |
| 1892 | #define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) |
| 1893 | |
| 1894 | /* ========================================================================== |
| 1895 | Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) |
| 1896 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 1897 | Instruction Type: CVI_VX_DV |
| 1898 | Execution Slots: SLOT23 |
| 1899 | ========================================================================== */ |
| 1900 | |
| 1901 | #define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) |
| 1902 | |
| 1903 | /* ========================================================================== |
| 1904 | Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) |
| 1905 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1906 | Instruction Type: CVI_VX_DV |
| 1907 | Execution Slots: SLOT23 |
| 1908 | ========================================================================== */ |
| 1909 | |
| 1910 | #define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) |
| 1911 | |
| 1912 | /* ========================================================================== |
| 1913 | Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) |
| 1914 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1915 | Instruction Type: CVI_VX_DV |
| 1916 | Execution Slots: SLOT23 |
| 1917 | ========================================================================== */ |
| 1918 | |
| 1919 | #define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) |
| 1920 | |
| 1921 | /* ========================================================================== |
| 1922 | Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) |
| 1923 | C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) |
| 1924 | Instruction Type: CVI_VA |
| 1925 | Execution Slots: SLOT0123 |
| 1926 | ========================================================================== */ |
| 1927 | |
| 1928 | #define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) |
| 1929 | |
| 1930 | /* ========================================================================== |
| 1931 | Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) |
| 1932 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1933 | Instruction Type: CVI_VA |
| 1934 | Execution Slots: SLOT0123 |
| 1935 | ========================================================================== */ |
| 1936 | |
| 1937 | #define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) |
| 1938 | |
| 1939 | /* ========================================================================== |
| 1940 | Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) |
| 1941 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1942 | Instruction Type: CVI_VA |
| 1943 | Execution Slots: SLOT0123 |
| 1944 | ========================================================================== */ |
| 1945 | |
| 1946 | #define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) |
| 1947 | |
| 1948 | /* ========================================================================== |
| 1949 | Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) |
| 1950 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1951 | Instruction Type: CVI_VA |
| 1952 | Execution Slots: SLOT0123 |
| 1953 | ========================================================================== */ |
| 1954 | |
| 1955 | #define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) |
| 1956 | |
| 1957 | /* ========================================================================== |
| 1958 | Assembly Syntax: Vd32.h=vnormamt(Vu32.h) |
| 1959 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) |
| 1960 | Instruction Type: CVI_VS |
| 1961 | Execution Slots: SLOT0123 |
| 1962 | ========================================================================== */ |
| 1963 | |
| 1964 | #define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) |
| 1965 | |
| 1966 | /* ========================================================================== |
| 1967 | Assembly Syntax: Vd32.w=vnormamt(Vu32.w) |
| 1968 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) |
| 1969 | Instruction Type: CVI_VS |
| 1970 | Execution Slots: SLOT0123 |
| 1971 | ========================================================================== */ |
| 1972 | |
| 1973 | #define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) |
| 1974 | |
| 1975 | /* ========================================================================== |
| 1976 | Assembly Syntax: Vd32=vnot(Vu32) |
| 1977 | C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) |
| 1978 | Instruction Type: CVI_VA |
| 1979 | Execution Slots: SLOT0123 |
| 1980 | ========================================================================== */ |
| 1981 | |
| 1982 | #define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) |
| 1983 | |
| 1984 | /* ========================================================================== |
| 1985 | Assembly Syntax: Vd32=vor(Vu32,Vv32) |
| 1986 | C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 1987 | Instruction Type: CVI_VA |
| 1988 | Execution Slots: SLOT0123 |
| 1989 | ========================================================================== */ |
| 1990 | |
| 1991 | #define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) |
| 1992 | |
| 1993 | /* ========================================================================== |
| 1994 | Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) |
| 1995 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1996 | Instruction Type: CVI_VP |
| 1997 | Execution Slots: SLOT0123 |
| 1998 | ========================================================================== */ |
| 1999 | |
| 2000 | #define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) |
| 2001 | |
| 2002 | /* ========================================================================== |
| 2003 | Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) |
| 2004 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2005 | Instruction Type: CVI_VP |
| 2006 | Execution Slots: SLOT0123 |
| 2007 | ========================================================================== */ |
| 2008 | |
| 2009 | #define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) |
| 2010 | |
| 2011 | /* ========================================================================== |
| 2012 | Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat |
| 2013 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2014 | Instruction Type: CVI_VP |
| 2015 | Execution Slots: SLOT0123 |
| 2016 | ========================================================================== */ |
| 2017 | |
| 2018 | #define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) |
| 2019 | |
| 2020 | /* ========================================================================== |
| 2021 | Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat |
| 2022 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2023 | Instruction Type: CVI_VP |
| 2024 | Execution Slots: SLOT0123 |
| 2025 | ========================================================================== */ |
| 2026 | |
| 2027 | #define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) |
| 2028 | |
| 2029 | /* ========================================================================== |
| 2030 | Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) |
| 2031 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2032 | Instruction Type: CVI_VP |
| 2033 | Execution Slots: SLOT0123 |
| 2034 | ========================================================================== */ |
| 2035 | |
| 2036 | #define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) |
| 2037 | |
| 2038 | /* ========================================================================== |
| 2039 | Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) |
| 2040 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2041 | Instruction Type: CVI_VP |
| 2042 | Execution Slots: SLOT0123 |
| 2043 | ========================================================================== */ |
| 2044 | |
| 2045 | #define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) |
| 2046 | |
| 2047 | /* ========================================================================== |
| 2048 | Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat |
| 2049 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2050 | Instruction Type: CVI_VP |
| 2051 | Execution Slots: SLOT0123 |
| 2052 | ========================================================================== */ |
| 2053 | |
| 2054 | #define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) |
| 2055 | |
| 2056 | /* ========================================================================== |
| 2057 | Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat |
| 2058 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2059 | Instruction Type: CVI_VP |
| 2060 | Execution Slots: SLOT0123 |
| 2061 | ========================================================================== */ |
| 2062 | |
| 2063 | #define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) |
| 2064 | |
| 2065 | /* ========================================================================== |
| 2066 | Assembly Syntax: Vd32.h=vpopcount(Vu32.h) |
| 2067 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) |
| 2068 | Instruction Type: CVI_VS |
| 2069 | Execution Slots: SLOT0123 |
| 2070 | ========================================================================== */ |
| 2071 | |
| 2072 | #define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) |
| 2073 | |
| 2074 | /* ========================================================================== |
| 2075 | Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) |
| 2076 | C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 2077 | Instruction Type: CVI_VP |
| 2078 | Execution Slots: SLOT0123 |
| 2079 | ========================================================================== */ |
| 2080 | |
| 2081 | #define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) |
| 2082 | |
| 2083 | /* ========================================================================== |
| 2084 | Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) |
| 2085 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
| 2086 | Instruction Type: CVI_VX |
| 2087 | Execution Slots: SLOT23 |
| 2088 | ========================================================================== */ |
| 2089 | |
| 2090 | #define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) |
| 2091 | |
| 2092 | /* ========================================================================== |
| 2093 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) |
| 2094 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2095 | Instruction Type: CVI_VX |
| 2096 | Execution Slots: SLOT23 |
| 2097 | ========================================================================== */ |
| 2098 | |
| 2099 | #define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) |
| 2100 | |
| 2101 | /* ========================================================================== |
| 2102 | Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) |
| 2103 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2104 | Instruction Type: CVI_VX_DV |
| 2105 | Execution Slots: SLOT23 |
| 2106 | ========================================================================== */ |
| 2107 | |
| 2108 | #define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) |
| 2109 | |
| 2110 | /* ========================================================================== |
| 2111 | Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) |
| 2112 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2113 | Instruction Type: CVI_VX_DV |
| 2114 | Execution Slots: SLOT23 |
| 2115 | ========================================================================== */ |
| 2116 | |
| 2117 | #define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) |
| 2118 | |
| 2119 | /* ========================================================================== |
| 2120 | Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) |
| 2121 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2122 | Instruction Type: CVI_VX |
| 2123 | Execution Slots: SLOT23 |
| 2124 | ========================================================================== */ |
| 2125 | |
| 2126 | #define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) |
| 2127 | |
| 2128 | /* ========================================================================== |
| 2129 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) |
| 2130 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2131 | Instruction Type: CVI_VX |
| 2132 | Execution Slots: SLOT23 |
| 2133 | ========================================================================== */ |
| 2134 | |
| 2135 | #define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) |
| 2136 | |
| 2137 | /* ========================================================================== |
| 2138 | Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) |
| 2139 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2140 | Instruction Type: CVI_VX |
| 2141 | Execution Slots: SLOT23 |
| 2142 | ========================================================================== */ |
| 2143 | |
| 2144 | #define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) |
| 2145 | |
| 2146 | /* ========================================================================== |
| 2147 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) |
| 2148 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2149 | Instruction Type: CVI_VX |
| 2150 | Execution Slots: SLOT23 |
| 2151 | ========================================================================== */ |
| 2152 | |
| 2153 | #define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) |
| 2154 | |
| 2155 | /* ========================================================================== |
| 2156 | Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) |
| 2157 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) |
| 2158 | Instruction Type: CVI_VX |
| 2159 | Execution Slots: SLOT23 |
| 2160 | ========================================================================== */ |
| 2161 | |
| 2162 | #define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) |
| 2163 | |
| 2164 | /* ========================================================================== |
| 2165 | Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) |
| 2166 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2167 | Instruction Type: CVI_VX |
| 2168 | Execution Slots: SLOT23 |
| 2169 | ========================================================================== */ |
| 2170 | |
| 2171 | #define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) |
| 2172 | |
| 2173 | /* ========================================================================== |
| 2174 | Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) |
| 2175 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2176 | Instruction Type: CVI_VX_DV |
| 2177 | Execution Slots: SLOT23 |
| 2178 | ========================================================================== */ |
| 2179 | |
| 2180 | #define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) |
| 2181 | |
| 2182 | /* ========================================================================== |
| 2183 | Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) |
| 2184 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2185 | Instruction Type: CVI_VX_DV |
| 2186 | Execution Slots: SLOT23 |
| 2187 | ========================================================================== */ |
| 2188 | |
| 2189 | #define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) |
| 2190 | |
| 2191 | /* ========================================================================== |
| 2192 | Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) |
| 2193 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 2194 | Instruction Type: CVI_VX |
| 2195 | Execution Slots: SLOT23 |
| 2196 | ========================================================================== */ |
| 2197 | |
| 2198 | #define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) |
| 2199 | |
| 2200 | /* ========================================================================== |
| 2201 | Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) |
| 2202 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2203 | Instruction Type: CVI_VX |
| 2204 | Execution Slots: SLOT23 |
| 2205 | ========================================================================== */ |
| 2206 | |
| 2207 | #define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) |
| 2208 | |
| 2209 | /* ========================================================================== |
| 2210 | Assembly Syntax: Vd32=vror(Vu32,Rt32) |
| 2211 | C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) |
| 2212 | Instruction Type: CVI_VP |
| 2213 | Execution Slots: SLOT0123 |
| 2214 | ========================================================================== */ |
| 2215 | |
| 2216 | #define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) |
| 2217 | |
| 2218 | /* ========================================================================== |
| 2219 | Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat |
| 2220 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2221 | Instruction Type: CVI_VS |
| 2222 | Execution Slots: SLOT0123 |
| 2223 | ========================================================================== */ |
| 2224 | |
| 2225 | #define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) |
| 2226 | |
| 2227 | /* ========================================================================== |
| 2228 | Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat |
| 2229 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2230 | Instruction Type: CVI_VS |
| 2231 | Execution Slots: SLOT0123 |
| 2232 | ========================================================================== */ |
| 2233 | |
| 2234 | #define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) |
| 2235 | |
| 2236 | /* ========================================================================== |
| 2237 | Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat |
| 2238 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2239 | Instruction Type: CVI_VS |
| 2240 | Execution Slots: SLOT0123 |
| 2241 | ========================================================================== */ |
| 2242 | |
| 2243 | #define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) |
| 2244 | |
| 2245 | /* ========================================================================== |
| 2246 | Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat |
| 2247 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2248 | Instruction Type: CVI_VS |
| 2249 | Execution Slots: SLOT0123 |
| 2250 | ========================================================================== */ |
| 2251 | |
| 2252 | #define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) |
| 2253 | |
| 2254 | /* ========================================================================== |
| 2255 | Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) |
| 2256 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2257 | Instruction Type: CVI_VX_DV |
| 2258 | Execution Slots: SLOT23 |
| 2259 | ========================================================================== */ |
| 2260 | |
| 2261 | #define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) |
| 2262 | |
| 2263 | /* ========================================================================== |
| 2264 | Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) |
| 2265 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2266 | Instruction Type: CVI_VX_DV |
| 2267 | Execution Slots: SLOT23 |
| 2268 | ========================================================================== */ |
| 2269 | |
| 2270 | #define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) |
| 2271 | |
| 2272 | /* ========================================================================== |
| 2273 | Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) |
| 2274 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2275 | Instruction Type: CVI_VA |
| 2276 | Execution Slots: SLOT0123 |
| 2277 | ========================================================================== */ |
| 2278 | |
| 2279 | #define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) |
| 2280 | |
| 2281 | /* ========================================================================== |
| 2282 | Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) |
| 2283 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2284 | Instruction Type: CVI_VA |
| 2285 | Execution Slots: SLOT0123 |
| 2286 | ========================================================================== */ |
| 2287 | |
| 2288 | #define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) |
| 2289 | |
| 2290 | /* ========================================================================== |
| 2291 | Assembly Syntax: Vdd32.h=vsxt(Vu32.b) |
| 2292 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) |
| 2293 | Instruction Type: CVI_VA_DV |
| 2294 | Execution Slots: SLOT0123 |
| 2295 | ========================================================================== */ |
| 2296 | |
| 2297 | #define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) |
| 2298 | |
| 2299 | /* ========================================================================== |
| 2300 | Assembly Syntax: Vdd32.w=vsxt(Vu32.h) |
| 2301 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) |
| 2302 | Instruction Type: CVI_VA_DV |
| 2303 | Execution Slots: SLOT0123 |
| 2304 | ========================================================================== */ |
| 2305 | |
| 2306 | #define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) |
| 2307 | |
| 2308 | /* ========================================================================== |
| 2309 | Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) |
| 2310 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2311 | Instruction Type: CVI_VA |
| 2312 | Execution Slots: SLOT0123 |
| 2313 | ========================================================================== */ |
| 2314 | |
| 2315 | #define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) |
| 2316 | |
| 2317 | /* ========================================================================== |
| 2318 | Assembly Syntax: Vd32.b=vshuff(Vu32.b) |
| 2319 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) |
| 2320 | Instruction Type: CVI_VP |
| 2321 | Execution Slots: SLOT0123 |
| 2322 | ========================================================================== */ |
| 2323 | |
| 2324 | #define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) |
| 2325 | |
| 2326 | /* ========================================================================== |
| 2327 | Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) |
| 2328 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2329 | Instruction Type: CVI_VA |
| 2330 | Execution Slots: SLOT0123 |
| 2331 | ========================================================================== */ |
| 2332 | |
| 2333 | #define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) |
| 2334 | |
| 2335 | /* ========================================================================== |
| 2336 | Assembly Syntax: Vd32.h=vshuff(Vu32.h) |
| 2337 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) |
| 2338 | Instruction Type: CVI_VP |
| 2339 | Execution Slots: SLOT0123 |
| 2340 | ========================================================================== */ |
| 2341 | |
| 2342 | #define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) |
| 2343 | |
| 2344 | /* ========================================================================== |
| 2345 | Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) |
| 2346 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2347 | Instruction Type: CVI_VA |
| 2348 | Execution Slots: SLOT0123 |
| 2349 | ========================================================================== */ |
| 2350 | |
| 2351 | #define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) |
| 2352 | |
| 2353 | /* ========================================================================== |
| 2354 | Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) |
| 2355 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 2356 | Instruction Type: CVI_VP_VS |
| 2357 | Execution Slots: SLOT0123 |
| 2358 | ========================================================================== */ |
| 2359 | |
| 2360 | #define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) |
| 2361 | |
| 2362 | /* ========================================================================== |
| 2363 | Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) |
| 2364 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2365 | Instruction Type: CVI_VA_DV |
| 2366 | Execution Slots: SLOT0123 |
| 2367 | ========================================================================== */ |
| 2368 | |
| 2369 | #define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) |
| 2370 | |
| 2371 | /* ========================================================================== |
| 2372 | Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) |
| 2373 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2374 | Instruction Type: CVI_VA_DV |
| 2375 | Execution Slots: SLOT0123 |
| 2376 | ========================================================================== */ |
| 2377 | |
| 2378 | #define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) |
| 2379 | |
| 2380 | /* ========================================================================== |
| 2381 | Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) |
| 2382 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2383 | Instruction Type: CVI_VA |
| 2384 | Execution Slots: SLOT0123 |
| 2385 | ========================================================================== */ |
| 2386 | |
| 2387 | #define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) |
| 2388 | |
| 2389 | /* ========================================================================== |
| 2390 | Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) |
| 2391 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2392 | Instruction Type: CVI_VA |
| 2393 | Execution Slots: SLOT0123 |
| 2394 | ========================================================================== */ |
| 2395 | |
| 2396 | #define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) |
| 2397 | |
| 2398 | /* ========================================================================== |
| 2399 | Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) |
| 2400 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2401 | Instruction Type: CVI_VA_DV |
| 2402 | Execution Slots: SLOT0123 |
| 2403 | ========================================================================== */ |
| 2404 | |
| 2405 | #define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) |
| 2406 | |
| 2407 | /* ========================================================================== |
| 2408 | Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b |
| 2409 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2410 | Instruction Type: CVI_VA |
| 2411 | Execution Slots: SLOT0123 |
| 2412 | ========================================================================== */ |
| 2413 | |
| 2414 | #define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 2415 | |
| 2416 | /* ========================================================================== |
| 2417 | Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b |
| 2418 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2419 | Instruction Type: CVI_VA |
| 2420 | Execution Slots: SLOT0123 |
| 2421 | ========================================================================== */ |
| 2422 | |
| 2423 | #define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 2424 | |
| 2425 | /* ========================================================================== |
| 2426 | Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) |
| 2427 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2428 | Instruction Type: CVI_VA |
| 2429 | Execution Slots: SLOT0123 |
| 2430 | ========================================================================== */ |
| 2431 | |
| 2432 | #define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) |
| 2433 | |
| 2434 | /* ========================================================================== |
| 2435 | Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) |
| 2436 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2437 | Instruction Type: CVI_VA_DV |
| 2438 | Execution Slots: SLOT0123 |
| 2439 | ========================================================================== */ |
| 2440 | |
| 2441 | #define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) |
| 2442 | |
| 2443 | /* ========================================================================== |
| 2444 | Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h |
| 2445 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2446 | Instruction Type: CVI_VA |
| 2447 | Execution Slots: SLOT0123 |
| 2448 | ========================================================================== */ |
| 2449 | |
| 2450 | #define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 2451 | |
| 2452 | /* ========================================================================== |
| 2453 | Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h |
| 2454 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2455 | Instruction Type: CVI_VA |
| 2456 | Execution Slots: SLOT0123 |
| 2457 | ========================================================================== */ |
| 2458 | |
| 2459 | #define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 2460 | |
| 2461 | /* ========================================================================== |
| 2462 | Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat |
| 2463 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2464 | Instruction Type: CVI_VA |
| 2465 | Execution Slots: SLOT0123 |
| 2466 | ========================================================================== */ |
| 2467 | |
| 2468 | #define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) |
| 2469 | |
| 2470 | /* ========================================================================== |
| 2471 | Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat |
| 2472 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2473 | Instruction Type: CVI_VA_DV |
| 2474 | Execution Slots: SLOT0123 |
| 2475 | ========================================================================== */ |
| 2476 | |
| 2477 | #define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) |
| 2478 | |
| 2479 | /* ========================================================================== |
| 2480 | Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) |
| 2481 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2482 | Instruction Type: CVI_VX_DV |
| 2483 | Execution Slots: SLOT23 |
| 2484 | ========================================================================== */ |
| 2485 | |
| 2486 | #define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) |
| 2487 | |
| 2488 | /* ========================================================================== |
| 2489 | Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) |
| 2490 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 2491 | Instruction Type: CVI_VX_DV |
| 2492 | Execution Slots: SLOT23 |
| 2493 | ========================================================================== */ |
| 2494 | |
| 2495 | #define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) |
| 2496 | |
| 2497 | /* ========================================================================== |
| 2498 | Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat |
| 2499 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2500 | Instruction Type: CVI_VA |
| 2501 | Execution Slots: SLOT0123 |
| 2502 | ========================================================================== */ |
| 2503 | |
| 2504 | #define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) |
| 2505 | |
| 2506 | /* ========================================================================== |
| 2507 | Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat |
| 2508 | C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2509 | Instruction Type: CVI_VA_DV |
| 2510 | Execution Slots: SLOT0123 |
| 2511 | ========================================================================== */ |
| 2512 | |
| 2513 | #define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) |
| 2514 | |
| 2515 | /* ========================================================================== |
| 2516 | Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat |
| 2517 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2518 | Instruction Type: CVI_VA |
| 2519 | Execution Slots: SLOT0123 |
| 2520 | ========================================================================== */ |
| 2521 | |
| 2522 | #define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) |
| 2523 | |
| 2524 | /* ========================================================================== |
| 2525 | Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat |
| 2526 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2527 | Instruction Type: CVI_VA_DV |
| 2528 | Execution Slots: SLOT0123 |
| 2529 | ========================================================================== */ |
| 2530 | |
| 2531 | #define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) |
| 2532 | |
| 2533 | /* ========================================================================== |
| 2534 | Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) |
| 2535 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 2536 | Instruction Type: CVI_VX_DV |
| 2537 | Execution Slots: SLOT23 |
| 2538 | ========================================================================== */ |
| 2539 | |
| 2540 | #define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) |
| 2541 | |
| 2542 | /* ========================================================================== |
| 2543 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) |
| 2544 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2545 | Instruction Type: CVI_VA |
| 2546 | Execution Slots: SLOT0123 |
| 2547 | ========================================================================== */ |
| 2548 | |
| 2549 | #define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) |
| 2550 | |
| 2551 | /* ========================================================================== |
| 2552 | Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) |
| 2553 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2554 | Instruction Type: CVI_VA_DV |
| 2555 | Execution Slots: SLOT0123 |
| 2556 | ========================================================================== */ |
| 2557 | |
| 2558 | #define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) |
| 2559 | |
| 2560 | /* ========================================================================== |
| 2561 | Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w |
| 2562 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2563 | Instruction Type: CVI_VA |
| 2564 | Execution Slots: SLOT0123 |
| 2565 | ========================================================================== */ |
| 2566 | |
| 2567 | #define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 2568 | |
| 2569 | /* ========================================================================== |
| 2570 | Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w |
| 2571 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2572 | Instruction Type: CVI_VA |
| 2573 | Execution Slots: SLOT0123 |
| 2574 | ========================================================================== */ |
| 2575 | |
| 2576 | #define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
| 2577 | |
| 2578 | /* ========================================================================== |
| 2579 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat |
| 2580 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2581 | Instruction Type: CVI_VA |
| 2582 | Execution Slots: SLOT0123 |
| 2583 | ========================================================================== */ |
| 2584 | |
| 2585 | #define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) |
| 2586 | |
| 2587 | /* ========================================================================== |
| 2588 | Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat |
| 2589 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2590 | Instruction Type: CVI_VA_DV |
| 2591 | Execution Slots: SLOT0123 |
| 2592 | ========================================================================== */ |
| 2593 | |
| 2594 | #define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) |
| 2595 | |
| 2596 | /* ========================================================================== |
| 2597 | Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) |
| 2598 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) |
| 2599 | Instruction Type: CVI_VA_DV |
| 2600 | Execution Slots: SLOT0123 |
| 2601 | ========================================================================== */ |
| 2602 | |
| 2603 | #define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) |
| 2604 | |
| 2605 | /* ========================================================================== |
| 2606 | Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) |
| 2607 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) |
| 2608 | Instruction Type: CVI_VX_DV |
| 2609 | Execution Slots: SLOT23 |
| 2610 | ========================================================================== */ |
| 2611 | |
| 2612 | #define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) |
| 2613 | |
| 2614 | /* ========================================================================== |
| 2615 | Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) |
| 2616 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 2617 | Instruction Type: CVI_VX_DV |
| 2618 | Execution Slots: SLOT23 |
| 2619 | ========================================================================== */ |
| 2620 | |
| 2621 | #define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) |
| 2622 | |
| 2623 | /* ========================================================================== |
| 2624 | Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) |
| 2625 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
| 2626 | Instruction Type: CVI_VX_DV |
| 2627 | Execution Slots: SLOT23 |
| 2628 | ========================================================================== */ |
| 2629 | |
| 2630 | #define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) |
| 2631 | |
| 2632 | /* ========================================================================== |
| 2633 | Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) |
| 2634 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 2635 | Instruction Type: CVI_VX_DV |
| 2636 | Execution Slots: SLOT23 |
| 2637 | ========================================================================== */ |
| 2638 | |
| 2639 | #define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) |
| 2640 | |
| 2641 | /* ========================================================================== |
| 2642 | Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) |
| 2643 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 2644 | Instruction Type: CVI_VX_DV |
| 2645 | Execution Slots: SLOT23 |
| 2646 | ========================================================================== */ |
| 2647 | |
| 2648 | #define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) |
| 2649 | |
| 2650 | /* ========================================================================== |
| 2651 | Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) |
| 2652 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 2653 | Instruction Type: CVI_VX_DV |
| 2654 | Execution Slots: SLOT23 |
| 2655 | ========================================================================== */ |
| 2656 | |
| 2657 | #define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) |
| 2658 | |
| 2659 | /* ========================================================================== |
| 2660 | Assembly Syntax: Vdd32.h=vunpack(Vu32.b) |
| 2661 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) |
| 2662 | Instruction Type: CVI_VP_VS |
| 2663 | Execution Slots: SLOT0123 |
| 2664 | ========================================================================== */ |
| 2665 | |
| 2666 | #define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) |
| 2667 | |
| 2668 | /* ========================================================================== |
| 2669 | Assembly Syntax: Vdd32.w=vunpack(Vu32.h) |
| 2670 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) |
| 2671 | Instruction Type: CVI_VP_VS |
| 2672 | Execution Slots: SLOT0123 |
| 2673 | ========================================================================== */ |
| 2674 | |
| 2675 | #define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) |
| 2676 | |
| 2677 | /* ========================================================================== |
| 2678 | Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) |
| 2679 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) |
| 2680 | Instruction Type: CVI_VP_VS |
| 2681 | Execution Slots: SLOT0123 |
| 2682 | ========================================================================== */ |
| 2683 | |
| 2684 | #define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) |
| 2685 | |
| 2686 | /* ========================================================================== |
| 2687 | Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) |
| 2688 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) |
| 2689 | Instruction Type: CVI_VP_VS |
| 2690 | Execution Slots: SLOT0123 |
| 2691 | ========================================================================== */ |
| 2692 | |
| 2693 | #define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) |
| 2694 | |
| 2695 | /* ========================================================================== |
| 2696 | Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) |
| 2697 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) |
| 2698 | Instruction Type: CVI_VP_VS |
| 2699 | Execution Slots: SLOT0123 |
| 2700 | ========================================================================== */ |
| 2701 | |
| 2702 | #define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) |
| 2703 | |
| 2704 | /* ========================================================================== |
| 2705 | Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) |
| 2706 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) |
| 2707 | Instruction Type: CVI_VP_VS |
| 2708 | Execution Slots: SLOT0123 |
| 2709 | ========================================================================== */ |
| 2710 | |
| 2711 | #define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) |
| 2712 | |
| 2713 | /* ========================================================================== |
| 2714 | Assembly Syntax: Vd32=vxor(Vu32,Vv32) |
| 2715 | C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 2716 | Instruction Type: CVI_VA |
| 2717 | Execution Slots: SLOT0123 |
| 2718 | ========================================================================== */ |
| 2719 | |
| 2720 | #define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) |
| 2721 | |
| 2722 | /* ========================================================================== |
| 2723 | Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) |
| 2724 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) |
| 2725 | Instruction Type: CVI_VA_DV |
| 2726 | Execution Slots: SLOT0123 |
| 2727 | ========================================================================== */ |
| 2728 | |
| 2729 | #define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) |
| 2730 | |
| 2731 | /* ========================================================================== |
| 2732 | Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) |
| 2733 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) |
| 2734 | Instruction Type: CVI_VA_DV |
| 2735 | Execution Slots: SLOT0123 |
| 2736 | ========================================================================== */ |
| 2737 | |
| 2738 | #define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) |
| 2739 | |
| 2740 | #if __HVX_ARCH__ >= 62 |
| 2741 | /* ========================================================================== |
| 2742 | Assembly Syntax: Vd32.b=vsplat(Rt32) |
| 2743 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) |
| 2744 | Instruction Type: CVI_VX_LATE |
| 2745 | Execution Slots: SLOT23 |
| 2746 | ========================================================================== */ |
| 2747 | |
| 2748 | #define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) |
| 2749 | #endif |
| 2750 | |
| 2751 | #if __HVX_ARCH__ >= 62 |
| 2752 | /* ========================================================================== |
| 2753 | Assembly Syntax: Vd32.h=vsplat(Rt32) |
| 2754 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) |
| 2755 | Instruction Type: CVI_VX_LATE |
| 2756 | Execution Slots: SLOT23 |
| 2757 | ========================================================================== */ |
| 2758 | |
| 2759 | #define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) |
| 2760 | #endif |
| 2761 | |
| 2762 | #if __HVX_ARCH__ >= 62 |
| 2763 | /* ========================================================================== |
| 2764 | Assembly Syntax: Qd4=vsetq2(Rt32) |
| 2765 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) |
| 2766 | Instruction Type: CVI_VP |
| 2767 | Execution Slots: SLOT0123 |
| 2768 | ========================================================================== */ |
| 2769 | |
| 2770 | #define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) |
| 2771 | #endif |
| 2772 | |
| 2773 | #if __HVX_ARCH__ >= 62 |
| 2774 | /* ========================================================================== |
| 2775 | Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) |
| 2776 | C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 2777 | Instruction Type: CVI_VA_DV |
| 2778 | Execution Slots: SLOT0123 |
| 2779 | ========================================================================== */ |
| 2780 | |
| 2781 | #define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 2782 | #endif |
| 2783 | |
| 2784 | #if __HVX_ARCH__ >= 62 |
| 2785 | /* ========================================================================== |
| 2786 | Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) |
| 2787 | C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 2788 | Instruction Type: CVI_VA_DV |
| 2789 | Execution Slots: SLOT0123 |
| 2790 | ========================================================================== */ |
| 2791 | |
| 2792 | #define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
| 2793 | #endif |
| 2794 | |
| 2795 | #if __HVX_ARCH__ >= 62 |
| 2796 | /* ========================================================================== |
| 2797 | Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat |
| 2798 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2799 | Instruction Type: CVI_VA |
| 2800 | Execution Slots: SLOT0123 |
| 2801 | ========================================================================== */ |
| 2802 | |
| 2803 | #define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) |
| 2804 | #endif |
| 2805 | |
| 2806 | #if __HVX_ARCH__ >= 62 |
| 2807 | /* ========================================================================== |
| 2808 | Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat |
| 2809 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2810 | Instruction Type: CVI_VA_DV |
| 2811 | Execution Slots: SLOT0123 |
| 2812 | ========================================================================== */ |
| 2813 | |
| 2814 | #define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) |
| 2815 | #endif |
| 2816 | |
| 2817 | #if __HVX_ARCH__ >= 62 |
| 2818 | /* ========================================================================== |
| 2819 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry |
| 2820 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) |
| 2821 | Instruction Type: CVI_VA |
| 2822 | Execution Slots: SLOT0123 |
| 2823 | ========================================================================== */ |
| 2824 | |
| 2825 | #define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) |
| 2826 | #endif |
| 2827 | |
| 2828 | #if __HVX_ARCH__ >= 62 |
| 2829 | /* ========================================================================== |
| 2830 | Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) |
| 2831 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2832 | Instruction Type: CVI_VS |
| 2833 | Execution Slots: SLOT0123 |
| 2834 | ========================================================================== */ |
| 2835 | |
| 2836 | #define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) |
| 2837 | #endif |
| 2838 | |
| 2839 | #if __HVX_ARCH__ >= 62 |
| 2840 | /* ========================================================================== |
| 2841 | Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) |
| 2842 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2843 | Instruction Type: CVI_VS |
| 2844 | Execution Slots: SLOT0123 |
| 2845 | ========================================================================== */ |
| 2846 | |
| 2847 | #define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) |
| 2848 | #endif |
| 2849 | |
| 2850 | #if __HVX_ARCH__ >= 62 |
| 2851 | /* ========================================================================== |
| 2852 | Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) |
| 2853 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2854 | Instruction Type: CVI_VX_DV |
| 2855 | Execution Slots: SLOT23 |
| 2856 | ========================================================================== */ |
| 2857 | |
| 2858 | #define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) |
| 2859 | #endif |
| 2860 | |
| 2861 | #if __HVX_ARCH__ >= 62 |
| 2862 | /* ========================================================================== |
| 2863 | Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) |
| 2864 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2865 | Instruction Type: CVI_VX_DV |
| 2866 | Execution Slots: SLOT23 |
| 2867 | ========================================================================== */ |
| 2868 | |
| 2869 | #define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) |
| 2870 | #endif |
| 2871 | |
| 2872 | #if __HVX_ARCH__ >= 62 |
| 2873 | /* ========================================================================== |
| 2874 | Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat |
| 2875 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2876 | Instruction Type: CVI_VA |
| 2877 | Execution Slots: SLOT0123 |
| 2878 | ========================================================================== */ |
| 2879 | |
| 2880 | #define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) |
| 2881 | #endif |
| 2882 | |
| 2883 | #if __HVX_ARCH__ >= 62 |
| 2884 | /* ========================================================================== |
| 2885 | Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) |
| 2886 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2887 | Instruction Type: CVI_VX_DV |
| 2888 | Execution Slots: SLOT23 |
| 2889 | ========================================================================== */ |
| 2890 | |
| 2891 | #define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) |
| 2892 | #endif |
| 2893 | |
| 2894 | #if __HVX_ARCH__ >= 62 |
| 2895 | /* ========================================================================== |
| 2896 | Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat |
| 2897 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2898 | Instruction Type: CVI_VA |
| 2899 | Execution Slots: SLOT0123 |
| 2900 | ========================================================================== */ |
| 2901 | |
| 2902 | #define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) |
| 2903 | #endif |
| 2904 | |
| 2905 | #if __HVX_ARCH__ >= 62 |
| 2906 | /* ========================================================================== |
| 2907 | Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat |
| 2908 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2909 | Instruction Type: CVI_VA_DV |
| 2910 | Execution Slots: SLOT0123 |
| 2911 | ========================================================================== */ |
| 2912 | |
| 2913 | #define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) |
| 2914 | #endif |
| 2915 | |
| 2916 | #if __HVX_ARCH__ >= 62 |
| 2917 | /* ========================================================================== |
| 2918 | Assembly Syntax: Vd32=vand(!Qu4,Rt32) |
| 2919 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) |
| 2920 | Instruction Type: CVI_VX_LATE |
| 2921 | Execution Slots: SLOT23 |
| 2922 | ========================================================================== */ |
| 2923 | |
| 2924 | #define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
| 2925 | #endif |
| 2926 | |
| 2927 | #if __HVX_ARCH__ >= 62 |
| 2928 | /* ========================================================================== |
| 2929 | Assembly Syntax: Vx32|=vand(!Qu4,Rt32) |
| 2930 | C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) |
| 2931 | Instruction Type: CVI_VX_LATE |
| 2932 | Execution Slots: SLOT23 |
| 2933 | ========================================================================== */ |
| 2934 | |
| 2935 | #define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
| 2936 | #endif |
| 2937 | |
| 2938 | #if __HVX_ARCH__ >= 62 |
| 2939 | /* ========================================================================== |
| 2940 | Assembly Syntax: Vd32=vand(!Qv4,Vu32) |
| 2941 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) |
| 2942 | Instruction Type: CVI_VA |
| 2943 | Execution Slots: SLOT0123 |
| 2944 | ========================================================================== */ |
| 2945 | |
| 2946 | #define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) |
| 2947 | #endif |
| 2948 | |
| 2949 | #if __HVX_ARCH__ >= 62 |
| 2950 | /* ========================================================================== |
| 2951 | Assembly Syntax: Vd32=vand(Qv4,Vu32) |
| 2952 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) |
| 2953 | Instruction Type: CVI_VA |
| 2954 | Execution Slots: SLOT0123 |
| 2955 | ========================================================================== */ |
| 2956 | |
| 2957 | #define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) |
| 2958 | #endif |
| 2959 | |
| 2960 | #if __HVX_ARCH__ >= 62 |
| 2961 | /* ========================================================================== |
| 2962 | Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat |
| 2963 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 2964 | Instruction Type: CVI_VS |
| 2965 | Execution Slots: SLOT0123 |
| 2966 | ========================================================================== */ |
| 2967 | |
| 2968 | #define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) |
| 2969 | #endif |
| 2970 | |
| 2971 | #if __HVX_ARCH__ >= 62 |
| 2972 | /* ========================================================================== |
| 2973 | Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat |
| 2974 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 2975 | Instruction Type: CVI_VS |
| 2976 | Execution Slots: SLOT0123 |
| 2977 | ========================================================================== */ |
| 2978 | |
| 2979 | #define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) |
| 2980 | #endif |
| 2981 | |
| 2982 | #if __HVX_ARCH__ >= 62 |
| 2983 | /* ========================================================================== |
| 2984 | Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat |
| 2985 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 2986 | Instruction Type: CVI_VS |
| 2987 | Execution Slots: SLOT0123 |
| 2988 | ========================================================================== */ |
| 2989 | |
| 2990 | #define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) |
| 2991 | #endif |
| 2992 | |
| 2993 | #if __HVX_ARCH__ >= 62 |
| 2994 | /* ========================================================================== |
| 2995 | Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) |
| 2996 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) |
| 2997 | Instruction Type: CVI_VS |
| 2998 | Execution Slots: SLOT0123 |
| 2999 | ========================================================================== */ |
| 3000 | |
| 3001 | #define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) |
| 3002 | #endif |
| 3003 | |
| 3004 | #if __HVX_ARCH__ >= 62 |
| 3005 | /* ========================================================================== |
| 3006 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch |
| 3007 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3008 | Instruction Type: CVI_VP |
| 3009 | Execution Slots: SLOT0123 |
| 3010 | ========================================================================== */ |
| 3011 | |
| 3012 | #define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) |
| 3013 | #endif |
| 3014 | |
| 3015 | #if __HVX_ARCH__ >= 62 |
| 3016 | /* ========================================================================== |
| 3017 | Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) |
| 3018 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3019 | Instruction Type: CVI_VP_VS |
| 3020 | Execution Slots: SLOT0123 |
| 3021 | ========================================================================== */ |
| 3022 | |
| 3023 | #define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) |
| 3024 | #endif |
| 3025 | |
| 3026 | #if __HVX_ARCH__ >= 62 |
| 3027 | /* ========================================================================== |
| 3028 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) |
| 3029 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3030 | Instruction Type: CVI_VP |
| 3031 | Execution Slots: SLOT0123 |
| 3032 | ========================================================================== */ |
| 3033 | |
| 3034 | #define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) |
| 3035 | #endif |
| 3036 | |
| 3037 | #if __HVX_ARCH__ >= 62 |
| 3038 | /* ========================================================================== |
| 3039 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch |
| 3040 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3041 | Instruction Type: CVI_VP_VS |
| 3042 | Execution Slots: SLOT0123 |
| 3043 | ========================================================================== */ |
| 3044 | |
| 3045 | #define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) |
| 3046 | #endif |
| 3047 | |
| 3048 | #if __HVX_ARCH__ >= 62 |
| 3049 | /* ========================================================================== |
| 3050 | Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) |
| 3051 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3052 | Instruction Type: CVI_VP_VS |
| 3053 | Execution Slots: SLOT0123 |
| 3054 | ========================================================================== */ |
| 3055 | |
| 3056 | #define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) |
| 3057 | #endif |
| 3058 | |
| 3059 | #if __HVX_ARCH__ >= 62 |
| 3060 | /* ========================================================================== |
| 3061 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) |
| 3062 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3063 | Instruction Type: CVI_VP_VS |
| 3064 | Execution Slots: SLOT0123 |
| 3065 | ========================================================================== */ |
| 3066 | |
| 3067 | #define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) |
| 3068 | #endif |
| 3069 | |
| 3070 | #if __HVX_ARCH__ >= 62 |
| 3071 | /* ========================================================================== |
| 3072 | Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) |
| 3073 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3074 | Instruction Type: CVI_VA |
| 3075 | Execution Slots: SLOT0123 |
| 3076 | ========================================================================== */ |
| 3077 | |
| 3078 | #define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) |
| 3079 | #endif |
| 3080 | |
| 3081 | #if __HVX_ARCH__ >= 62 |
| 3082 | /* ========================================================================== |
| 3083 | Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) |
| 3084 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3085 | Instruction Type: CVI_VA |
| 3086 | Execution Slots: SLOT0123 |
| 3087 | ========================================================================== */ |
| 3088 | |
| 3089 | #define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) |
| 3090 | #endif |
| 3091 | |
| 3092 | #if __HVX_ARCH__ >= 62 |
| 3093 | /* ========================================================================== |
| 3094 | Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) |
| 3095 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 3096 | Instruction Type: CVI_VX_DV |
| 3097 | Execution Slots: SLOT23 |
| 3098 | ========================================================================== */ |
| 3099 | |
| 3100 | #define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) |
| 3101 | #endif |
| 3102 | |
| 3103 | #if __HVX_ARCH__ >= 62 |
| 3104 | /* ========================================================================== |
| 3105 | Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) |
| 3106 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 3107 | Instruction Type: CVI_VX_DV |
| 3108 | Execution Slots: SLOT23 |
| 3109 | ========================================================================== */ |
| 3110 | |
| 3111 | #define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) |
| 3112 | #endif |
| 3113 | |
| 3114 | #if __HVX_ARCH__ >= 62 |
| 3115 | /* ========================================================================== |
| 3116 | Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) |
| 3117 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 3118 | Instruction Type: CVI_VX_DV |
| 3119 | Execution Slots: SLOT23 |
| 3120 | ========================================================================== */ |
| 3121 | |
| 3122 | #define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) |
| 3123 | #endif |
| 3124 | |
| 3125 | #if __HVX_ARCH__ >= 62 |
| 3126 | /* ========================================================================== |
| 3127 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) |
| 3128 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) |
| 3129 | Instruction Type: CVI_VX |
| 3130 | Execution Slots: SLOT23 |
| 3131 | ========================================================================== */ |
| 3132 | |
| 3133 | #define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) |
| 3134 | #endif |
| 3135 | |
| 3136 | #if __HVX_ARCH__ >= 62 |
| 3137 | /* ========================================================================== |
| 3138 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) |
| 3139 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3140 | Instruction Type: CVI_VX |
| 3141 | Execution Slots: SLOT23 |
| 3142 | ========================================================================== */ |
| 3143 | |
| 3144 | #define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) |
| 3145 | #endif |
| 3146 | |
| 3147 | #if __HVX_ARCH__ >= 62 |
| 3148 | /* ========================================================================== |
| 3149 | Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) |
| 3150 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 3151 | Instruction Type: CVI_VX_DV |
| 3152 | Execution Slots: SLOT23 |
| 3153 | ========================================================================== */ |
| 3154 | |
| 3155 | #define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) |
| 3156 | #endif |
| 3157 | |
| 3158 | #if __HVX_ARCH__ >= 62 |
| 3159 | /* ========================================================================== |
| 3160 | Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat |
| 3161 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3162 | Instruction Type: CVI_VS |
| 3163 | Execution Slots: SLOT0123 |
| 3164 | ========================================================================== */ |
| 3165 | |
| 3166 | #define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) |
| 3167 | #endif |
| 3168 | |
| 3169 | #if __HVX_ARCH__ >= 62 |
| 3170 | /* ========================================================================== |
| 3171 | Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat |
| 3172 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3173 | Instruction Type: CVI_VS |
| 3174 | Execution Slots: SLOT0123 |
| 3175 | ========================================================================== */ |
| 3176 | |
| 3177 | #define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) |
| 3178 | #endif |
| 3179 | |
| 3180 | #if __HVX_ARCH__ >= 62 |
| 3181 | /* ========================================================================== |
| 3182 | Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) |
| 3183 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 3184 | Instruction Type: CVI_VA |
| 3185 | Execution Slots: SLOT0123 |
| 3186 | ========================================================================== */ |
| 3187 | |
| 3188 | #define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) |
| 3189 | #endif |
| 3190 | |
| 3191 | #if __HVX_ARCH__ >= 62 |
| 3192 | /* ========================================================================== |
| 3193 | Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat |
| 3194 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3195 | Instruction Type: CVI_VA |
| 3196 | Execution Slots: SLOT0123 |
| 3197 | ========================================================================== */ |
| 3198 | |
| 3199 | #define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) |
| 3200 | #endif |
| 3201 | |
| 3202 | #if __HVX_ARCH__ >= 62 |
| 3203 | /* ========================================================================== |
| 3204 | Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat |
| 3205 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3206 | Instruction Type: CVI_VA_DV |
| 3207 | Execution Slots: SLOT0123 |
| 3208 | ========================================================================== */ |
| 3209 | |
| 3210 | #define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) |
| 3211 | #endif |
| 3212 | |
| 3213 | #if __HVX_ARCH__ >= 62 |
| 3214 | /* ========================================================================== |
| 3215 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry |
| 3216 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) |
| 3217 | Instruction Type: CVI_VA |
| 3218 | Execution Slots: SLOT0123 |
| 3219 | ========================================================================== */ |
| 3220 | |
| 3221 | #define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) |
| 3222 | #endif |
| 3223 | |
| 3224 | #if __HVX_ARCH__ >= 62 |
| 3225 | /* ========================================================================== |
| 3226 | Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat |
| 3227 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3228 | Instruction Type: CVI_VA |
| 3229 | Execution Slots: SLOT0123 |
| 3230 | ========================================================================== */ |
| 3231 | |
| 3232 | #define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) |
| 3233 | #endif |
| 3234 | |
| 3235 | #if __HVX_ARCH__ >= 62 |
| 3236 | /* ========================================================================== |
| 3237 | Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat |
| 3238 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3239 | Instruction Type: CVI_VA |
| 3240 | Execution Slots: SLOT0123 |
| 3241 | ========================================================================== */ |
| 3242 | |
| 3243 | #define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) |
| 3244 | #endif |
| 3245 | |
| 3246 | #if __HVX_ARCH__ >= 62 |
| 3247 | /* ========================================================================== |
| 3248 | Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat |
| 3249 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3250 | Instruction Type: CVI_VA_DV |
| 3251 | Execution Slots: SLOT0123 |
| 3252 | ========================================================================== */ |
| 3253 | |
| 3254 | #define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) |
| 3255 | #endif |
| 3256 | |
| 3257 | #if __HVX_ARCH__ >= 65 |
| 3258 | /* ========================================================================== |
| 3259 | Assembly Syntax: Vd32.b=vabs(Vu32.b) |
| 3260 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) |
| 3261 | Instruction Type: CVI_VA |
| 3262 | Execution Slots: SLOT0123 |
| 3263 | ========================================================================== */ |
| 3264 | |
| 3265 | #define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) |
| 3266 | #endif |
| 3267 | |
| 3268 | #if __HVX_ARCH__ >= 65 |
| 3269 | /* ========================================================================== |
| 3270 | Assembly Syntax: Vd32.b=vabs(Vu32.b):sat |
| 3271 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) |
| 3272 | Instruction Type: CVI_VA |
| 3273 | Execution Slots: SLOT0123 |
| 3274 | ========================================================================== */ |
| 3275 | |
| 3276 | #define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) |
| 3277 | #endif |
| 3278 | |
| 3279 | #if __HVX_ARCH__ >= 65 |
| 3280 | /* ========================================================================== |
| 3281 | Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) |
| 3282 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3283 | Instruction Type: CVI_VS |
| 3284 | Execution Slots: SLOT0123 |
| 3285 | ========================================================================== */ |
| 3286 | |
| 3287 | #define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) |
| 3288 | #endif |
| 3289 | |
| 3290 | #if __HVX_ARCH__ >= 65 |
| 3291 | /* ========================================================================== |
| 3292 | Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) |
| 3293 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3294 | Instruction Type: CVI_VS |
| 3295 | Execution Slots: SLOT0123 |
| 3296 | ========================================================================== */ |
| 3297 | |
| 3298 | #define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) |
| 3299 | #endif |
| 3300 | |
| 3301 | #if __HVX_ARCH__ >= 65 |
| 3302 | /* ========================================================================== |
| 3303 | Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat |
| 3304 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3305 | Instruction Type: CVI_VS |
| 3306 | Execution Slots: SLOT0123 |
| 3307 | ========================================================================== */ |
| 3308 | |
| 3309 | #define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) |
| 3310 | #endif |
| 3311 | |
| 3312 | #if __HVX_ARCH__ >= 65 |
| 3313 | /* ========================================================================== |
| 3314 | Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat |
| 3315 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3316 | Instruction Type: CVI_VS |
| 3317 | Execution Slots: SLOT0123 |
| 3318 | ========================================================================== */ |
| 3319 | |
| 3320 | #define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) |
| 3321 | #endif |
| 3322 | |
| 3323 | #if __HVX_ARCH__ >= 65 |
| 3324 | /* ========================================================================== |
| 3325 | Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat |
| 3326 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3327 | Instruction Type: CVI_VS |
| 3328 | Execution Slots: SLOT0123 |
| 3329 | ========================================================================== */ |
| 3330 | |
| 3331 | #define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) |
| 3332 | #endif |
| 3333 | |
| 3334 | #if __HVX_ARCH__ >= 65 |
| 3335 | /* ========================================================================== |
| 3336 | Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) |
| 3337 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3338 | Instruction Type: CVI_VA |
| 3339 | Execution Slots: SLOT0123 |
| 3340 | ========================================================================== */ |
| 3341 | |
| 3342 | #define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) |
| 3343 | #endif |
| 3344 | |
| 3345 | #if __HVX_ARCH__ >= 65 |
| 3346 | /* ========================================================================== |
| 3347 | Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd |
| 3348 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 3349 | Instruction Type: CVI_VA |
| 3350 | Execution Slots: SLOT0123 |
| 3351 | ========================================================================== */ |
| 3352 | |
| 3353 | #define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) |
| 3354 | #endif |
| 3355 | |
| 3356 | #if __HVX_ARCH__ >= 65 |
| 3357 | /* ========================================================================== |
| 3358 | Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) |
| 3359 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 3360 | Instruction Type: CVI_VA |
| 3361 | Execution Slots: SLOT0123 |
| 3362 | ========================================================================== */ |
| 3363 | |
| 3364 | #define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) |
| 3365 | #endif |
| 3366 | |
| 3367 | #if __HVX_ARCH__ >= 65 |
| 3368 | /* ========================================================================== |
| 3369 | Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd |
| 3370 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 3371 | Instruction Type: CVI_VA |
| 3372 | Execution Slots: SLOT0123 |
| 3373 | ========================================================================== */ |
| 3374 | |
| 3375 | #define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) |
| 3376 | #endif |
| 3377 | |
| 3378 | #if __HVX_ARCH__ >= 65 |
| 3379 | /* ========================================================================== |
| 3380 | Assembly Syntax: Vdd32=#0 |
| 3381 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() |
| 3382 | Instruction Type: MAPPING |
| 3383 | Execution Slots: SLOT0123 |
| 3384 | ========================================================================== */ |
| 3385 | |
| 3386 | #define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() |
| 3387 | #endif |
| 3388 | |
| 3389 | #if __HVX_ARCH__ >= 65 |
| 3390 | /* ========================================================================== |
| 3391 | Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h |
| 3392 | C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 3393 | Instruction Type: CVI_GATHER |
| 3394 | Execution Slots: SLOT01 |
| 3395 | ========================================================================== */ |
| 3396 | |
| 3397 | #define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) |
| 3398 | #endif |
| 3399 | |
| 3400 | #if __HVX_ARCH__ >= 65 |
| 3401 | /* ========================================================================== |
| 3402 | Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h |
| 3403 | C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 3404 | Instruction Type: CVI_GATHER |
| 3405 | Execution Slots: SLOT01 |
| 3406 | ========================================================================== */ |
| 3407 | |
| 3408 | #define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) |
| 3409 | #endif |
| 3410 | |
| 3411 | #if __HVX_ARCH__ >= 65 |
| 3412 | /* ========================================================================== |
| 3413 | Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h |
| 3414 | C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) |
| 3415 | Instruction Type: CVI_GATHER_DV |
| 3416 | Execution Slots: SLOT01 |
| 3417 | ========================================================================== */ |
| 3418 | |
| 3419 | #define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) |
| 3420 | #endif |
| 3421 | |
| 3422 | #if __HVX_ARCH__ >= 65 |
| 3423 | /* ========================================================================== |
| 3424 | Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h |
| 3425 | C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) |
| 3426 | Instruction Type: CVI_GATHER_DV |
| 3427 | Execution Slots: SLOT01 |
| 3428 | ========================================================================== */ |
| 3429 | |
| 3430 | #define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) |
| 3431 | #endif |
| 3432 | |
| 3433 | #if __HVX_ARCH__ >= 65 |
| 3434 | /* ========================================================================== |
| 3435 | Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w |
| 3436 | C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 3437 | Instruction Type: CVI_GATHER |
| 3438 | Execution Slots: SLOT01 |
| 3439 | ========================================================================== */ |
| 3440 | |
| 3441 | #define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) |
| 3442 | #endif |
| 3443 | |
| 3444 | #if __HVX_ARCH__ >= 65 |
| 3445 | /* ========================================================================== |
| 3446 | Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w |
| 3447 | C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 3448 | Instruction Type: CVI_GATHER |
| 3449 | Execution Slots: SLOT01 |
| 3450 | ========================================================================== */ |
| 3451 | |
| 3452 | #define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) |
| 3453 | #endif |
| 3454 | |
| 3455 | #if __HVX_ARCH__ >= 65 |
| 3456 | /* ========================================================================== |
| 3457 | Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) |
| 3458 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) |
| 3459 | Instruction Type: CVI_VX_DV |
| 3460 | Execution Slots: SLOT2 |
| 3461 | ========================================================================== */ |
| 3462 | |
| 3463 | #define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) |
| 3464 | #endif |
| 3465 | |
| 3466 | #if __HVX_ARCH__ >= 65 |
| 3467 | /* ========================================================================== |
| 3468 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) |
| 3469 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) |
| 3470 | Instruction Type: CVI_VX_DV |
| 3471 | Execution Slots: SLOT23 |
| 3472 | ========================================================================== */ |
| 3473 | |
| 3474 | #define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) |
| 3475 | #endif |
| 3476 | |
| 3477 | #if __HVX_ARCH__ >= 65 |
| 3478 | /* ========================================================================== |
| 3479 | Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) |
| 3480 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 3481 | Instruction Type: CVI_VX_DV |
| 3482 | Execution Slots: SLOT23 |
| 3483 | ========================================================================== */ |
| 3484 | |
| 3485 | #define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) |
| 3486 | #endif |
| 3487 | |
| 3488 | #if __HVX_ARCH__ >= 65 |
| 3489 | /* ========================================================================== |
| 3490 | Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat |
| 3491 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
| 3492 | Instruction Type: CVI_VX_DV |
| 3493 | Execution Slots: SLOT2 |
| 3494 | ========================================================================== */ |
| 3495 | |
| 3496 | #define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) |
| 3497 | #endif |
| 3498 | |
| 3499 | #if __HVX_ARCH__ >= 65 |
| 3500 | /* ========================================================================== |
| 3501 | Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat |
| 3502 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
| 3503 | Instruction Type: CVI_VX_DV |
| 3504 | Execution Slots: SLOT2 |
| 3505 | ========================================================================== */ |
| 3506 | |
| 3507 | #define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) |
| 3508 | #endif |
| 3509 | |
| 3510 | #if __HVX_ARCH__ >= 65 |
| 3511 | /* ========================================================================== |
| 3512 | Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat |
| 3513 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
| 3514 | Instruction Type: CVI_VX_DV |
| 3515 | Execution Slots: SLOT2 |
| 3516 | ========================================================================== */ |
| 3517 | |
| 3518 | #define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) |
| 3519 | #endif |
| 3520 | |
| 3521 | #if __HVX_ARCH__ >= 65 |
| 3522 | /* ========================================================================== |
| 3523 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) |
| 3524 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 3525 | Instruction Type: CVI_VX_DV |
| 3526 | Execution Slots: SLOT23 |
| 3527 | ========================================================================== */ |
| 3528 | |
| 3529 | #define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) |
| 3530 | #endif |
| 3531 | |
| 3532 | #if __HVX_ARCH__ >= 65 |
| 3533 | /* ========================================================================== |
| 3534 | Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) |
| 3535 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) |
| 3536 | Instruction Type: CVI_VX |
| 3537 | Execution Slots: SLOT23 |
| 3538 | ========================================================================== */ |
| 3539 | |
| 3540 | #define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) |
| 3541 | #endif |
| 3542 | |
| 3543 | #if __HVX_ARCH__ >= 65 |
| 3544 | /* ========================================================================== |
| 3545 | Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) |
| 3546 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3547 | Instruction Type: CVI_VX |
| 3548 | Execution Slots: SLOT23 |
| 3549 | ========================================================================== */ |
| 3550 | |
| 3551 | #define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) |
| 3552 | #endif |
| 3553 | |
| 3554 | #if __HVX_ARCH__ >= 65 |
| 3555 | /* ========================================================================== |
| 3556 | Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) |
| 3557 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3558 | Instruction Type: CVI_VA |
| 3559 | Execution Slots: SLOT0123 |
| 3560 | ========================================================================== */ |
| 3561 | |
| 3562 | #define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) |
| 3563 | #endif |
| 3564 | |
| 3565 | #if __HVX_ARCH__ >= 65 |
| 3566 | /* ========================================================================== |
| 3567 | Assembly Syntax: Vd32.b=prefixsum(Qv4) |
| 3568 | C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) |
| 3569 | Instruction Type: CVI_VS |
| 3570 | Execution Slots: SLOT0123 |
| 3571 | ========================================================================== */ |
| 3572 | |
| 3573 | #define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) |
| 3574 | #endif |
| 3575 | |
| 3576 | #if __HVX_ARCH__ >= 65 |
| 3577 | /* ========================================================================== |
| 3578 | Assembly Syntax: Vd32.h=prefixsum(Qv4) |
| 3579 | C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) |
| 3580 | Instruction Type: CVI_VS |
| 3581 | Execution Slots: SLOT0123 |
| 3582 | ========================================================================== */ |
| 3583 | |
| 3584 | #define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) |
| 3585 | #endif |
| 3586 | |
| 3587 | #if __HVX_ARCH__ >= 65 |
| 3588 | /* ========================================================================== |
| 3589 | Assembly Syntax: Vd32.w=prefixsum(Qv4) |
| 3590 | C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) |
| 3591 | Instruction Type: CVI_VS |
| 3592 | Execution Slots: SLOT0123 |
| 3593 | ========================================================================== */ |
| 3594 | |
| 3595 | #define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) |
| 3596 | #endif |
| 3597 | |
| 3598 | #if __HVX_ARCH__ >= 65 |
| 3599 | /* ========================================================================== |
| 3600 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 |
| 3601 | C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 3602 | Instruction Type: CVI_SCATTER |
| 3603 | Execution Slots: SLOT0 |
| 3604 | ========================================================================== */ |
| 3605 | |
| 3606 | #define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) |
| 3607 | #endif |
| 3608 | |
| 3609 | #if __HVX_ARCH__ >= 65 |
| 3610 | /* ========================================================================== |
| 3611 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 |
| 3612 | C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 3613 | Instruction Type: CVI_SCATTER |
| 3614 | Execution Slots: SLOT0 |
| 3615 | ========================================================================== */ |
| 3616 | |
| 3617 | #define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) |
| 3618 | #endif |
| 3619 | |
| 3620 | #if __HVX_ARCH__ >= 65 |
| 3621 | /* ========================================================================== |
| 3622 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 |
| 3623 | C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 3624 | Instruction Type: CVI_SCATTER |
| 3625 | Execution Slots: SLOT0 |
| 3626 | ========================================================================== */ |
| 3627 | |
| 3628 | #define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) |
| 3629 | #endif |
| 3630 | |
| 3631 | #if __HVX_ARCH__ >= 65 |
| 3632 | /* ========================================================================== |
| 3633 | Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 |
| 3634 | C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
| 3635 | Instruction Type: CVI_SCATTER_DV |
| 3636 | Execution Slots: SLOT0 |
| 3637 | ========================================================================== */ |
| 3638 | |
| 3639 | #define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) |
| 3640 | #endif |
| 3641 | |
| 3642 | #if __HVX_ARCH__ >= 65 |
| 3643 | /* ========================================================================== |
| 3644 | Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 |
| 3645 | C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
| 3646 | Instruction Type: CVI_SCATTER_DV |
| 3647 | Execution Slots: SLOT0 |
| 3648 | ========================================================================== */ |
| 3649 | |
| 3650 | #define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) |
| 3651 | #endif |
| 3652 | |
| 3653 | #if __HVX_ARCH__ >= 65 |
| 3654 | /* ========================================================================== |
| 3655 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 |
| 3656 | C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
| 3657 | Instruction Type: CVI_SCATTER_DV |
| 3658 | Execution Slots: SLOT0 |
| 3659 | ========================================================================== */ |
| 3660 | |
| 3661 | #define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) |
| 3662 | #endif |
| 3663 | |
| 3664 | #if __HVX_ARCH__ >= 65 |
| 3665 | /* ========================================================================== |
| 3666 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 |
| 3667 | C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 3668 | Instruction Type: CVI_SCATTER |
| 3669 | Execution Slots: SLOT0 |
| 3670 | ========================================================================== */ |
| 3671 | |
| 3672 | #define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) |
| 3673 | #endif |
| 3674 | |
| 3675 | #if __HVX_ARCH__ >= 65 |
| 3676 | /* ========================================================================== |
| 3677 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 |
| 3678 | C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 3679 | Instruction Type: CVI_SCATTER |
| 3680 | Execution Slots: SLOT0 |
| 3681 | ========================================================================== */ |
| 3682 | |
| 3683 | #define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) |
| 3684 | #endif |
| 3685 | |
| 3686 | #if __HVX_ARCH__ >= 65 |
| 3687 | /* ========================================================================== |
| 3688 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 |
| 3689 | C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 3690 | Instruction Type: CVI_SCATTER |
| 3691 | Execution Slots: SLOT0 |
| 3692 | ========================================================================== */ |
| 3693 | |
| 3694 | #define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) |
| 3695 | #endif |
| 3696 | |
| 3697 | #if __HVX_ARCH__ >= 66 |
| 3698 | /* ========================================================================== |
| 3699 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat |
| 3700 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) |
| 3701 | Instruction Type: CVI_VA |
| 3702 | Execution Slots: SLOT0123 |
| 3703 | ========================================================================== */ |
| 3704 | |
| 3705 | #define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) |
| 3706 | #endif |
| 3707 | |
| 3708 | #if __HVX_ARCH__ >= 66 |
| 3709 | /* ========================================================================== |
| 3710 | Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) |
| 3711 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 3712 | Instruction Type: CVI_VP_VS |
| 3713 | Execution Slots: SLOT0123 |
| 3714 | ========================================================================== */ |
| 3715 | |
| 3716 | #define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) |
| 3717 | #endif |
| 3718 | |
| 3719 | #if __HVX_ARCH__ >= 66 |
| 3720 | /* ========================================================================== |
| 3721 | Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) |
| 3722 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 3723 | Instruction Type: CVI_VS |
| 3724 | Execution Slots: SLOT0123 |
| 3725 | ========================================================================== */ |
| 3726 | |
| 3727 | #define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) |
| 3728 | #endif |
| 3729 | |
| 3730 | #if __HVX_ARCH__ >= 66 |
| 3731 | /* ========================================================================== |
| 3732 | Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) |
| 3733 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 3734 | Instruction Type: CVI_VA |
| 3735 | Execution Slots: SLOT0123 |
| 3736 | ========================================================================== */ |
| 3737 | |
| 3738 | #define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) |
| 3739 | #endif |
| 3740 | |
| 3741 | #if __HVX_ARCH__ >= 68 |
| 3742 | /* ========================================================================== |
| 3743 | Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h |
| 3744 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 3745 | Instruction Type: CVI_VX_DV |
| 3746 | Execution Slots: SLOT23 |
| 3747 | ========================================================================== */ |
| 3748 | |
| 3749 | #define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) |
| 3750 | #endif |
| 3751 | |
| 3752 | #if __HVX_ARCH__ >= 68 |
| 3753 | /* ========================================================================== |
| 3754 | Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h |
| 3755 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 3756 | Instruction Type: CVI_VX_DV |
| 3757 | Execution Slots: SLOT23 |
| 3758 | ========================================================================== */ |
| 3759 | |
| 3760 | #define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) |
| 3761 | #endif |
| 3762 | |
| 3763 | #if __HVX_ARCH__ >= 68 |
| 3764 | /* ========================================================================== |
| 3765 | Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v |
| 3766 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 3767 | Instruction Type: CVI_VX_DV |
| 3768 | Execution Slots: SLOT23 |
| 3769 | ========================================================================== */ |
| 3770 | |
| 3771 | #define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) |
| 3772 | #endif |
| 3773 | |
| 3774 | #if __HVX_ARCH__ >= 68 |
| 3775 | /* ========================================================================== |
| 3776 | Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v |
| 3777 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 3778 | Instruction Type: CVI_VX_DV |
| 3779 | Execution Slots: SLOT23 |
| 3780 | ========================================================================== */ |
| 3781 | |
| 3782 | #define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) |
| 3783 | #endif |
| 3784 | |
| 3785 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3786 | /* ========================================================================== |
| 3787 | Assembly Syntax: Vd32.hf=vabs(Vu32.hf) |
| 3788 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu) |
| 3789 | Instruction Type: CVI_VX_LATE |
| 3790 | Execution Slots: SLOT23 |
| 3791 | ========================================================================== */ |
| 3792 | |
| 3793 | #define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu) |
| 3794 | #endif |
| 3795 | |
| 3796 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3797 | /* ========================================================================== |
| 3798 | Assembly Syntax: Vd32.sf=vabs(Vu32.sf) |
| 3799 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu) |
| 3800 | Instruction Type: CVI_VX_LATE |
| 3801 | Execution Slots: SLOT23 |
| 3802 | ========================================================================== */ |
| 3803 | |
| 3804 | #define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu) |
| 3805 | #endif |
| 3806 | |
| 3807 | #if __HVX_ARCH__ >= 68 |
| 3808 | /* ========================================================================== |
| 3809 | Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf) |
| 3810 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 3811 | Instruction Type: CVI_VS |
| 3812 | Execution Slots: SLOT0123 |
| 3813 | ========================================================================== */ |
| 3814 | |
| 3815 | #define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv) |
| 3816 | #endif |
| 3817 | |
| 3818 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3819 | /* ========================================================================== |
| 3820 | Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf) |
| 3821 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 3822 | Instruction Type: CVI_VX |
| 3823 | Execution Slots: SLOT23 |
| 3824 | ========================================================================== */ |
| 3825 | |
| 3826 | #define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv) |
| 3827 | #endif |
| 3828 | |
| 3829 | #if __HVX_ARCH__ >= 68 |
| 3830 | /* ========================================================================== |
| 3831 | Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16) |
| 3832 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
| 3833 | Instruction Type: CVI_VS |
| 3834 | Execution Slots: SLOT0123 |
| 3835 | ========================================================================== */ |
| 3836 | |
| 3837 | #define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv) |
| 3838 | #endif |
| 3839 | |
| 3840 | #if __HVX_ARCH__ >= 68 |
| 3841 | /* ========================================================================== |
| 3842 | Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf) |
| 3843 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
| 3844 | Instruction Type: CVI_VS |
| 3845 | Execution Slots: SLOT0123 |
| 3846 | ========================================================================== */ |
| 3847 | |
| 3848 | #define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv) |
| 3849 | #endif |
| 3850 | |
| 3851 | #if __HVX_ARCH__ >= 68 |
| 3852 | /* ========================================================================== |
| 3853 | Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32) |
| 3854 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) |
| 3855 | Instruction Type: CVI_VS |
| 3856 | Execution Slots: SLOT0123 |
| 3857 | ========================================================================== */ |
| 3858 | |
| 3859 | #define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv) |
| 3860 | #endif |
| 3861 | |
| 3862 | #if __HVX_ARCH__ >= 68 |
| 3863 | /* ========================================================================== |
| 3864 | Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf) |
| 3865 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) |
| 3866 | Instruction Type: CVI_VS |
| 3867 | Execution Slots: SLOT0123 |
| 3868 | ========================================================================== */ |
| 3869 | |
| 3870 | #define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv) |
| 3871 | #endif |
| 3872 | |
| 3873 | #if __HVX_ARCH__ >= 68 |
| 3874 | /* ========================================================================== |
| 3875 | Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf) |
| 3876 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 3877 | Instruction Type: CVI_VS |
| 3878 | Execution Slots: SLOT0123 |
| 3879 | ========================================================================== */ |
| 3880 | |
| 3881 | #define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv) |
| 3882 | #endif |
| 3883 | |
| 3884 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3885 | /* ========================================================================== |
| 3886 | Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf) |
| 3887 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 3888 | Instruction Type: CVI_VX_DV |
| 3889 | Execution Slots: SLOT23 |
| 3890 | ========================================================================== */ |
| 3891 | |
| 3892 | #define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv) |
| 3893 | #endif |
| 3894 | |
| 3895 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3896 | /* ========================================================================== |
| 3897 | Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf) |
| 3898 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 3899 | Instruction Type: CVI_VX |
| 3900 | Execution Slots: SLOT23 |
| 3901 | ========================================================================== */ |
| 3902 | |
| 3903 | #define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv) |
| 3904 | #endif |
| 3905 | |
| 3906 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3907 | /* ========================================================================== |
| 3908 | Assembly Syntax: Vd32.w=vfmv(Vu32.w) |
| 3909 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu) |
| 3910 | Instruction Type: CVI_VX_LATE |
| 3911 | Execution Slots: SLOT23 |
| 3912 | ========================================================================== */ |
| 3913 | |
| 3914 | #define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu) |
| 3915 | #endif |
| 3916 | |
| 3917 | #if __HVX_ARCH__ >= 68 |
| 3918 | /* ========================================================================== |
| 3919 | Assembly Syntax: Vd32.hf=Vu32.qf16 |
| 3920 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu) |
| 3921 | Instruction Type: CVI_VS |
| 3922 | Execution Slots: SLOT0123 |
| 3923 | ========================================================================== */ |
| 3924 | |
| 3925 | #define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu) |
| 3926 | #endif |
| 3927 | |
| 3928 | #if __HVX_ARCH__ >= 68 |
| 3929 | /* ========================================================================== |
| 3930 | Assembly Syntax: Vd32.hf=Vuu32.qf32 |
| 3931 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu) |
| 3932 | Instruction Type: CVI_VS |
| 3933 | Execution Slots: SLOT0123 |
| 3934 | ========================================================================== */ |
| 3935 | |
| 3936 | #define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu) |
| 3937 | #endif |
| 3938 | |
| 3939 | #if __HVX_ARCH__ >= 68 |
| 3940 | /* ========================================================================== |
| 3941 | Assembly Syntax: Vd32.sf=Vu32.qf32 |
| 3942 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu) |
| 3943 | Instruction Type: CVI_VS |
| 3944 | Execution Slots: SLOT0123 |
| 3945 | ========================================================================== */ |
| 3946 | |
| 3947 | #define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu) |
| 3948 | #endif |
| 3949 | |
| 3950 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3951 | /* ========================================================================== |
| 3952 | Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf) |
| 3953 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 3954 | Instruction Type: CVI_VX |
| 3955 | Execution Slots: SLOT23 |
| 3956 | ========================================================================== */ |
| 3957 | |
| 3958 | #define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv) |
| 3959 | #endif |
| 3960 | |
| 3961 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3962 | /* ========================================================================== |
| 3963 | Assembly Syntax: Vd32.h=vcvt(Vu32.hf) |
| 3964 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu) |
| 3965 | Instruction Type: CVI_VX |
| 3966 | Execution Slots: SLOT23 |
| 3967 | ========================================================================== */ |
| 3968 | |
| 3969 | #define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu) |
| 3970 | #endif |
| 3971 | |
| 3972 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3973 | /* ========================================================================== |
| 3974 | Assembly Syntax: Vdd32.hf=vcvt(Vu32.b) |
| 3975 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu) |
| 3976 | Instruction Type: CVI_VX_DV |
| 3977 | Execution Slots: SLOT23 |
| 3978 | ========================================================================== */ |
| 3979 | |
| 3980 | #define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu) |
| 3981 | #endif |
| 3982 | |
| 3983 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3984 | /* ========================================================================== |
| 3985 | Assembly Syntax: Vd32.hf=vcvt(Vu32.h) |
| 3986 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu) |
| 3987 | Instruction Type: CVI_VX |
| 3988 | Execution Slots: SLOT23 |
| 3989 | ========================================================================== */ |
| 3990 | |
| 3991 | #define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu) |
| 3992 | #endif |
| 3993 | |
| 3994 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 3995 | /* ========================================================================== |
| 3996 | Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf) |
| 3997 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 3998 | Instruction Type: CVI_VX |
| 3999 | Execution Slots: SLOT23 |
| 4000 | ========================================================================== */ |
| 4001 | |
| 4002 | #define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv) |
| 4003 | #endif |
| 4004 | |
| 4005 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4006 | /* ========================================================================== |
| 4007 | Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub) |
| 4008 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu) |
| 4009 | Instruction Type: CVI_VX_DV |
| 4010 | Execution Slots: SLOT23 |
| 4011 | ========================================================================== */ |
| 4012 | |
| 4013 | #define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu) |
| 4014 | #endif |
| 4015 | |
| 4016 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4017 | /* ========================================================================== |
| 4018 | Assembly Syntax: Vd32.hf=vcvt(Vu32.uh) |
| 4019 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu) |
| 4020 | Instruction Type: CVI_VX |
| 4021 | Execution Slots: SLOT23 |
| 4022 | ========================================================================== */ |
| 4023 | |
| 4024 | #define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu) |
| 4025 | #endif |
| 4026 | |
| 4027 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4028 | /* ========================================================================== |
| 4029 | Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf) |
| 4030 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu) |
| 4031 | Instruction Type: CVI_VX_DV |
| 4032 | Execution Slots: SLOT23 |
| 4033 | ========================================================================== */ |
| 4034 | |
| 4035 | #define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu) |
| 4036 | #endif |
| 4037 | |
| 4038 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4039 | /* ========================================================================== |
| 4040 | Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf) |
| 4041 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4042 | Instruction Type: CVI_VX |
| 4043 | Execution Slots: SLOT23 |
| 4044 | ========================================================================== */ |
| 4045 | |
| 4046 | #define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv) |
| 4047 | #endif |
| 4048 | |
| 4049 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4050 | /* ========================================================================== |
| 4051 | Assembly Syntax: Vd32.uh=vcvt(Vu32.hf) |
| 4052 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu) |
| 4053 | Instruction Type: CVI_VX |
| 4054 | Execution Slots: SLOT23 |
| 4055 | ========================================================================== */ |
| 4056 | |
| 4057 | #define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu) |
| 4058 | #endif |
| 4059 | |
| 4060 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4061 | /* ========================================================================== |
| 4062 | Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf) |
| 4063 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4064 | Instruction Type: CVI_VX |
| 4065 | Execution Slots: SLOT23 |
| 4066 | ========================================================================== */ |
| 4067 | |
| 4068 | #define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv) |
| 4069 | #endif |
| 4070 | |
| 4071 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4072 | /* ========================================================================== |
| 4073 | Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf) |
| 4074 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 4075 | Instruction Type: CVI_VX |
| 4076 | Execution Slots: SLOT23 |
| 4077 | ========================================================================== */ |
| 4078 | |
| 4079 | #define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv) |
| 4080 | #endif |
| 4081 | |
| 4082 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4083 | /* ========================================================================== |
| 4084 | Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf) |
| 4085 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4086 | Instruction Type: CVI_VX_LATE |
| 4087 | Execution Slots: SLOT23 |
| 4088 | ========================================================================== */ |
| 4089 | |
| 4090 | #define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv) |
| 4091 | #endif |
| 4092 | |
| 4093 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4094 | /* ========================================================================== |
| 4095 | Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf) |
| 4096 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4097 | Instruction Type: CVI_VX_LATE |
| 4098 | Execution Slots: SLOT23 |
| 4099 | ========================================================================== */ |
| 4100 | |
| 4101 | #define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv) |
| 4102 | #endif |
| 4103 | |
| 4104 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4105 | /* ========================================================================== |
| 4106 | Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf) |
| 4107 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4108 | Instruction Type: CVI_VX_LATE |
| 4109 | Execution Slots: SLOT23 |
| 4110 | ========================================================================== */ |
| 4111 | |
| 4112 | #define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv) |
| 4113 | #endif |
| 4114 | |
| 4115 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4116 | /* ========================================================================== |
| 4117 | Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf) |
| 4118 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4119 | Instruction Type: CVI_VX_LATE |
| 4120 | Execution Slots: SLOT23 |
| 4121 | ========================================================================== */ |
| 4122 | |
| 4123 | #define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv) |
| 4124 | #endif |
| 4125 | |
| 4126 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4127 | /* ========================================================================== |
| 4128 | Assembly Syntax: Vd32.hf=vfneg(Vu32.hf) |
| 4129 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu) |
| 4130 | Instruction Type: CVI_VX_LATE |
| 4131 | Execution Slots: SLOT23 |
| 4132 | ========================================================================== */ |
| 4133 | |
| 4134 | #define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu) |
| 4135 | #endif |
| 4136 | |
| 4137 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4138 | /* ========================================================================== |
| 4139 | Assembly Syntax: Vd32.sf=vfneg(Vu32.sf) |
| 4140 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu) |
| 4141 | Instruction Type: CVI_VX_LATE |
| 4142 | Execution Slots: SLOT23 |
| 4143 | ========================================================================== */ |
| 4144 | |
| 4145 | #define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu) |
| 4146 | #endif |
| 4147 | |
| 4148 | #if __HVX_ARCH__ >= 68 |
| 4149 | /* ========================================================================== |
| 4150 | Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf) |
| 4151 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4152 | Instruction Type: CVI_VA |
| 4153 | Execution Slots: SLOT0123 |
| 4154 | ========================================================================== */ |
| 4155 | |
| 4156 | #define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1) |
| 4157 | #endif |
| 4158 | |
| 4159 | #if __HVX_ARCH__ >= 68 |
| 4160 | /* ========================================================================== |
| 4161 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf) |
| 4162 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 4163 | Instruction Type: CVI_VA |
| 4164 | Execution Slots: SLOT0123 |
| 4165 | ========================================================================== */ |
| 4166 | |
| 4167 | #define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 4168 | #endif |
| 4169 | |
| 4170 | #if __HVX_ARCH__ >= 68 |
| 4171 | /* ========================================================================== |
| 4172 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf) |
| 4173 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 4174 | Instruction Type: CVI_VA |
| 4175 | Execution Slots: SLOT0123 |
| 4176 | ========================================================================== */ |
| 4177 | |
| 4178 | #define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 4179 | #endif |
| 4180 | |
| 4181 | #if __HVX_ARCH__ >= 68 |
| 4182 | /* ========================================================================== |
| 4183 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf) |
| 4184 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 4185 | Instruction Type: CVI_VA |
| 4186 | Execution Slots: SLOT0123 |
| 4187 | ========================================================================== */ |
| 4188 | |
| 4189 | #define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 4190 | #endif |
| 4191 | |
| 4192 | #if __HVX_ARCH__ >= 68 |
| 4193 | /* ========================================================================== |
| 4194 | Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf) |
| 4195 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4196 | Instruction Type: CVI_VA |
| 4197 | Execution Slots: SLOT0123 |
| 4198 | ========================================================================== */ |
| 4199 | |
| 4200 | #define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1) |
| 4201 | #endif |
| 4202 | |
| 4203 | #if __HVX_ARCH__ >= 68 |
| 4204 | /* ========================================================================== |
| 4205 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf) |
| 4206 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 4207 | Instruction Type: CVI_VA |
| 4208 | Execution Slots: SLOT0123 |
| 4209 | ========================================================================== */ |
| 4210 | |
| 4211 | #define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 4212 | #endif |
| 4213 | |
| 4214 | #if __HVX_ARCH__ >= 68 |
| 4215 | /* ========================================================================== |
| 4216 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf) |
| 4217 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 4218 | Instruction Type: CVI_VA |
| 4219 | Execution Slots: SLOT0123 |
| 4220 | ========================================================================== */ |
| 4221 | |
| 4222 | #define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 4223 | #endif |
| 4224 | |
| 4225 | #if __HVX_ARCH__ >= 68 |
| 4226 | /* ========================================================================== |
| 4227 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf) |
| 4228 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 4229 | Instruction Type: CVI_VA |
| 4230 | Execution Slots: SLOT0123 |
| 4231 | ========================================================================== */ |
| 4232 | |
| 4233 | #define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
| 4234 | #endif |
| 4235 | |
| 4236 | #if __HVX_ARCH__ >= 68 |
| 4237 | /* ========================================================================== |
| 4238 | Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf) |
| 4239 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4240 | Instruction Type: CVI_VA |
| 4241 | Execution Slots: SLOT0123 |
| 4242 | ========================================================================== */ |
| 4243 | |
| 4244 | #define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv) |
| 4245 | #endif |
| 4246 | |
| 4247 | #if __HVX_ARCH__ >= 68 |
| 4248 | /* ========================================================================== |
| 4249 | Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf) |
| 4250 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4251 | Instruction Type: CVI_VA |
| 4252 | Execution Slots: SLOT0123 |
| 4253 | ========================================================================== */ |
| 4254 | |
| 4255 | #define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv) |
| 4256 | #endif |
| 4257 | |
| 4258 | #if __HVX_ARCH__ >= 68 |
| 4259 | /* ========================================================================== |
| 4260 | Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf) |
| 4261 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4262 | Instruction Type: CVI_VA |
| 4263 | Execution Slots: SLOT0123 |
| 4264 | ========================================================================== */ |
| 4265 | |
| 4266 | #define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv) |
| 4267 | #endif |
| 4268 | |
| 4269 | #if __HVX_ARCH__ >= 68 |
| 4270 | /* ========================================================================== |
| 4271 | Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf) |
| 4272 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4273 | Instruction Type: CVI_VA |
| 4274 | Execution Slots: SLOT0123 |
| 4275 | ========================================================================== */ |
| 4276 | |
| 4277 | #define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv) |
| 4278 | #endif |
| 4279 | |
| 4280 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4281 | /* ========================================================================== |
| 4282 | Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf) |
| 4283 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4284 | Instruction Type: CVI_VX |
| 4285 | Execution Slots: SLOT23 |
| 4286 | ========================================================================== */ |
| 4287 | |
| 4288 | #define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv) |
| 4289 | #endif |
| 4290 | |
| 4291 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4292 | /* ========================================================================== |
| 4293 | Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf) |
| 4294 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 4295 | Instruction Type: CVI_VX |
| 4296 | Execution Slots: SLOT23 |
| 4297 | ========================================================================== */ |
| 4298 | |
| 4299 | #define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv) |
| 4300 | #endif |
| 4301 | |
| 4302 | #if __HVX_ARCH__ >= 68 |
| 4303 | /* ========================================================================== |
| 4304 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16) |
| 4305 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
| 4306 | Instruction Type: CVI_VX_DV |
| 4307 | Execution Slots: SLOT23 |
| 4308 | ========================================================================== */ |
| 4309 | |
| 4310 | #define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv) |
| 4311 | #endif |
| 4312 | |
| 4313 | #if __HVX_ARCH__ >= 68 |
| 4314 | /* ========================================================================== |
| 4315 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf) |
| 4316 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4317 | Instruction Type: CVI_VX_DV |
| 4318 | Execution Slots: SLOT23 |
| 4319 | ========================================================================== */ |
| 4320 | |
| 4321 | #define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv) |
| 4322 | #endif |
| 4323 | |
| 4324 | #if __HVX_ARCH__ >= 68 |
| 4325 | /* ========================================================================== |
| 4326 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf) |
| 4327 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4328 | Instruction Type: CVI_VX_DV |
| 4329 | Execution Slots: SLOT23 |
| 4330 | ========================================================================== */ |
| 4331 | |
| 4332 | #define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv) |
| 4333 | #endif |
| 4334 | |
| 4335 | #if __HVX_ARCH__ >= 68 |
| 4336 | /* ========================================================================== |
| 4337 | Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32) |
| 4338 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) |
| 4339 | Instruction Type: CVI_VX_DV |
| 4340 | Execution Slots: SLOT23 |
| 4341 | ========================================================================== */ |
| 4342 | |
| 4343 | #define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv) |
| 4344 | #endif |
| 4345 | |
| 4346 | #if __HVX_ARCH__ >= 68 |
| 4347 | /* ========================================================================== |
| 4348 | Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf) |
| 4349 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4350 | Instruction Type: CVI_VX_DV |
| 4351 | Execution Slots: SLOT23 |
| 4352 | ========================================================================== */ |
| 4353 | |
| 4354 | #define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv) |
| 4355 | #endif |
| 4356 | |
| 4357 | #if __HVX_ARCH__ >= 68 |
| 4358 | /* ========================================================================== |
| 4359 | Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf) |
| 4360 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4361 | Instruction Type: CVI_VX_DV |
| 4362 | Execution Slots: SLOT23 |
| 4363 | ========================================================================== */ |
| 4364 | |
| 4365 | #define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv) |
| 4366 | #endif |
| 4367 | |
| 4368 | #if __HVX_ARCH__ >= 68 |
| 4369 | /* ========================================================================== |
| 4370 | Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16) |
| 4371 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
| 4372 | Instruction Type: CVI_VX_DV |
| 4373 | Execution Slots: SLOT23 |
| 4374 | ========================================================================== */ |
| 4375 | |
| 4376 | #define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv) |
| 4377 | #endif |
| 4378 | |
| 4379 | #if __HVX_ARCH__ >= 68 |
| 4380 | /* ========================================================================== |
| 4381 | Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf) |
| 4382 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4383 | Instruction Type: CVI_VX_DV |
| 4384 | Execution Slots: SLOT23 |
| 4385 | ========================================================================== */ |
| 4386 | |
| 4387 | #define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv) |
| 4388 | #endif |
| 4389 | |
| 4390 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4391 | /* ========================================================================== |
| 4392 | Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf) |
| 4393 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4394 | Instruction Type: CVI_VX_DV |
| 4395 | Execution Slots: SLOT23 |
| 4396 | ========================================================================== */ |
| 4397 | |
| 4398 | #define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv) |
| 4399 | #endif |
| 4400 | |
| 4401 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4402 | /* ========================================================================== |
| 4403 | Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf) |
| 4404 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 4405 | Instruction Type: CVI_VX_DV |
| 4406 | Execution Slots: SLOT23 |
| 4407 | ========================================================================== */ |
| 4408 | |
| 4409 | #define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv) |
| 4410 | #endif |
| 4411 | |
| 4412 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4413 | /* ========================================================================== |
| 4414 | Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf) |
| 4415 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4416 | Instruction Type: CVI_VX_DV |
| 4417 | Execution Slots: SLOT23 |
| 4418 | ========================================================================== */ |
| 4419 | |
| 4420 | #define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv) |
| 4421 | #endif |
| 4422 | |
| 4423 | #if __HVX_ARCH__ >= 68 |
| 4424 | /* ========================================================================== |
| 4425 | Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf) |
| 4426 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4427 | Instruction Type: CVI_VS |
| 4428 | Execution Slots: SLOT0123 |
| 4429 | ========================================================================== */ |
| 4430 | |
| 4431 | #define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv) |
| 4432 | #endif |
| 4433 | |
| 4434 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4435 | /* ========================================================================== |
| 4436 | Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf) |
| 4437 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4438 | Instruction Type: CVI_VX |
| 4439 | Execution Slots: SLOT23 |
| 4440 | ========================================================================== */ |
| 4441 | |
| 4442 | #define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv) |
| 4443 | #endif |
| 4444 | |
| 4445 | #if __HVX_ARCH__ >= 68 |
| 4446 | /* ========================================================================== |
| 4447 | Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16) |
| 4448 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
| 4449 | Instruction Type: CVI_VS |
| 4450 | Execution Slots: SLOT0123 |
| 4451 | ========================================================================== */ |
| 4452 | |
| 4453 | #define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv) |
| 4454 | #endif |
| 4455 | |
| 4456 | #if __HVX_ARCH__ >= 68 |
| 4457 | /* ========================================================================== |
| 4458 | Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf) |
| 4459 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4460 | Instruction Type: CVI_VS |
| 4461 | Execution Slots: SLOT0123 |
| 4462 | ========================================================================== */ |
| 4463 | |
| 4464 | #define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv) |
| 4465 | #endif |
| 4466 | |
| 4467 | #if __HVX_ARCH__ >= 68 |
| 4468 | /* ========================================================================== |
| 4469 | Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32) |
| 4470 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) |
| 4471 | Instruction Type: CVI_VS |
| 4472 | Execution Slots: SLOT0123 |
| 4473 | ========================================================================== */ |
| 4474 | |
| 4475 | #define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv) |
| 4476 | #endif |
| 4477 | |
| 4478 | #if __HVX_ARCH__ >= 68 |
| 4479 | /* ========================================================================== |
| 4480 | Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf) |
| 4481 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4482 | Instruction Type: CVI_VS |
| 4483 | Execution Slots: SLOT0123 |
| 4484 | ========================================================================== */ |
| 4485 | |
| 4486 | #define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv) |
| 4487 | #endif |
| 4488 | |
| 4489 | #if __HVX_ARCH__ >= 68 |
| 4490 | /* ========================================================================== |
| 4491 | Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf) |
| 4492 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4493 | Instruction Type: CVI_VS |
| 4494 | Execution Slots: SLOT0123 |
| 4495 | ========================================================================== */ |
| 4496 | |
| 4497 | #define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv) |
| 4498 | #endif |
| 4499 | |
| 4500 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4501 | /* ========================================================================== |
| 4502 | Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf) |
| 4503 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
| 4504 | Instruction Type: CVI_VX_DV |
| 4505 | Execution Slots: SLOT23 |
| 4506 | ========================================================================== */ |
| 4507 | |
| 4508 | #define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv) |
| 4509 | #endif |
| 4510 | |
| 4511 | #if __HVX_ARCH__ >= 68 && defined __HVX_IEEE_FP__ |
| 4512 | /* ========================================================================== |
| 4513 | Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf) |
| 4514 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
| 4515 | Instruction Type: CVI_VX |
| 4516 | Execution Slots: SLOT23 |
| 4517 | ========================================================================== */ |
| 4518 | |
| 4519 | #define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv) |
| 4520 | #endif |
| 4521 | |
| 4522 | #if __HVX_ARCH__ >= 69 |
| 4523 | /* ========================================================================== |
| 4524 | Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat |
| 4525 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
| 4526 | Instruction Type: CVI_VS |
| 4527 | Execution Slots: SLOT0123 |
| 4528 | ========================================================================== */ |
| 4529 | |
| 4530 | #define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv) |
| 4531 | #endif |
| 4532 | |
| 4533 | #if __HVX_ARCH__ >= 69 |
| 4534 | /* ========================================================================== |
| 4535 | Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat |
| 4536 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
| 4537 | Instruction Type: CVI_VS |
| 4538 | Execution Slots: SLOT0123 |
| 4539 | ========================================================================== */ |
| 4540 | |
| 4541 | #define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv) |
| 4542 | #endif |
| 4543 | |
| 4544 | #if __HVX_ARCH__ >= 69 |
| 4545 | /* ========================================================================== |
| 4546 | Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat |
| 4547 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
| 4548 | Instruction Type: CVI_VS |
| 4549 | Execution Slots: SLOT0123 |
| 4550 | ========================================================================== */ |
| 4551 | |
| 4552 | #define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv) |
| 4553 | #endif |
| 4554 | |
| 4555 | #if __HVX_ARCH__ >= 69 |
| 4556 | /* ========================================================================== |
| 4557 | Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat |
| 4558 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
| 4559 | Instruction Type: CVI_VS |
| 4560 | Execution Slots: SLOT0123 |
| 4561 | ========================================================================== */ |
| 4562 | |
| 4563 | #define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv) |
| 4564 | #endif |
| 4565 | |
| 4566 | #if __HVX_ARCH__ >= 69 |
| 4567 | /* ========================================================================== |
| 4568 | Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16 |
| 4569 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv) |
| 4570 | Instruction Type: CVI_VX |
| 4571 | Execution Slots: SLOT23 |
| 4572 | ========================================================================== */ |
| 4573 | |
| 4574 | #define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv) |
| 4575 | #endif |
| 4576 | |
| 4577 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4578 | /* ========================================================================== |
| 4579 | Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf) |
| 4580 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, |
| 4581 | HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4582 | ========================================================================== */ |
| 4583 | |
| 4584 | #define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \ |
| 4585 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_bf)(Vu, Vv) |
| 4586 | #endif |
| 4587 | |
| 4588 | #if __HVX_ARCH__ >= 73 |
| 4589 | /* ========================================================================== |
| 4590 | Assembly Syntax: Vd32.h=Vu32.hf |
| 4591 | C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf(HVX_Vector Vu) |
| 4592 | Instruction Type: CVI_VS |
| 4593 | Execution Slots: SLOT0123 |
| 4594 | ========================================================================== */ |
| 4595 | |
| 4596 | #define Q6_Vh_equals_Vhf(Vu) \ |
| 4597 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf)(Vu) |
| 4598 | #endif |
| 4599 | |
| 4600 | #if __HVX_ARCH__ >= 73 |
| 4601 | /* ========================================================================== |
| 4602 | Assembly Syntax: Vd32.hf=Vu32.h |
| 4603 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vh(HVX_Vector Vu) |
| 4604 | Instruction Type: CVI_VS |
| 4605 | Execution Slots: SLOT0123 |
| 4606 | ========================================================================== */ |
| 4607 | |
| 4608 | #define Q6_Vhf_equals_Vh(Vu) \ |
| 4609 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_h)(Vu) |
| 4610 | #endif |
| 4611 | |
| 4612 | #if __HVX_ARCH__ >= 73 |
| 4613 | /* ========================================================================== |
| 4614 | Assembly Syntax: Vd32.sf=Vu32.w |
| 4615 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vw(HVX_Vector Vu) |
| 4616 | Instruction Type: CVI_VS |
| 4617 | Execution Slots: SLOT0123 |
| 4618 | ========================================================================== */ |
| 4619 | |
| 4620 | #define Q6_Vsf_equals_Vw(Vu) \ |
| 4621 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_w)(Vu) |
| 4622 | #endif |
| 4623 | |
| 4624 | #if __HVX_ARCH__ >= 73 |
| 4625 | /* ========================================================================== |
| 4626 | Assembly Syntax: Vd32.w=Vu32.sf |
| 4627 | C Intrinsic Prototype: HVX_Vector Q6_Vw_equals_Vsf(HVX_Vector Vu) |
| 4628 | Instruction Type: CVI_VS |
| 4629 | Execution Slots: SLOT0123 |
| 4630 | ========================================================================== */ |
| 4631 | |
| 4632 | #define Q6_Vw_equals_Vsf(Vu) \ |
| 4633 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_w_sf)(Vu) |
| 4634 | #endif |
| 4635 | |
| 4636 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4637 | /* ========================================================================== |
| 4638 | Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf) |
| 4639 | C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, |
| 4640 | HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 |
| 4641 | ========================================================================== */ |
| 4642 | |
| 4643 | #define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \ |
| 4644 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_bf_sf)(Vu, Vv) |
| 4645 | #endif |
| 4646 | |
| 4647 | #if __HVX_ARCH__ >= 73 |
| 4648 | /* ========================================================================== |
| 4649 | Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf) |
| 4650 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, |
| 4651 | HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 |
| 4652 | ========================================================================== */ |
| 4653 | |
| 4654 | #define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \ |
| 4655 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ |
| 4656 | ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf)(Vu, Vv)), -1) |
| 4657 | #endif |
| 4658 | |
| 4659 | #if __HVX_ARCH__ >= 73 |
| 4660 | /* ========================================================================== |
| 4661 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf) |
| 4662 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred |
| 4663 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 4664 | Slots: SLOT0123 |
| 4665 | ========================================================================== */ |
| 4666 | |
| 4667 | #define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \ |
| 4668 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ |
| 4669 | ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_and)( \ |
| 4670 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 4671 | Vv)), \ |
| 4672 | -1) |
| 4673 | #endif |
| 4674 | |
| 4675 | #if __HVX_ARCH__ >= 73 |
| 4676 | /* ========================================================================== |
| 4677 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.bf,Vv32.bf) |
| 4678 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred |
| 4679 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 4680 | Slots: SLOT0123 |
| 4681 | ========================================================================== */ |
| 4682 | |
| 4683 | #define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \ |
| 4684 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ |
| 4685 | ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_or)( \ |
| 4686 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 4687 | Vv)), \ |
| 4688 | -1) |
| 4689 | #endif |
| 4690 | |
| 4691 | #if __HVX_ARCH__ >= 73 |
| 4692 | /* ========================================================================== |
| 4693 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf) |
| 4694 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred |
| 4695 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 4696 | Slots: SLOT0123 |
| 4697 | ========================================================================== */ |
| 4698 | |
| 4699 | #define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \ |
| 4700 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ |
| 4701 | ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_xor)( \ |
| 4702 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 4703 | Vv)), \ |
| 4704 | -1) |
| 4705 | #endif |
| 4706 | |
| 4707 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4708 | /* ========================================================================== |
| 4709 | Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf) |
| 4710 | C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, |
| 4711 | HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 |
| 4712 | ========================================================================== */ |
| 4713 | |
| 4714 | #define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \ |
| 4715 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_bf)(Vu, Vv) |
| 4716 | #endif |
| 4717 | |
| 4718 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4719 | /* ========================================================================== |
| 4720 | Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf) |
| 4721 | C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, |
| 4722 | HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 |
| 4723 | ========================================================================== */ |
| 4724 | |
| 4725 | #define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \ |
| 4726 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_bf)(Vu, Vv) |
| 4727 | #endif |
| 4728 | |
| 4729 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4730 | /* ========================================================================== |
| 4731 | Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf) |
| 4732 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, |
| 4733 | HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4734 | ========================================================================== */ |
| 4735 | |
| 4736 | #define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \ |
| 4737 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf)(Vu, Vv) |
| 4738 | #endif |
| 4739 | |
| 4740 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4741 | /* ========================================================================== |
| 4742 | Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf) |
| 4743 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair |
| 4744 | Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution |
| 4745 | Slots: SLOT23 |
| 4746 | ========================================================================== */ |
| 4747 | |
| 4748 | #define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \ |
| 4749 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf_acc)(Vxx, Vu, Vv) |
| 4750 | #endif |
| 4751 | |
| 4752 | #if __HVX_ARCH__ >= 73 && defined __HVX_IEEE_FP__ |
| 4753 | /* ========================================================================== |
| 4754 | Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf) |
| 4755 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, |
| 4756 | HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4757 | ========================================================================== */ |
| 4758 | |
| 4759 | #define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \ |
| 4760 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_bf)(Vu, Vv) |
| 4761 | #endif |
| 4762 | |
| 4763 | #if __HVX_ARCH__ >= 79 |
| 4764 | /* ========================================================================== |
| 4765 | Assembly Syntax: Vd32=vgetqfext(Vu32.x,Rt32) |
| 4766 | C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfext_VR(HVX_Vector Vu, Word32 Rt) |
| 4767 | Instruction Type: CVI_VX |
| 4768 | Execution Slots: SLOT23 |
| 4769 | ========================================================================== */ |
| 4770 | |
| 4771 | #define Q6_V_vgetqfext_VR(Vu, Rt) \ |
| 4772 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext)(Vu, Rt) |
| 4773 | #endif |
| 4774 | |
| 4775 | #if __HVX_ARCH__ >= 79 |
| 4776 | /* ========================================================================== |
| 4777 | Assembly Syntax: Vx32|=vgetqfext(Vu32.x,Rt32) |
| 4778 | C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, |
| 4779 | HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots: |
| 4780 | SLOT23 |
| 4781 | ========================================================================== */ |
| 4782 | |
| 4783 | #define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \ |
| 4784 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext_oracc)(Vx, Vu, Rt) |
| 4785 | #endif |
| 4786 | |
| 4787 | #if __HVX_ARCH__ >= 79 |
| 4788 | /* ========================================================================== |
| 4789 | Assembly Syntax: Vd32.x=vsetqfext(Vu32,Rt32) |
| 4790 | C Intrinsic Prototype: HVX_Vector Q6_V_vsetqfext_VR(HVX_Vector Vu, Word32 Rt) |
| 4791 | Instruction Type: CVI_VX |
| 4792 | Execution Slots: SLOT23 |
| 4793 | ========================================================================== */ |
| 4794 | |
| 4795 | #define Q6_V_vsetqfext_VR(Vu, Rt) \ |
| 4796 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_set_qfext)(Vu, Rt) |
| 4797 | #endif |
| 4798 | |
| 4799 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4800 | /* ========================================================================== |
| 4801 | Assembly Syntax: Vd32.f8=vabs(Vu32.f8) |
| 4802 | C Intrinsic Prototype: HVX_Vector Q6_V_vabs_V(HVX_Vector Vu) |
| 4803 | Instruction Type: CVI_VX_LATE |
| 4804 | Execution Slots: SLOT23 |
| 4805 | ========================================================================== */ |
| 4806 | |
| 4807 | #define Q6_V_vabs_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_f8)(Vu) |
| 4808 | #endif |
| 4809 | |
| 4810 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4811 | /* ========================================================================== |
| 4812 | Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8) |
| 4813 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, |
| 4814 | HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4815 | ========================================================================== */ |
| 4816 | |
| 4817 | #define Q6_Whf_vadd_VV(Vu, Vv) \ |
| 4818 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_f8)(Vu, Vv) |
| 4819 | #endif |
| 4820 | |
| 4821 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4822 | /* ========================================================================== |
| 4823 | Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf) |
| 4824 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, |
| 4825 | HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 |
| 4826 | ========================================================================== */ |
| 4827 | |
| 4828 | #define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \ |
| 4829 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_b_hf)(Vu, Vv) |
| 4830 | #endif |
| 4831 | |
| 4832 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4833 | /* ========================================================================== |
| 4834 | Assembly Syntax: Vdd32.hf=vcvt2(Vu32.b) |
| 4835 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vb(HVX_Vector Vu) |
| 4836 | Instruction Type: CVI_VX_DV |
| 4837 | Execution Slots: SLOT23 |
| 4838 | ========================================================================== */ |
| 4839 | |
| 4840 | #define Q6_Whf_vcvt2_Vb(Vu) \ |
| 4841 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_b)(Vu) |
| 4842 | #endif |
| 4843 | |
| 4844 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4845 | /* ========================================================================== |
| 4846 | Assembly Syntax: Vdd32.hf=vcvt2(Vu32.ub) |
| 4847 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vub(HVX_Vector Vu) |
| 4848 | Instruction Type: CVI_VX_DV |
| 4849 | Execution Slots: SLOT23 |
| 4850 | ========================================================================== */ |
| 4851 | |
| 4852 | #define Q6_Whf_vcvt2_Vub(Vu) \ |
| 4853 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_ub)(Vu) |
| 4854 | #endif |
| 4855 | |
| 4856 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4857 | /* ========================================================================== |
| 4858 | Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf) |
| 4859 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, |
| 4860 | HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 |
| 4861 | ========================================================================== */ |
| 4862 | |
| 4863 | #define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \ |
| 4864 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_ub_hf)(Vu, Vv) |
| 4865 | #endif |
| 4866 | |
| 4867 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4868 | /* ========================================================================== |
| 4869 | Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf) |
| 4870 | C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector |
| 4871 | Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 |
| 4872 | ========================================================================== */ |
| 4873 | |
| 4874 | #define Q6_V_vcvt_VhfVhf(Vu, Vv) \ |
| 4875 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_f8_hf)(Vu, Vv) |
| 4876 | #endif |
| 4877 | |
| 4878 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4879 | /* ========================================================================== |
| 4880 | Assembly Syntax: Vdd32.hf=vcvt(Vu32.f8) |
| 4881 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_V(HVX_Vector Vu) |
| 4882 | Instruction Type: CVI_VX_DV |
| 4883 | Execution Slots: SLOT23 |
| 4884 | ========================================================================== */ |
| 4885 | |
| 4886 | #define Q6_Whf_vcvt_V(Vu) \ |
| 4887 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_f8)(Vu) |
| 4888 | #endif |
| 4889 | |
| 4890 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4891 | /* ========================================================================== |
| 4892 | Assembly Syntax: Vd32.f8=vfmax(Vu32.f8,Vv32.f8) |
| 4893 | C Intrinsic Prototype: HVX_Vector Q6_V_vfmax_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 4894 | Instruction Type: CVI_VX_LATE |
| 4895 | Execution Slots: SLOT23 |
| 4896 | ========================================================================== */ |
| 4897 | |
| 4898 | #define Q6_V_vfmax_VV(Vu, Vv) \ |
| 4899 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_f8)(Vu, Vv) |
| 4900 | #endif |
| 4901 | |
| 4902 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4903 | /* ========================================================================== |
| 4904 | Assembly Syntax: Vd32.f8=vfmin(Vu32.f8,Vv32.f8) |
| 4905 | C Intrinsic Prototype: HVX_Vector Q6_V_vfmin_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 4906 | Instruction Type: CVI_VX_LATE |
| 4907 | Execution Slots: SLOT23 |
| 4908 | ========================================================================== */ |
| 4909 | |
| 4910 | #define Q6_V_vfmin_VV(Vu, Vv) \ |
| 4911 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_f8)(Vu, Vv) |
| 4912 | #endif |
| 4913 | |
| 4914 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4915 | /* ========================================================================== |
| 4916 | Assembly Syntax: Vd32.f8=vfneg(Vu32.f8) |
| 4917 | C Intrinsic Prototype: HVX_Vector Q6_V_vfneg_V(HVX_Vector Vu) |
| 4918 | Instruction Type: CVI_VX_LATE |
| 4919 | Execution Slots: SLOT23 |
| 4920 | ========================================================================== */ |
| 4921 | |
| 4922 | #define Q6_V_vfneg_V(Vu) \ |
| 4923 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_f8)(Vu) |
| 4924 | #endif |
| 4925 | |
| 4926 | #if __HVX_ARCH__ >= 79 |
| 4927 | /* ========================================================================== |
| 4928 | Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w) |
| 4929 | C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector |
| 4930 | Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 |
| 4931 | ========================================================================== */ |
| 4932 | |
| 4933 | #define Q6_V_vmerge_VVw(Vu, Vv) \ |
| 4934 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmerge_qf)(Vu, Vv) |
| 4935 | #endif |
| 4936 | |
| 4937 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4938 | /* ========================================================================== |
| 4939 | Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8) |
| 4940 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, |
| 4941 | HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4942 | ========================================================================== */ |
| 4943 | |
| 4944 | #define Q6_Whf_vmpy_VV(Vu, Vv) \ |
| 4945 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8)(Vu, Vv) |
| 4946 | #endif |
| 4947 | |
| 4948 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4949 | /* ========================================================================== |
| 4950 | Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8) |
| 4951 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair |
| 4952 | Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution |
| 4953 | Slots: SLOT23 |
| 4954 | ========================================================================== */ |
| 4955 | |
| 4956 | #define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \ |
| 4957 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8_acc)(Vxx, Vu, Vv) |
| 4958 | #endif |
| 4959 | |
| 4960 | #if __HVX_ARCH__ >= 79 |
| 4961 | /* ========================================================================== |
| 4962 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf) |
| 4963 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 |
| 4964 | Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4965 | ========================================================================== */ |
| 4966 | |
| 4967 | #define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \ |
| 4968 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_hf)(Vu, Rt) |
| 4969 | #endif |
| 4970 | |
| 4971 | #if __HVX_ARCH__ >= 79 |
| 4972 | /* ========================================================================== |
| 4973 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf) |
| 4974 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, |
| 4975 | Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4976 | ========================================================================== */ |
| 4977 | |
| 4978 | #define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \ |
| 4979 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_qf16)(Vu, Rt) |
| 4980 | #endif |
| 4981 | |
| 4982 | #if __HVX_ARCH__ >= 79 |
| 4983 | /* ========================================================================== |
| 4984 | Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf) |
| 4985 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 |
| 4986 | Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4987 | ========================================================================== */ |
| 4988 | |
| 4989 | #define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \ |
| 4990 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_sf)(Vu, Rt) |
| 4991 | #endif |
| 4992 | |
| 4993 | #if __HVX_ARCH__ >= 79 && defined __HVX_IEEE_FP__ |
| 4994 | /* ========================================================================== |
| 4995 | Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8) |
| 4996 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, |
| 4997 | HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 |
| 4998 | ========================================================================== */ |
| 4999 | |
| 5000 | #define Q6_Whf_vsub_VV(Vu, Vv) \ |
| 5001 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv) |
| 5002 | #endif |
| 5003 | |
| 5004 | #if __HVX_ARCH__ >= 81 |
| 5005 | /* ========================================================================== |
| 5006 | Assembly Syntax: Vd32.qf16=vabs(Vu32.hf) |
| 5007 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu) |
| 5008 | Instruction Type: CVI_VS |
| 5009 | Execution Slots: SLOT0123 |
| 5010 | ========================================================================== */ |
| 5011 | |
| 5012 | #define Q6_Vqf16_vabs_Vhf(Vu) \ |
| 5013 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu) |
| 5014 | #endif |
| 5015 | |
| 5016 | #if __HVX_ARCH__ >= 81 |
| 5017 | /* ========================================================================== |
| 5018 | Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16) |
| 5019 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu) |
| 5020 | Instruction Type: CVI_VS |
| 5021 | Execution Slots: SLOT0123 |
| 5022 | ========================================================================== */ |
| 5023 | |
| 5024 | #define Q6_Vqf16_vabs_Vqf16(Vu) \ |
| 5025 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu) |
| 5026 | #endif |
| 5027 | |
| 5028 | #if __HVX_ARCH__ >= 81 |
| 5029 | /* ========================================================================== |
| 5030 | Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32) |
| 5031 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu) |
| 5032 | Instruction Type: CVI_VS |
| 5033 | Execution Slots: SLOT0123 |
| 5034 | ========================================================================== */ |
| 5035 | |
| 5036 | #define Q6_Vqf32_vabs_Vqf32(Vu) \ |
| 5037 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu) |
| 5038 | #endif |
| 5039 | |
| 5040 | #if __HVX_ARCH__ >= 81 |
| 5041 | /* ========================================================================== |
| 5042 | Assembly Syntax: Vd32.qf32=vabs(Vu32.sf) |
| 5043 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu) |
| 5044 | Instruction Type: CVI_VS |
| 5045 | Execution Slots: SLOT0123 |
| 5046 | ========================================================================== */ |
| 5047 | |
| 5048 | #define Q6_Vqf32_vabs_Vsf(Vu) \ |
| 5049 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu) |
| 5050 | #endif |
| 5051 | |
| 5052 | #if __HVX_ARCH__ >= 81 |
| 5053 | /* ========================================================================== |
| 5054 | Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8) |
| 5055 | C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector |
| 5056 | Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123 |
| 5057 | ========================================================================== */ |
| 5058 | |
| 5059 | #define Q6_V_valign4_VVR(Vu, Vv, Rt) \ |
| 5060 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt) |
| 5061 | #endif |
| 5062 | |
| 5063 | #if __HVX_ARCH__ >= 81 |
| 5064 | /* ========================================================================== |
| 5065 | Assembly Syntax: Vd32.bf=Vuu32.qf32 |
| 5066 | C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu) |
| 5067 | Instruction Type: CVI_VS |
| 5068 | Execution Slots: SLOT0123 |
| 5069 | ========================================================================== */ |
| 5070 | |
| 5071 | #define Q6_Vbf_equals_Wqf32(Vuu) \ |
| 5072 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu) |
| 5073 | #endif |
| 5074 | |
| 5075 | #if __HVX_ARCH__ >= 81 |
| 5076 | /* ========================================================================== |
| 5077 | Assembly Syntax: Vd32.f8=Vu32.qf16 |
| 5078 | C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu) |
| 5079 | Instruction Type: CVI_VS |
| 5080 | Execution Slots: SLOT0123 |
| 5081 | ========================================================================== */ |
| 5082 | |
| 5083 | #define Q6_V_equals_Vqf16(Vu) \ |
| 5084 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu) |
| 5085 | #endif |
| 5086 | |
| 5087 | #if __HVX_ARCH__ >= 81 |
| 5088 | /* ========================================================================== |
| 5089 | Assembly Syntax: Vd32.h=Vu32.hf:rnd |
| 5090 | C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu) |
| 5091 | Instruction Type: CVI_VS |
| 5092 | Execution Slots: SLOT0123 |
| 5093 | ========================================================================== */ |
| 5094 | |
| 5095 | #define Q6_Vh_equals_Vhf_rnd(Vu) \ |
| 5096 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu) |
| 5097 | #endif |
| 5098 | |
| 5099 | #if __HVX_ARCH__ >= 81 |
| 5100 | /* ========================================================================== |
| 5101 | Assembly Syntax: Vdd32.qf16=Vu32.f8 |
| 5102 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu) |
| 5103 | Instruction Type: CVI_VP_VS |
| 5104 | Execution Slots: SLOT0123 |
| 5105 | ========================================================================== */ |
| 5106 | |
| 5107 | #define Q6_Wqf16_equals_V(Vu) \ |
| 5108 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu) |
| 5109 | #endif |
| 5110 | |
| 5111 | #if __HVX_ARCH__ >= 81 |
| 5112 | /* ========================================================================== |
| 5113 | Assembly Syntax: Vd32.qf16=Vu32.hf |
| 5114 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu) |
| 5115 | Instruction Type: CVI_VS |
| 5116 | Execution Slots: SLOT0123 |
| 5117 | ========================================================================== */ |
| 5118 | |
| 5119 | #define Q6_Vqf16_equals_Vhf(Vu) \ |
| 5120 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu) |
| 5121 | #endif |
| 5122 | |
| 5123 | #if __HVX_ARCH__ >= 81 |
| 5124 | /* ========================================================================== |
| 5125 | Assembly Syntax: Vd32.qf16=Vu32.qf16 |
| 5126 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu) |
| 5127 | Instruction Type: CVI_VS |
| 5128 | Execution Slots: SLOT0123 |
| 5129 | ========================================================================== */ |
| 5130 | |
| 5131 | #define Q6_Vqf16_equals_Vqf16(Vu) \ |
| 5132 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu) |
| 5133 | #endif |
| 5134 | |
| 5135 | #if __HVX_ARCH__ >= 81 |
| 5136 | /* ========================================================================== |
| 5137 | Assembly Syntax: Vd32.qf32=Vu32.qf32 |
| 5138 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu) |
| 5139 | Instruction Type: CVI_VS |
| 5140 | Execution Slots: SLOT0123 |
| 5141 | ========================================================================== */ |
| 5142 | |
| 5143 | #define Q6_Vqf32_equals_Vqf32(Vu) \ |
| 5144 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu) |
| 5145 | #endif |
| 5146 | |
| 5147 | #if __HVX_ARCH__ >= 81 |
| 5148 | /* ========================================================================== |
| 5149 | Assembly Syntax: Vd32.qf32=Vu32.sf |
| 5150 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu) |
| 5151 | Instruction Type: CVI_VS |
| 5152 | Execution Slots: SLOT0123 |
| 5153 | ========================================================================== */ |
| 5154 | |
| 5155 | #define Q6_Vqf32_equals_Vsf(Vu) \ |
| 5156 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu) |
| 5157 | #endif |
| 5158 | |
| 5159 | #if __HVX_ARCH__ >= 81 |
| 5160 | /* ========================================================================== |
| 5161 | Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf) |
| 5162 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, |
| 5163 | HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 |
| 5164 | ========================================================================== */ |
| 5165 | |
| 5166 | #define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \ |
| 5167 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5168 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1) |
| 5169 | #endif |
| 5170 | |
| 5171 | #if __HVX_ARCH__ >= 81 |
| 5172 | /* ========================================================================== |
| 5173 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf) |
| 5174 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred |
| 5175 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 5176 | Slots: SLOT0123 |
| 5177 | ========================================================================== */ |
| 5178 | |
| 5179 | #define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \ |
| 5180 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5181 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \ |
| 5182 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 5183 | Vv)), \ |
| 5184 | -1) |
| 5185 | #endif |
| 5186 | |
| 5187 | #if __HVX_ARCH__ >= 81 |
| 5188 | /* ========================================================================== |
| 5189 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf) |
| 5190 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred |
| 5191 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 5192 | Slots: SLOT0123 |
| 5193 | ========================================================================== */ |
| 5194 | |
| 5195 | #define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \ |
| 5196 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5197 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \ |
| 5198 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 5199 | Vv)), \ |
| 5200 | -1) |
| 5201 | #endif |
| 5202 | |
| 5203 | #if __HVX_ARCH__ >= 81 |
| 5204 | /* ========================================================================== |
| 5205 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf) |
| 5206 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred |
| 5207 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 5208 | Slots: SLOT0123 |
| 5209 | ========================================================================== */ |
| 5210 | |
| 5211 | #define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \ |
| 5212 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5213 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \ |
| 5214 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 5215 | Vv)), \ |
| 5216 | -1) |
| 5217 | #endif |
| 5218 | |
| 5219 | #if __HVX_ARCH__ >= 81 |
| 5220 | /* ========================================================================== |
| 5221 | Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf) |
| 5222 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, |
| 5223 | HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 |
| 5224 | ========================================================================== */ |
| 5225 | |
| 5226 | #define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \ |
| 5227 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5228 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1) |
| 5229 | #endif |
| 5230 | |
| 5231 | #if __HVX_ARCH__ >= 81 |
| 5232 | /* ========================================================================== |
| 5233 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf) |
| 5234 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred |
| 5235 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 5236 | Slots: SLOT0123 |
| 5237 | ========================================================================== */ |
| 5238 | |
| 5239 | #define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \ |
| 5240 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5241 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \ |
| 5242 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 5243 | Vv)), \ |
| 5244 | -1) |
| 5245 | #endif |
| 5246 | |
| 5247 | #if __HVX_ARCH__ >= 81 |
| 5248 | /* ========================================================================== |
| 5249 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf) |
| 5250 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred |
| 5251 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 5252 | Slots: SLOT0123 |
| 5253 | ========================================================================== */ |
| 5254 | |
| 5255 | #define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \ |
| 5256 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5257 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \ |
| 5258 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 5259 | Vv)), \ |
| 5260 | -1) |
| 5261 | #endif |
| 5262 | |
| 5263 | #if __HVX_ARCH__ >= 81 |
| 5264 | /* ========================================================================== |
| 5265 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf) |
| 5266 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred |
| 5267 | Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution |
| 5268 | Slots: SLOT0123 |
| 5269 | ========================================================================== */ |
| 5270 | |
| 5271 | #define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \ |
| 5272 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ |
| 5273 | (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \ |
| 5274 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ |
| 5275 | Vv)), \ |
| 5276 | -1) |
| 5277 | #endif |
| 5278 | |
| 5279 | #if __HVX_ARCH__ >= 81 |
| 5280 | /* ========================================================================== |
| 5281 | Assembly Syntax: Vd32.w=vilog2(Vu32.hf) |
| 5282 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu) |
| 5283 | Instruction Type: CVI_VS |
| 5284 | Execution Slots: SLOT0123 |
| 5285 | ========================================================================== */ |
| 5286 | |
| 5287 | #define Q6_Vw_vilog2_Vhf(Vu) \ |
| 5288 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu) |
| 5289 | #endif |
| 5290 | |
| 5291 | #if __HVX_ARCH__ >= 81 |
| 5292 | /* ========================================================================== |
| 5293 | Assembly Syntax: Vd32.w=vilog2(Vu32.qf16) |
| 5294 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu) |
| 5295 | Instruction Type: CVI_VS |
| 5296 | Execution Slots: SLOT0123 |
| 5297 | ========================================================================== */ |
| 5298 | |
| 5299 | #define Q6_Vw_vilog2_Vqf16(Vu) \ |
| 5300 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu) |
| 5301 | #endif |
| 5302 | |
| 5303 | #if __HVX_ARCH__ >= 81 |
| 5304 | /* ========================================================================== |
| 5305 | Assembly Syntax: Vd32.w=vilog2(Vu32.qf32) |
| 5306 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu) |
| 5307 | Instruction Type: CVI_VS |
| 5308 | Execution Slots: SLOT0123 |
| 5309 | ========================================================================== */ |
| 5310 | |
| 5311 | #define Q6_Vw_vilog2_Vqf32(Vu) \ |
| 5312 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu) |
| 5313 | #endif |
| 5314 | |
| 5315 | #if __HVX_ARCH__ >= 81 |
| 5316 | /* ========================================================================== |
| 5317 | Assembly Syntax: Vd32.w=vilog2(Vu32.sf) |
| 5318 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu) |
| 5319 | Instruction Type: CVI_VS |
| 5320 | Execution Slots: SLOT0123 |
| 5321 | ========================================================================== */ |
| 5322 | |
| 5323 | #define Q6_Vw_vilog2_Vsf(Vu) \ |
| 5324 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu) |
| 5325 | #endif |
| 5326 | |
| 5327 | #if __HVX_ARCH__ >= 81 |
| 5328 | /* ========================================================================== |
| 5329 | Assembly Syntax: Vd32.qf16=vneg(Vu32.hf) |
| 5330 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu) |
| 5331 | Instruction Type: CVI_VS |
| 5332 | Execution Slots: SLOT0123 |
| 5333 | ========================================================================== */ |
| 5334 | |
| 5335 | #define Q6_Vqf16_vneg_Vhf(Vu) \ |
| 5336 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu) |
| 5337 | #endif |
| 5338 | |
| 5339 | #if __HVX_ARCH__ >= 81 |
| 5340 | /* ========================================================================== |
| 5341 | Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16) |
| 5342 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu) |
| 5343 | Instruction Type: CVI_VS |
| 5344 | Execution Slots: SLOT0123 |
| 5345 | ========================================================================== */ |
| 5346 | |
| 5347 | #define Q6_Vqf16_vneg_Vqf16(Vu) \ |
| 5348 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu) |
| 5349 | #endif |
| 5350 | |
| 5351 | #if __HVX_ARCH__ >= 81 |
| 5352 | /* ========================================================================== |
| 5353 | Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32) |
| 5354 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu) |
| 5355 | Instruction Type: CVI_VS |
| 5356 | Execution Slots: SLOT0123 |
| 5357 | ========================================================================== */ |
| 5358 | |
| 5359 | #define Q6_Vqf32_vneg_Vqf32(Vu) \ |
| 5360 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu) |
| 5361 | #endif |
| 5362 | |
| 5363 | #if __HVX_ARCH__ >= 81 |
| 5364 | /* ========================================================================== |
| 5365 | Assembly Syntax: Vd32.qf32=vneg(Vu32.sf) |
| 5366 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu) |
| 5367 | Instruction Type: CVI_VS |
| 5368 | Execution Slots: SLOT0123 |
| 5369 | ========================================================================== */ |
| 5370 | |
| 5371 | #define Q6_Vqf32_vneg_Vsf(Vu) \ |
| 5372 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu) |
| 5373 | #endif |
| 5374 | |
| 5375 | #if __HVX_ARCH__ >= 81 |
| 5376 | /* ========================================================================== |
| 5377 | Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16) |
| 5378 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, |
| 5379 | HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 |
| 5380 | ========================================================================== */ |
| 5381 | |
| 5382 | #define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \ |
| 5383 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv) |
| 5384 | #endif |
| 5385 | |
| 5386 | #if __HVX_ARCH__ >= 81 |
| 5387 | /* ========================================================================== |
| 5388 | Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32) |
| 5389 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, |
| 5390 | HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 |
| 5391 | ========================================================================== */ |
| 5392 | |
| 5393 | #define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \ |
| 5394 | __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv) |
| 5395 | #endif |
| 5396 | |
| 5397 | #endif /* __HVX__ */ |
| 5398 | |
| 5399 | #endif |