1/*===---- riscv_vector.h - RISC-V V-extension RVVIntrinsics -------------------===
2 *
3 *
4 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 * See https://llvm.org/LICENSE.txt for license information.
6 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *
8 *===-----------------------------------------------------------------------===
9 */
10
11#ifndef __RISCV_VECTOR_H
12#define __RISCV_VECTOR_H
13
14#include <stdint.h>
15#include <stddef.h>
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#pragma clang riscv intrinsic vector
22
23
24enum __RISCV_FRM {
25 __RISCV_FRM_RNE = 0,
26 __RISCV_FRM_RTZ = 1,
27 __RISCV_FRM_RDN = 2,
28 __RISCV_FRM_RUP = 3,
29 __RISCV_FRM_RMM = 4,
30};
31
32#define __riscv_vlenb() __builtin_rvv_vlenb()
33
34#define __riscv_vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
35#define __riscv_vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
36#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 0)
37#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 1)
38#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 2)
39#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 3)
40
41#define __riscv_vsetvl_e16mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 7)
42#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 0)
43#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 1)
44#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 2)
45#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 3)
46
47#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 0)
48#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 1)
49#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
50#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
51
52#define __riscv_vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
53#define __riscv_vsetvl_e16mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 6)
54#define __riscv_vsetvl_e32mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 7)
55
56#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 0)
57#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 1)
58#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 2)
59#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 3)
60
61#define __riscv_vsetvlmax_e8mf4() __builtin_rvv_vsetvlimax(0, 6)
62#define __riscv_vsetvlmax_e8mf2() __builtin_rvv_vsetvlimax(0, 7)
63#define __riscv_vsetvlmax_e8m1() __builtin_rvv_vsetvlimax(0, 0)
64#define __riscv_vsetvlmax_e8m2() __builtin_rvv_vsetvlimax(0, 1)
65#define __riscv_vsetvlmax_e8m4() __builtin_rvv_vsetvlimax(0, 2)
66#define __riscv_vsetvlmax_e8m8() __builtin_rvv_vsetvlimax(0, 3)
67
68#define __riscv_vsetvlmax_e16mf2() __builtin_rvv_vsetvlimax(1, 7)
69#define __riscv_vsetvlmax_e16m1() __builtin_rvv_vsetvlimax(1, 0)
70#define __riscv_vsetvlmax_e16m2() __builtin_rvv_vsetvlimax(1, 1)
71#define __riscv_vsetvlmax_e16m4() __builtin_rvv_vsetvlimax(1, 2)
72#define __riscv_vsetvlmax_e16m8() __builtin_rvv_vsetvlimax(1, 3)
73
74#define __riscv_vsetvlmax_e32m1() __builtin_rvv_vsetvlimax(2, 0)
75#define __riscv_vsetvlmax_e32m2() __builtin_rvv_vsetvlimax(2, 1)
76#define __riscv_vsetvlmax_e32m4() __builtin_rvv_vsetvlimax(2, 2)
77#define __riscv_vsetvlmax_e32m8() __builtin_rvv_vsetvlimax(2, 3)
78
79#define __riscv_vsetvlmax_e8mf8() __builtin_rvv_vsetvlimax(0, 5)
80#define __riscv_vsetvlmax_e16mf4() __builtin_rvv_vsetvlimax(1, 6)
81#define __riscv_vsetvlmax_e32mf2() __builtin_rvv_vsetvlimax(2, 7)
82
83#define __riscv_vsetvlmax_e64m1() __builtin_rvv_vsetvlimax(3, 0)
84#define __riscv_vsetvlmax_e64m2() __builtin_rvv_vsetvlimax(3, 1)
85#define __riscv_vsetvlmax_e64m4() __builtin_rvv_vsetvlimax(3, 2)
86#define __riscv_vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
87
88
89enum __RISCV_VXRM {
90 __RISCV_VXRM_RNU = 0,
91 __RISCV_VXRM_RNE = 1,
92 __RISCV_VXRM_RDN = 2,
93 __RISCV_VXRM_ROD = 3,
94};
95typedef __rvv_bool64_t vbool64_t;
96typedef __rvv_bool32_t vbool32_t;
97typedef __rvv_bool16_t vbool16_t;
98typedef __rvv_bool8_t vbool8_t;
99typedef __rvv_bool4_t vbool4_t;
100typedef __rvv_bool2_t vbool2_t;
101typedef __rvv_bool1_t vbool1_t;
102typedef __rvv_int8mf8_t vint8mf8_t;
103typedef __rvv_uint8mf8_t vuint8mf8_t;
104typedef __rvv_int8mf8x2_t vint8mf8x2_t;
105typedef __rvv_uint8mf8x2_t vuint8mf8x2_t;
106typedef __rvv_int8mf8x3_t vint8mf8x3_t;
107typedef __rvv_uint8mf8x3_t vuint8mf8x3_t;
108typedef __rvv_int8mf8x4_t vint8mf8x4_t;
109typedef __rvv_uint8mf8x4_t vuint8mf8x4_t;
110typedef __rvv_int8mf8x5_t vint8mf8x5_t;
111typedef __rvv_uint8mf8x5_t vuint8mf8x5_t;
112typedef __rvv_int8mf8x6_t vint8mf8x6_t;
113typedef __rvv_uint8mf8x6_t vuint8mf8x6_t;
114typedef __rvv_int8mf8x7_t vint8mf8x7_t;
115typedef __rvv_uint8mf8x7_t vuint8mf8x7_t;
116typedef __rvv_int8mf8x8_t vint8mf8x8_t;
117typedef __rvv_uint8mf8x8_t vuint8mf8x8_t;
118typedef __rvv_int8mf4_t vint8mf4_t;
119typedef __rvv_uint8mf4_t vuint8mf4_t;
120typedef __rvv_int8mf4x2_t vint8mf4x2_t;
121typedef __rvv_uint8mf4x2_t vuint8mf4x2_t;
122typedef __rvv_int8mf4x3_t vint8mf4x3_t;
123typedef __rvv_uint8mf4x3_t vuint8mf4x3_t;
124typedef __rvv_int8mf4x4_t vint8mf4x4_t;
125typedef __rvv_uint8mf4x4_t vuint8mf4x4_t;
126typedef __rvv_int8mf4x5_t vint8mf4x5_t;
127typedef __rvv_uint8mf4x5_t vuint8mf4x5_t;
128typedef __rvv_int8mf4x6_t vint8mf4x6_t;
129typedef __rvv_uint8mf4x6_t vuint8mf4x6_t;
130typedef __rvv_int8mf4x7_t vint8mf4x7_t;
131typedef __rvv_uint8mf4x7_t vuint8mf4x7_t;
132typedef __rvv_int8mf4x8_t vint8mf4x8_t;
133typedef __rvv_uint8mf4x8_t vuint8mf4x8_t;
134typedef __rvv_int8mf2_t vint8mf2_t;
135typedef __rvv_uint8mf2_t vuint8mf2_t;
136typedef __rvv_int8mf2x2_t vint8mf2x2_t;
137typedef __rvv_uint8mf2x2_t vuint8mf2x2_t;
138typedef __rvv_int8mf2x3_t vint8mf2x3_t;
139typedef __rvv_uint8mf2x3_t vuint8mf2x3_t;
140typedef __rvv_int8mf2x4_t vint8mf2x4_t;
141typedef __rvv_uint8mf2x4_t vuint8mf2x4_t;
142typedef __rvv_int8mf2x5_t vint8mf2x5_t;
143typedef __rvv_uint8mf2x5_t vuint8mf2x5_t;
144typedef __rvv_int8mf2x6_t vint8mf2x6_t;
145typedef __rvv_uint8mf2x6_t vuint8mf2x6_t;
146typedef __rvv_int8mf2x7_t vint8mf2x7_t;
147typedef __rvv_uint8mf2x7_t vuint8mf2x7_t;
148typedef __rvv_int8mf2x8_t vint8mf2x8_t;
149typedef __rvv_uint8mf2x8_t vuint8mf2x8_t;
150typedef __rvv_int8m1_t vint8m1_t;
151typedef __rvv_uint8m1_t vuint8m1_t;
152typedef __rvv_int8m1x2_t vint8m1x2_t;
153typedef __rvv_uint8m1x2_t vuint8m1x2_t;
154typedef __rvv_int8m1x3_t vint8m1x3_t;
155typedef __rvv_uint8m1x3_t vuint8m1x3_t;
156typedef __rvv_int8m1x4_t vint8m1x4_t;
157typedef __rvv_uint8m1x4_t vuint8m1x4_t;
158typedef __rvv_int8m1x5_t vint8m1x5_t;
159typedef __rvv_uint8m1x5_t vuint8m1x5_t;
160typedef __rvv_int8m1x6_t vint8m1x6_t;
161typedef __rvv_uint8m1x6_t vuint8m1x6_t;
162typedef __rvv_int8m1x7_t vint8m1x7_t;
163typedef __rvv_uint8m1x7_t vuint8m1x7_t;
164typedef __rvv_int8m1x8_t vint8m1x8_t;
165typedef __rvv_uint8m1x8_t vuint8m1x8_t;
166typedef __rvv_int8m2_t vint8m2_t;
167typedef __rvv_uint8m2_t vuint8m2_t;
168typedef __rvv_int8m2x2_t vint8m2x2_t;
169typedef __rvv_uint8m2x2_t vuint8m2x2_t;
170typedef __rvv_int8m2x3_t vint8m2x3_t;
171typedef __rvv_uint8m2x3_t vuint8m2x3_t;
172typedef __rvv_int8m2x4_t vint8m2x4_t;
173typedef __rvv_uint8m2x4_t vuint8m2x4_t;
174typedef __rvv_int8m4_t vint8m4_t;
175typedef __rvv_uint8m4_t vuint8m4_t;
176typedef __rvv_int8m4x2_t vint8m4x2_t;
177typedef __rvv_uint8m4x2_t vuint8m4x2_t;
178typedef __rvv_int8m8_t vint8m8_t;
179typedef __rvv_uint8m8_t vuint8m8_t;
180typedef __rvv_int16mf4_t vint16mf4_t;
181typedef __rvv_uint16mf4_t vuint16mf4_t;
182typedef __rvv_int16mf4x2_t vint16mf4x2_t;
183typedef __rvv_uint16mf4x2_t vuint16mf4x2_t;
184typedef __rvv_int16mf4x3_t vint16mf4x3_t;
185typedef __rvv_uint16mf4x3_t vuint16mf4x3_t;
186typedef __rvv_int16mf4x4_t vint16mf4x4_t;
187typedef __rvv_uint16mf4x4_t vuint16mf4x4_t;
188typedef __rvv_int16mf4x5_t vint16mf4x5_t;
189typedef __rvv_uint16mf4x5_t vuint16mf4x5_t;
190typedef __rvv_int16mf4x6_t vint16mf4x6_t;
191typedef __rvv_uint16mf4x6_t vuint16mf4x6_t;
192typedef __rvv_int16mf4x7_t vint16mf4x7_t;
193typedef __rvv_uint16mf4x7_t vuint16mf4x7_t;
194typedef __rvv_int16mf4x8_t vint16mf4x8_t;
195typedef __rvv_uint16mf4x8_t vuint16mf4x8_t;
196typedef __rvv_int16mf2_t vint16mf2_t;
197typedef __rvv_uint16mf2_t vuint16mf2_t;
198typedef __rvv_int16mf2x2_t vint16mf2x2_t;
199typedef __rvv_uint16mf2x2_t vuint16mf2x2_t;
200typedef __rvv_int16mf2x3_t vint16mf2x3_t;
201typedef __rvv_uint16mf2x3_t vuint16mf2x3_t;
202typedef __rvv_int16mf2x4_t vint16mf2x4_t;
203typedef __rvv_uint16mf2x4_t vuint16mf2x4_t;
204typedef __rvv_int16mf2x5_t vint16mf2x5_t;
205typedef __rvv_uint16mf2x5_t vuint16mf2x5_t;
206typedef __rvv_int16mf2x6_t vint16mf2x6_t;
207typedef __rvv_uint16mf2x6_t vuint16mf2x6_t;
208typedef __rvv_int16mf2x7_t vint16mf2x7_t;
209typedef __rvv_uint16mf2x7_t vuint16mf2x7_t;
210typedef __rvv_int16mf2x8_t vint16mf2x8_t;
211typedef __rvv_uint16mf2x8_t vuint16mf2x8_t;
212typedef __rvv_int16m1_t vint16m1_t;
213typedef __rvv_uint16m1_t vuint16m1_t;
214typedef __rvv_int16m1x2_t vint16m1x2_t;
215typedef __rvv_uint16m1x2_t vuint16m1x2_t;
216typedef __rvv_int16m1x3_t vint16m1x3_t;
217typedef __rvv_uint16m1x3_t vuint16m1x3_t;
218typedef __rvv_int16m1x4_t vint16m1x4_t;
219typedef __rvv_uint16m1x4_t vuint16m1x4_t;
220typedef __rvv_int16m1x5_t vint16m1x5_t;
221typedef __rvv_uint16m1x5_t vuint16m1x5_t;
222typedef __rvv_int16m1x6_t vint16m1x6_t;
223typedef __rvv_uint16m1x6_t vuint16m1x6_t;
224typedef __rvv_int16m1x7_t vint16m1x7_t;
225typedef __rvv_uint16m1x7_t vuint16m1x7_t;
226typedef __rvv_int16m1x8_t vint16m1x8_t;
227typedef __rvv_uint16m1x8_t vuint16m1x8_t;
228typedef __rvv_int16m2_t vint16m2_t;
229typedef __rvv_uint16m2_t vuint16m2_t;
230typedef __rvv_int16m2x2_t vint16m2x2_t;
231typedef __rvv_uint16m2x2_t vuint16m2x2_t;
232typedef __rvv_int16m2x3_t vint16m2x3_t;
233typedef __rvv_uint16m2x3_t vuint16m2x3_t;
234typedef __rvv_int16m2x4_t vint16m2x4_t;
235typedef __rvv_uint16m2x4_t vuint16m2x4_t;
236typedef __rvv_int16m4_t vint16m4_t;
237typedef __rvv_uint16m4_t vuint16m4_t;
238typedef __rvv_int16m4x2_t vint16m4x2_t;
239typedef __rvv_uint16m4x2_t vuint16m4x2_t;
240typedef __rvv_int16m8_t vint16m8_t;
241typedef __rvv_uint16m8_t vuint16m8_t;
242typedef __rvv_int32mf2_t vint32mf2_t;
243typedef __rvv_uint32mf2_t vuint32mf2_t;
244typedef __rvv_int32mf2x2_t vint32mf2x2_t;
245typedef __rvv_uint32mf2x2_t vuint32mf2x2_t;
246typedef __rvv_int32mf2x3_t vint32mf2x3_t;
247typedef __rvv_uint32mf2x3_t vuint32mf2x3_t;
248typedef __rvv_int32mf2x4_t vint32mf2x4_t;
249typedef __rvv_uint32mf2x4_t vuint32mf2x4_t;
250typedef __rvv_int32mf2x5_t vint32mf2x5_t;
251typedef __rvv_uint32mf2x5_t vuint32mf2x5_t;
252typedef __rvv_int32mf2x6_t vint32mf2x6_t;
253typedef __rvv_uint32mf2x6_t vuint32mf2x6_t;
254typedef __rvv_int32mf2x7_t vint32mf2x7_t;
255typedef __rvv_uint32mf2x7_t vuint32mf2x7_t;
256typedef __rvv_int32mf2x8_t vint32mf2x8_t;
257typedef __rvv_uint32mf2x8_t vuint32mf2x8_t;
258typedef __rvv_int32m1_t vint32m1_t;
259typedef __rvv_uint32m1_t vuint32m1_t;
260typedef __rvv_int32m1x2_t vint32m1x2_t;
261typedef __rvv_uint32m1x2_t vuint32m1x2_t;
262typedef __rvv_int32m1x3_t vint32m1x3_t;
263typedef __rvv_uint32m1x3_t vuint32m1x3_t;
264typedef __rvv_int32m1x4_t vint32m1x4_t;
265typedef __rvv_uint32m1x4_t vuint32m1x4_t;
266typedef __rvv_int32m1x5_t vint32m1x5_t;
267typedef __rvv_uint32m1x5_t vuint32m1x5_t;
268typedef __rvv_int32m1x6_t vint32m1x6_t;
269typedef __rvv_uint32m1x6_t vuint32m1x6_t;
270typedef __rvv_int32m1x7_t vint32m1x7_t;
271typedef __rvv_uint32m1x7_t vuint32m1x7_t;
272typedef __rvv_int32m1x8_t vint32m1x8_t;
273typedef __rvv_uint32m1x8_t vuint32m1x8_t;
274typedef __rvv_int32m2_t vint32m2_t;
275typedef __rvv_uint32m2_t vuint32m2_t;
276typedef __rvv_int32m2x2_t vint32m2x2_t;
277typedef __rvv_uint32m2x2_t vuint32m2x2_t;
278typedef __rvv_int32m2x3_t vint32m2x3_t;
279typedef __rvv_uint32m2x3_t vuint32m2x3_t;
280typedef __rvv_int32m2x4_t vint32m2x4_t;
281typedef __rvv_uint32m2x4_t vuint32m2x4_t;
282typedef __rvv_int32m4_t vint32m4_t;
283typedef __rvv_uint32m4_t vuint32m4_t;
284typedef __rvv_int32m4x2_t vint32m4x2_t;
285typedef __rvv_uint32m4x2_t vuint32m4x2_t;
286typedef __rvv_int32m8_t vint32m8_t;
287typedef __rvv_uint32m8_t vuint32m8_t;
288typedef __rvv_int64m1_t vint64m1_t;
289typedef __rvv_uint64m1_t vuint64m1_t;
290typedef __rvv_int64m1x2_t vint64m1x2_t;
291typedef __rvv_uint64m1x2_t vuint64m1x2_t;
292typedef __rvv_int64m1x3_t vint64m1x3_t;
293typedef __rvv_uint64m1x3_t vuint64m1x3_t;
294typedef __rvv_int64m1x4_t vint64m1x4_t;
295typedef __rvv_uint64m1x4_t vuint64m1x4_t;
296typedef __rvv_int64m1x5_t vint64m1x5_t;
297typedef __rvv_uint64m1x5_t vuint64m1x5_t;
298typedef __rvv_int64m1x6_t vint64m1x6_t;
299typedef __rvv_uint64m1x6_t vuint64m1x6_t;
300typedef __rvv_int64m1x7_t vint64m1x7_t;
301typedef __rvv_uint64m1x7_t vuint64m1x7_t;
302typedef __rvv_int64m1x8_t vint64m1x8_t;
303typedef __rvv_uint64m1x8_t vuint64m1x8_t;
304typedef __rvv_int64m2_t vint64m2_t;
305typedef __rvv_uint64m2_t vuint64m2_t;
306typedef __rvv_int64m2x2_t vint64m2x2_t;
307typedef __rvv_uint64m2x2_t vuint64m2x2_t;
308typedef __rvv_int64m2x3_t vint64m2x3_t;
309typedef __rvv_uint64m2x3_t vuint64m2x3_t;
310typedef __rvv_int64m2x4_t vint64m2x4_t;
311typedef __rvv_uint64m2x4_t vuint64m2x4_t;
312typedef __rvv_int64m4_t vint64m4_t;
313typedef __rvv_uint64m4_t vuint64m4_t;
314typedef __rvv_int64m4x2_t vint64m4x2_t;
315typedef __rvv_uint64m4x2_t vuint64m4x2_t;
316typedef __rvv_int64m8_t vint64m8_t;
317typedef __rvv_uint64m8_t vuint64m8_t;
318typedef __rvv_float16mf4_t vfloat16mf4_t;
319typedef __rvv_float16mf4x2_t vfloat16mf4x2_t;
320typedef __rvv_float16mf4x3_t vfloat16mf4x3_t;
321typedef __rvv_float16mf4x4_t vfloat16mf4x4_t;
322typedef __rvv_float16mf4x5_t vfloat16mf4x5_t;
323typedef __rvv_float16mf4x6_t vfloat16mf4x6_t;
324typedef __rvv_float16mf4x7_t vfloat16mf4x7_t;
325typedef __rvv_float16mf4x8_t vfloat16mf4x8_t;
326typedef __rvv_float16mf2_t vfloat16mf2_t;
327typedef __rvv_float16mf2x2_t vfloat16mf2x2_t;
328typedef __rvv_float16mf2x3_t vfloat16mf2x3_t;
329typedef __rvv_float16mf2x4_t vfloat16mf2x4_t;
330typedef __rvv_float16mf2x5_t vfloat16mf2x5_t;
331typedef __rvv_float16mf2x6_t vfloat16mf2x6_t;
332typedef __rvv_float16mf2x7_t vfloat16mf2x7_t;
333typedef __rvv_float16mf2x8_t vfloat16mf2x8_t;
334typedef __rvv_float16m1_t vfloat16m1_t;
335typedef __rvv_float16m1x2_t vfloat16m1x2_t;
336typedef __rvv_float16m1x3_t vfloat16m1x3_t;
337typedef __rvv_float16m1x4_t vfloat16m1x4_t;
338typedef __rvv_float16m1x5_t vfloat16m1x5_t;
339typedef __rvv_float16m1x6_t vfloat16m1x6_t;
340typedef __rvv_float16m1x7_t vfloat16m1x7_t;
341typedef __rvv_float16m1x8_t vfloat16m1x8_t;
342typedef __rvv_float16m2_t vfloat16m2_t;
343typedef __rvv_float16m2x2_t vfloat16m2x2_t;
344typedef __rvv_float16m2x3_t vfloat16m2x3_t;
345typedef __rvv_float16m2x4_t vfloat16m2x4_t;
346typedef __rvv_float16m4_t vfloat16m4_t;
347typedef __rvv_float16m4x2_t vfloat16m4x2_t;
348typedef __rvv_float16m8_t vfloat16m8_t;
349typedef __rvv_float32mf2_t vfloat32mf2_t;
350typedef __rvv_float32mf2x2_t vfloat32mf2x2_t;
351typedef __rvv_float32mf2x3_t vfloat32mf2x3_t;
352typedef __rvv_float32mf2x4_t vfloat32mf2x4_t;
353typedef __rvv_float32mf2x5_t vfloat32mf2x5_t;
354typedef __rvv_float32mf2x6_t vfloat32mf2x6_t;
355typedef __rvv_float32mf2x7_t vfloat32mf2x7_t;
356typedef __rvv_float32mf2x8_t vfloat32mf2x8_t;
357typedef __rvv_float32m1_t vfloat32m1_t;
358typedef __rvv_float32m1x2_t vfloat32m1x2_t;
359typedef __rvv_float32m1x3_t vfloat32m1x3_t;
360typedef __rvv_float32m1x4_t vfloat32m1x4_t;
361typedef __rvv_float32m1x5_t vfloat32m1x5_t;
362typedef __rvv_float32m1x6_t vfloat32m1x6_t;
363typedef __rvv_float32m1x7_t vfloat32m1x7_t;
364typedef __rvv_float32m1x8_t vfloat32m1x8_t;
365typedef __rvv_float32m2_t vfloat32m2_t;
366typedef __rvv_float32m2x2_t vfloat32m2x2_t;
367typedef __rvv_float32m2x3_t vfloat32m2x3_t;
368typedef __rvv_float32m2x4_t vfloat32m2x4_t;
369typedef __rvv_float32m4_t vfloat32m4_t;
370typedef __rvv_float32m4x2_t vfloat32m4x2_t;
371typedef __rvv_float32m8_t vfloat32m8_t;
372typedef __rvv_float64m1_t vfloat64m1_t;
373typedef __rvv_float64m1x2_t vfloat64m1x2_t;
374typedef __rvv_float64m1x3_t vfloat64m1x3_t;
375typedef __rvv_float64m1x4_t vfloat64m1x4_t;
376typedef __rvv_float64m1x5_t vfloat64m1x5_t;
377typedef __rvv_float64m1x6_t vfloat64m1x6_t;
378typedef __rvv_float64m1x7_t vfloat64m1x7_t;
379typedef __rvv_float64m1x8_t vfloat64m1x8_t;
380typedef __rvv_float64m2_t vfloat64m2_t;
381typedef __rvv_float64m2x2_t vfloat64m2x2_t;
382typedef __rvv_float64m2x3_t vfloat64m2x3_t;
383typedef __rvv_float64m2x4_t vfloat64m2x4_t;
384typedef __rvv_float64m4_t vfloat64m4_t;
385typedef __rvv_float64m4x2_t vfloat64m4x2_t;
386typedef __rvv_float64m8_t vfloat64m8_t;
387typedef __rvv_bfloat16mf4_t vbfloat16mf4_t;
388typedef __rvv_bfloat16mf4x2_t vbfloat16mf4x2_t;
389typedef __rvv_bfloat16mf4x3_t vbfloat16mf4x3_t;
390typedef __rvv_bfloat16mf4x4_t vbfloat16mf4x4_t;
391typedef __rvv_bfloat16mf4x5_t vbfloat16mf4x5_t;
392typedef __rvv_bfloat16mf4x6_t vbfloat16mf4x6_t;
393typedef __rvv_bfloat16mf4x7_t vbfloat16mf4x7_t;
394typedef __rvv_bfloat16mf4x8_t vbfloat16mf4x8_t;
395typedef __rvv_bfloat16mf2_t vbfloat16mf2_t;
396typedef __rvv_bfloat16mf2x2_t vbfloat16mf2x2_t;
397typedef __rvv_bfloat16mf2x3_t vbfloat16mf2x3_t;
398typedef __rvv_bfloat16mf2x4_t vbfloat16mf2x4_t;
399typedef __rvv_bfloat16mf2x5_t vbfloat16mf2x5_t;
400typedef __rvv_bfloat16mf2x6_t vbfloat16mf2x6_t;
401typedef __rvv_bfloat16mf2x7_t vbfloat16mf2x7_t;
402typedef __rvv_bfloat16mf2x8_t vbfloat16mf2x8_t;
403typedef __rvv_bfloat16m1_t vbfloat16m1_t;
404typedef __rvv_bfloat16m1x2_t vbfloat16m1x2_t;
405typedef __rvv_bfloat16m1x3_t vbfloat16m1x3_t;
406typedef __rvv_bfloat16m1x4_t vbfloat16m1x4_t;
407typedef __rvv_bfloat16m1x5_t vbfloat16m1x5_t;
408typedef __rvv_bfloat16m1x6_t vbfloat16m1x6_t;
409typedef __rvv_bfloat16m1x7_t vbfloat16m1x7_t;
410typedef __rvv_bfloat16m1x8_t vbfloat16m1x8_t;
411typedef __rvv_bfloat16m2_t vbfloat16m2_t;
412typedef __rvv_bfloat16m2x2_t vbfloat16m2x2_t;
413typedef __rvv_bfloat16m2x3_t vbfloat16m2x3_t;
414typedef __rvv_bfloat16m2x4_t vbfloat16m2x4_t;
415typedef __rvv_bfloat16m4_t vbfloat16m4_t;
416typedef __rvv_bfloat16m4x2_t vbfloat16m4x2_t;
417typedef __rvv_bfloat16m8_t vbfloat16m8_t;
418
419#ifdef __cplusplus
420}
421#endif // __cplusplus
422#endif // __RISCV_VECTOR_H