| 1 | /*- |
| 2 | * Copyright (c) 2013, 2014 Andrew Turner |
| 3 | * Copyright (c) 2021 The FreeBSD Foundation |
| 4 | * |
| 5 | * Portions of this software were developed by Andrew Turner |
| 6 | * under sponsorship from the FreeBSD Foundation. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #ifndef _MACHINE_HYPERVISOR_H_ |
| 31 | #define _MACHINE_HYPERVISOR_H_ |
| 32 | |
| 33 | /* |
| 34 | * These registers are only useful when in hypervisor context, |
| 35 | * e.g. specific to EL2, or controlling the hypervisor. |
| 36 | */ |
| 37 | |
| 38 | /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ |
| 39 | #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ |
| 40 | /* Valid if HCR_EL2.E2H == 0 */ |
| 41 | #define CNTHCTL_EL1PCTEN (1 << 0) /* Allow physical counter access */ |
| 42 | #define CNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access */ |
| 43 | /* Valid if HCR_EL2.E2H == 1 */ |
| 44 | #define CNTHCTL_E2H_EL0PCTEN (1 << 0) /* Allow EL0 physical counter access */ |
| 45 | #define CNTHCTL_E2H_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ |
| 46 | #define CNTHCTL_E2H_EL0VTEN (1 << 8) |
| 47 | #define CNTHCTL_E2H_EL0PTEN (1 << 9) |
| 48 | #define CNTHCTL_E2H_EL1PCTEN (1 << 10) /* Allow physical counter access */ |
| 49 | #define CNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer access */ |
| 50 | /* Unconditionally valid */ |
| 51 | #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ |
| 52 | #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ |
| 53 | |
| 54 | /* CNTPOFF_EL2 - Counter-timer Physical Offset Register */ |
| 55 | #define CNTPOFF_EL2_REG MRS_REG_ALT_NAME(CNTPOFF_EL2) |
| 56 | #define CNTPOFF_EL2_op0 3 |
| 57 | #define CNTPOFF_EL2_op1 4 |
| 58 | #define CNTPOFF_EL2_CRn 14 |
| 59 | #define CNTPOFF_EL2_CRm 0 |
| 60 | #define CNTPOFF_EL2_op2 6 |
| 61 | |
| 62 | /* CPTR_EL2 - Architecture feature trap register */ |
| 63 | /* Valid if HCR_EL2.E2H == 0 */ |
| 64 | #define CPTR_TRAP_ALL 0xc01037ff /* Enable all traps */ |
| 65 | #define CPTR_RES0 0x7fefc800 |
| 66 | #define CPTR_RES1 0x000032ff |
| 67 | #define CPTR_TZ 0x00000100 |
| 68 | #define CPTR_TFP 0x00000400 |
| 69 | #define CPTR_TTA 0x00100000 |
| 70 | /* Valid if HCR_EL2.E2H == 1 */ |
| 71 | #define CPTR_E2H_TRAP_ALL 0xd0000000 |
| 72 | #define CPTR_E2H_ZPEN 0x00030000 |
| 73 | #define CPTR_E2H_FPEN 0x00300000 |
| 74 | #define CPTR_E2H_TTA 0x10000000 |
| 75 | /* Unconditionally valid */ |
| 76 | #define CPTR_TCPAC 0x80000000 |
| 77 | |
| 78 | /* HCR_EL2 - Hypervisor Config Register */ |
| 79 | #define HCR_VM (UL(0x1) << 0) |
| 80 | #define HCR_SWIO (UL(0x1) << 1) |
| 81 | #define HCR_PTW (UL(0x1) << 2) |
| 82 | #define HCR_FMO (UL(0x1) << 3) |
| 83 | #define HCR_IMO (UL(0x1) << 4) |
| 84 | #define HCR_AMO (UL(0x1) << 5) |
| 85 | #define HCR_VF (UL(0x1) << 6) |
| 86 | #define HCR_VI (UL(0x1) << 7) |
| 87 | #define HCR_VSE (UL(0x1) << 8) |
| 88 | #define HCR_FB (UL(0x1) << 9) |
| 89 | #define HCR_BSU_MASK (UL(0x3) << 10) |
| 90 | #define HCR_BSU_IS (UL(0x1) << 10) |
| 91 | #define HCR_BSU_OS (UL(0x2) << 10) |
| 92 | #define HCR_BSU_FS (UL(0x3) << 10) |
| 93 | #define HCR_DC (UL(0x1) << 12) |
| 94 | #define HCR_TWI (UL(0x1) << 13) |
| 95 | #define HCR_TWE (UL(0x1) << 14) |
| 96 | #define HCR_TID0 (UL(0x1) << 15) |
| 97 | #define HCR_TID1 (UL(0x1) << 16) |
| 98 | #define HCR_TID2 (UL(0x1) << 17) |
| 99 | #define HCR_TID3 (UL(0x1) << 18) |
| 100 | #define HCR_TSC (UL(0x1) << 19) |
| 101 | #define HCR_TIDCP (UL(0x1) << 20) |
| 102 | #define HCR_TACR (UL(0x1) << 21) |
| 103 | #define HCR_TSW (UL(0x1) << 22) |
| 104 | #define HCR_TPCP (UL(0x1) << 23) |
| 105 | #define HCR_TPU (UL(0x1) << 24) |
| 106 | #define HCR_TTLB (UL(0x1) << 25) |
| 107 | #define HCR_TVM (UL(0x1) << 26) |
| 108 | #define HCR_TGE (UL(0x1) << 27) |
| 109 | #define HCR_TDZ (UL(0x1) << 28) |
| 110 | #define HCR_HCD (UL(0x1) << 29) |
| 111 | #define HCR_TRVM (UL(0x1) << 30) |
| 112 | #define HCR_RW (UL(0x1) << 31) |
| 113 | #define HCR_CD (UL(0x1) << 32) |
| 114 | #define HCR_ID (UL(0x1) << 33) |
| 115 | #define HCR_E2H (UL(0x1) << 34) |
| 116 | #define HCR_TLOR (UL(0x1) << 35) |
| 117 | #define HCR_TERR (UL(0x1) << 36) |
| 118 | #define HCR_TEA (UL(0x1) << 37) |
| 119 | #define HCR_MIOCNCE (UL(0x1) << 38) |
| 120 | /* Bit 39 is reserved */ |
| 121 | #define HCR_APK (UL(0x1) << 40) |
| 122 | #define HCR_API (UL(0x1) << 41) |
| 123 | #define HCR_NV (UL(0x1) << 42) |
| 124 | #define HCR_NV1 (UL(0x1) << 43) |
| 125 | #define HCR_AT (UL(0x1) << 44) |
| 126 | #define HCR_NV2 (UL(0x1) << 45) |
| 127 | #define HCR_FWB (UL(0x1) << 46) |
| 128 | #define HCR_FIEN (UL(0x1) << 47) |
| 129 | /* Bit 48 is reserved */ |
| 130 | #define HCR_TID4 (UL(0x1) << 49) |
| 131 | #define HCR_TICAB (UL(0x1) << 50) |
| 132 | #define HCR_AMVOFFEN (UL(0x1) << 51) |
| 133 | #define HCR_TOCU (UL(0x1) << 52) |
| 134 | #define HCR_EnSCXT (UL(0x1) << 53) |
| 135 | #define HCR_TTLBIS (UL(0x1) << 54) |
| 136 | #define HCR_TTLBOS (UL(0x1) << 55) |
| 137 | #define HCR_ATA (UL(0x1) << 56) |
| 138 | #define HCR_DCT (UL(0x1) << 57) |
| 139 | #define HCR_TID5 (UL(0x1) << 58) |
| 140 | #define HCR_TWEDEn (UL(0x1) << 59) |
| 141 | #define HCR_TWEDEL_MASK (UL(0xf) << 60) |
| 142 | |
| 143 | /* HCRX_EL2 - Extended Hypervisor Configuration Register */ |
| 144 | #define HCRX_EL2_REG MRS_REG_ALT_NAME(HCRX_EL2) |
| 145 | #define HCRX_EL2_op0 3 |
| 146 | #define HCRX_EL2_op1 4 |
| 147 | #define HCRX_EL2_CRn 1 |
| 148 | #define HCRX_EL2_CRm 2 |
| 149 | #define HCRX_EL2_op2 2 |
| 150 | |
| 151 | #define HCRX_EnAS0 (UL(0x1) << 0) |
| 152 | #define HCRX_EnALS (UL(0x1) << 1) |
| 153 | #define HCRX_EnASR (UL(0x1) << 2) |
| 154 | #define HCRX_FnXS (UL(0x1) << 3) |
| 155 | #define HCRX_FGTnXS (UL(0x1) << 4) |
| 156 | #define HCRX_SMPME (UL(0x1) << 5) |
| 157 | #define HCRX_TALLINT (UL(0x1) << 6) |
| 158 | #define HCRX_VINMI (UL(0x1) << 7) |
| 159 | #define HCRX_VFNMI (UL(0x1) << 8) |
| 160 | #define HCRX_CMOW (UL(0x1) << 9) |
| 161 | #define HCRX_MCE2 (UL(0x1) << 10) |
| 162 | #define HCRX_MSCEn (UL(0x1) << 11) |
| 163 | /* Bits 12 & 13 are reserved */ |
| 164 | #define HCRX_TCR2En (UL(0x1) << 14) |
| 165 | #define HCRX_SCTLR2En (UL(0x1) << 15) |
| 166 | #define HCRX_PTTWI (UL(0x1) << 16) |
| 167 | #define HCRX_D128En (UL(0x1) << 17) |
| 168 | #define HCRX_EnSNERR (UL(0x1) << 18) |
| 169 | #define HCRX_TMEA (UL(0x1) << 19) |
| 170 | #define HCRX_EnSDERR (UL(0x1) << 20) |
| 171 | #define HCRX_EnIDCP128 (UL(0x1) << 21) |
| 172 | #define HCRX_GCSEn (UL(0x1) << 22) |
| 173 | #define HCRX_EnFPM (UL(0x1) << 23) |
| 174 | #define HCRX_PACMEn (UL(0x1) << 24) |
| 175 | /* Bit 25 is reserved */ |
| 176 | #define HCRX_SRMASKEn (UL(0x1) << 26) |
| 177 | |
| 178 | /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ |
| 179 | #define HPFAR_EL2_FIPA_SHIFT 4 |
| 180 | #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 |
| 181 | #define HPFAR_EL2_FIPA_GET(x) \ |
| 182 | (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT) |
| 183 | /* HPFAR_EL2_FIPA holds the 4k page address */ |
| 184 | #define HPFAR_EL2_FIPA_ADDR(x) \ |
| 185 | (HPFAR_EL2_FIPA_GET(x) << 12) |
| 186 | /* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */ |
| 187 | #define FAR_EL2_HPFAR_PAGE_MASK (0xffful) |
| 188 | |
| 189 | /* ICC_SRE_EL2 */ |
| 190 | #define ICC_SRE_EL2_SRE (1UL << 0) |
| 191 | #define ICC_SRE_EL2_EN (1UL << 3) |
| 192 | |
| 193 | /* MDCR_EL2 - Hyp Debug Control Register */ |
| 194 | #define MDCR_EL2_HPMN_MASK 0x1f |
| 195 | #define MDCR_EL2_HPMN_SHIFT 0 |
| 196 | #define MDCR_EL2_TPMCR_SHIFT 5 |
| 197 | #define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) |
| 198 | #define MDCR_EL2_TPM_SHIFT 6 |
| 199 | #define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) |
| 200 | #define MDCR_EL2_HPME_SHIFT 7 |
| 201 | #define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) |
| 202 | #define MDCR_EL2_TDE_SHIFT 8 |
| 203 | #define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) |
| 204 | #define MDCR_EL2_TDA_SHIFT 9 |
| 205 | #define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) |
| 206 | #define MDCR_EL2_TDOSA_SHIFT 10 |
| 207 | #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) |
| 208 | #define MDCR_EL2_TDRA_SHIFT 11 |
| 209 | #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) |
| 210 | #define MDCR_EL2_E2PB_SHIFT 12 |
| 211 | #define MDCR_EL2_E2PB_MASK (0x3UL << MDCR_EL2_E2PB_SHIFT) |
| 212 | #define MDCR_EL2_TPMS_SHIFT 14 |
| 213 | #define MDCR_EL2_TPMS (0x1UL << MDCR_EL2_TPMS_SHIFT) |
| 214 | #define MDCR_EL2_EnSPM_SHIFT 15 |
| 215 | #define MDCR_EL2_EnSPM (0x1UL << MDCR_EL2_EnSPM_SHIFT) |
| 216 | #define MDCR_EL2_HPMD_SHIFT 17 |
| 217 | #define MDCR_EL2_HPMD (0x1UL << MDCR_EL2_HPMD_SHIFT) |
| 218 | #define MDCR_EL2_TTRF_SHIFT 19 |
| 219 | #define MDCR_EL2_TTRF (0x1UL << MDCR_EL2_TTRF_SHIFT) |
| 220 | #define MDCR_EL2_HCCD_SHIFT 23 |
| 221 | #define MDCR_EL2_HCCD (0x1UL << MDCR_EL2_HCCD_SHIFT) |
| 222 | #define MDCR_EL2_E2TB_SHIFT 24 |
| 223 | #define MDCR_EL2_E2TB_MASK (0x3UL << MDCR_EL2_E2TB_SHIFT) |
| 224 | #define MDCR_EL2_HLP_SHIFT 26 |
| 225 | #define MDCR_EL2_HLP (0x1UL << MDCR_EL2_HLP_SHIFT) |
| 226 | #define MDCR_EL2_TDCC_SHIFT 27 |
| 227 | #define MDCR_EL2_TDCC (0x1UL << MDCR_EL2_TDCC_SHIFT) |
| 228 | #define MDCR_EL2_MTPME_SHIFT 28 |
| 229 | #define MDCR_EL2_MTPME (0x1UL << MDCR_EL2_MTPME_SHIFT) |
| 230 | #define MDCR_EL2_HPMFZO_SHIFT 29 |
| 231 | #define MDCR_EL2_HPMFZO (0x1UL << MDCR_EL2_HPMFZO_SHIFT) |
| 232 | #define MDCR_EL2_PMSSE_SHIFT 30 |
| 233 | #define MDCR_EL2_PMSSE_MASK (0x3UL << MDCR_EL2_PMSSE_SHIFT) |
| 234 | #define MDCR_EL2_HPMFZS_SHIFT 36 |
| 235 | #define MDCR_EL2_HPMFZS (0x1UL << MDCR_EL2_HPMFZS_SHIFT) |
| 236 | #define MDCR_EL2_PMEE_SHIFT 40 |
| 237 | #define MDCR_EL2_PMEE_MASK (0x3UL << MDCR_EL2_PMEE_SHIFT) |
| 238 | #define MDCR_EL2_EBWE_SHIFT 43 |
| 239 | #define MDCR_EL2_EBWE (0x1UL << MDCR_EL2_EBWE_SHIFT) |
| 240 | |
| 241 | /* SCTLR_EL2 - System Control Register */ |
| 242 | #define SCTLR_EL2_RES1 0x30c50830 |
| 243 | #define SCTLR_EL2_M_SHIFT 0 |
| 244 | #define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) |
| 245 | #define SCTLR_EL2_A_SHIFT 1 |
| 246 | #define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) |
| 247 | #define SCTLR_EL2_C_SHIFT 2 |
| 248 | #define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) |
| 249 | #define SCTLR_EL2_SA_SHIFT 3 |
| 250 | #define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) |
| 251 | #define SCTLR_EL2_EOS_SHIFT 11 |
| 252 | #define SCTLR_EL2_EOS (0x1UL << SCTLR_EL2_EOS_SHIFT) |
| 253 | #define SCTLR_EL2_I_SHIFT 12 |
| 254 | #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) |
| 255 | #define SCTLR_EL2_WXN_SHIFT 19 |
| 256 | #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) |
| 257 | #define SCTLR_EL2_EIS_SHIFT 22 |
| 258 | #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) |
| 259 | #define SCTLR_EL2_EE_SHIFT 25 |
| 260 | #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) |
| 261 | |
| 262 | /* TCR_EL2 - Translation Control Register */ |
| 263 | #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) |
| 264 | #define TCR_EL2_T0SZ_SHIFT 0 |
| 265 | #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) |
| 266 | #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) |
| 267 | /* Bits 7:6 are reserved */ |
| 268 | #define TCR_EL2_IRGN0_SHIFT 8 |
| 269 | #define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) |
| 270 | #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT) |
| 271 | #define TCR_EL2_ORGN0_SHIFT 10 |
| 272 | #define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) |
| 273 | #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT) |
| 274 | #define TCR_EL2_SH0_SHIFT 12 |
| 275 | #define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) |
| 276 | #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT) |
| 277 | #define TCR_EL2_TG0_SHIFT 14 |
| 278 | #define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) |
| 279 | #define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT) |
| 280 | #define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT) |
| 281 | #define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT) |
| 282 | #define TCR_EL2_PS_SHIFT 16 |
| 283 | #define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT) |
| 284 | #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) |
| 285 | #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) |
| 286 | #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) |
| 287 | #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) |
| 288 | #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) |
| 289 | #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) |
| 290 | #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) |
| 291 | #define TCR_EL2_HPD_SHIFT 24 |
| 292 | #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT) |
| 293 | #define TCR_EL2_HWU59_SHIFT 25 |
| 294 | #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT) |
| 295 | #define TCR_EL2_HWU60_SHIFT 26 |
| 296 | #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) |
| 297 | #define TCR_EL2_HWU61_SHIFT 27 |
| 298 | #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) |
| 299 | #define TCR_EL2_HWU62_SHIFT 28 |
| 300 | #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) |
| 301 | #define TCR_EL2_HWU \ |
| 302 | (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) |
| 303 | |
| 304 | /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ |
| 305 | #define VMPIDR_EL2_U 0x0000000040000000 |
| 306 | #define VMPIDR_EL2_MT 0x0000000001000000 |
| 307 | #define VMPIDR_EL2_RES1 0x0000000080000000 |
| 308 | |
| 309 | /* VTCR_EL2 - Virtualization Translation Control Register */ |
| 310 | #define VTCR_EL2_RES1 (0x1UL << 31) |
| 311 | #define VTCR_EL2_T0SZ_SHIFT 0 |
| 312 | #define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT) |
| 313 | #define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT) |
| 314 | #define VTCR_EL2_SL0_SHIFT 6 |
| 315 | #define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) |
| 316 | #define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) |
| 317 | #define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) |
| 318 | #define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT) |
| 319 | #define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT) |
| 320 | #define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT) |
| 321 | #define VTCR_EL2_IRGN0_SHIFT 8 |
| 322 | #define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) |
| 323 | #define VTCR_EL2_ORGN0_SHIFT 10 |
| 324 | #define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) |
| 325 | #define VTCR_EL2_SH0_SHIFT 12 |
| 326 | #define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) |
| 327 | #define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) |
| 328 | #define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) |
| 329 | #define VTCR_EL2_TG0_SHIFT 14 |
| 330 | #define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) |
| 331 | #define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) |
| 332 | #define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) |
| 333 | #define VTCR_EL2_PS_SHIFT 16 |
| 334 | #define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) |
| 335 | #define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) |
| 336 | #define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) |
| 337 | #define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) |
| 338 | #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) |
| 339 | #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) |
| 340 | #define VTCR_EL2_PS_52BIT (0x6UL << VTCR_EL2_PS_SHIFT) |
| 341 | #define VTCR_EL2_DS_SHIFT 32 |
| 342 | #define VTCR_EL2_DS (0x1UL << VTCR_EL2_DS_SHIFT) |
| 343 | |
| 344 | /* VTTBR_EL2 - Virtualization Translation Table Base Register */ |
| 345 | #define VTTBR_VMID_MASK 0xffff000000000000 |
| 346 | #define VTTBR_VMID_SHIFT 48 |
| 347 | /* Assumed to be 0 by locore.S */ |
| 348 | #define VTTBR_HOST 0x0000000000000000 |
| 349 | |
| 350 | #endif /* !_MACHINE_HYPERVISOR_H_ */ |