1/*-
2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2014-2015 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#ifdef __arm__
32#include <arm/pte.h>
33#else /* !__arm__ */
34
35#ifndef _MACHINE_PTE_H_
36#define _MACHINE_PTE_H_
37
38#ifndef LOCORE
39typedef uint64_t pd_entry_t; /* page directory entry */
40typedef uint64_t pt_entry_t; /* page table entry */
41#endif
42
43/* Table attributes */
44#define TATTR_MASK UINT64_C(0xfff8000000000000)
45#define TATTR_AP_TABLE_MASK (3UL << 61)
46#define TATTR_AP_TABLE_RO (2UL << 61)
47#define TATTR_AP_TABLE_NO_EL0 (1UL << 61)
48#define TATTR_UXN_TABLE (1UL << 60)
49#define TATTR_PXN_TABLE (1UL << 59)
50/* Bits 58:51 are ignored */
51
52/* Block and Page attributes */
53#define ATTR_MASK_H UINT64_C(0xfffc000000000000)
54#define ATTR_MASK_L UINT64_C(0x0000000000000fff)
55#define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L)
56
57/* Bits 58:55 are reserved for software */
58#define ATTR_SW_UNUSED1 (1UL << 58)
59#define ATTR_SW_NO_PROMOTE (1UL << 57)
60#define ATTR_SW_MANAGED (1UL << 56)
61#define ATTR_SW_WIRED (1UL << 55)
62
63#define ATTR_S1_UXN (1UL << 54)
64#define ATTR_S1_PXN (1UL << 53)
65#define ATTR_S1_XN (ATTR_S1_PXN | ATTR_S1_UXN)
66
67#define ATTR_S2_XN(x) ((x) << 53)
68#define ATTR_S2_XN_MASK ATTR_S2_XN(3UL)
69#define ATTR_S2_XN_NONE 0UL /* Allow execution at EL0 & EL1 */
70#define ATTR_S2_XN_EL1 1UL /* Allow execution at EL0 */
71#define ATTR_S2_XN_ALL 2UL /* No execution */
72#define ATTR_S2_XN_EL0 3UL /* Allow execution at EL1 */
73
74#define ATTR_CONTIGUOUS (1UL << 52)
75#define ATTR_DBM (1UL << 51)
76#define ATTR_S1_GP_SHIFT 50
77#define ATTR_S1_GP (1UL << ATTR_S1_GP_SHIFT)
78
79/*
80 * Largest possible output address field for a level 3 page. Block
81 * entries will use fewer low address bits, but these are res0 so
82 * should be safe to include.
83 *
84 * This is also safe to use for the next-level table address for
85 * table entries as they encode a physical address in the same way.
86 */
87#if PAGE_SIZE == PAGE_SIZE_4K
88#define ATTR_ADDR UINT64_C(0x0003fffffffff000)
89#elif PAGE_SIZE == PAGE_SIZE_16K
90#define ATTR_ADDR UINT64_C(0x0003ffffffffc000)
91#else
92#error Unsupported page size
93#endif
94
95#define ATTR_S1_nG (1 << 11)
96#define ATTR_AF (1 << 10)
97/* When TCR_EL1.DS == 0 */
98#define ATTR_SH(x) ((x) << 8)
99#define ATTR_SH_MASK ATTR_SH(3)
100#define ATTR_SH_NS 0 /* Non-shareable */
101#define ATTR_SH_OS 2 /* Outer-shareable */
102#define ATTR_SH_IS 3 /* Inner-shareable */
103/* When TCR_EL1.DS == 1 */
104#define ATTR_OA_51_50_SHIFT 8
105#define ATTR_OA_51_50_MASK (3 << ATTR_OA_51_50_SHIFT)
106#define ATTR_OA_51_50_DELTA (50 - 8) /* Delta from address to pte */
107
108#define ATTR_S1_AP_RW_BIT (1 << 7)
109#define ATTR_S1_AP(x) ((x) << 6)
110#define ATTR_S1_AP_MASK ATTR_S1_AP(3)
111#define ATTR_S1_AP_RW (0 << 1)
112#define ATTR_S1_AP_RO (1 << 1)
113#define ATTR_S1_AP_USER (1 << 0)
114#define ATTR_S1_NS (1 << 5)
115#define ATTR_S1_IDX(x) ((x) << 2)
116#define ATTR_S1_IDX_MASK (7 << 2)
117
118#define ATTR_S2_S2AP(x) ((x) << 6)
119#define ATTR_S2_S2AP_MASK 3
120#define ATTR_S2_S2AP_READ 1
121#define ATTR_S2_S2AP_WRITE 2
122
123#define ATTR_S2_MEMATTR(x) ((x) << 2)
124#define ATTR_S2_MEMATTR_MASK ATTR_S2_MEMATTR(0xf)
125#define ATTR_S2_MEMATTR_DEVICE_nGnRnE 0x0
126#define ATTR_S2_MEMATTR_NC 0xf
127#define ATTR_S2_MEMATTR_WT 0xa
128#define ATTR_S2_MEMATTR_WB 0xf
129
130#define ATTR_DESCR_MASK 3
131#define ATTR_DESCR_VALID 1
132#define ATTR_DESCR_TYPE_MASK 2
133#define ATTR_DESCR_TYPE_TABLE 2
134#define ATTR_DESCR_TYPE_PAGE 2
135#define ATTR_DESCR_TYPE_BLOCK 0
136
137/*
138 * Superpage promotion requires that the bits specified by the following
139 * mask all be identical in the constituent PTEs.
140 */
141#define ATTR_PROMOTE (ATTR_MASK & ~(ATTR_CONTIGUOUS | ATTR_AF))
142
143/* Read the output address or next-level table address from a PTE */
144#define PTE_TO_PHYS(x) ({ \
145 pt_entry_t _pte = (x); \
146 vm_paddr_t _pa; \
147 _pa = _pte & ATTR_ADDR; \
148 if (pmap_lpa_enabled) \
149 _pa |= (_pte & ATTR_OA_51_50_MASK) << ATTR_OA_51_50_DELTA; \
150 _pa; \
151})
152
153/*
154 * Convert a physical address to an output address or next-level
155 * table address in a PTE
156 */
157#define PHYS_TO_PTE(x) ({ \
158 vm_paddr_t _pa = (x); \
159 pt_entry_t _pte; \
160 _pte = _pa & ATTR_ADDR; \
161 if (pmap_lpa_enabled) \
162 _pte |= (_pa >> ATTR_OA_51_50_DELTA) & ATTR_OA_51_50_MASK; \
163 _pte; \
164})
165
166#if PAGE_SIZE == PAGE_SIZE_4K
167#define L0_SHIFT 39
168#define L1_SHIFT 30
169#define L2_SHIFT 21
170#define L3_SHIFT 12
171#elif PAGE_SIZE == PAGE_SIZE_16K
172#define L0_SHIFT 47
173#define L1_SHIFT 36
174#define L2_SHIFT 25
175#define L3_SHIFT 14
176#else
177#error Unsupported page size
178#endif
179
180/* Level 0 table, 512GiB/128TiB per entry */
181#define L0_SIZE (UINT64_C(1) << L0_SHIFT)
182#define L0_OFFSET (L0_SIZE - 1ul)
183#define L0_INVAL 0x0 /* An invalid address */
184 /* 0x1 Level 0 doesn't support block translation */
185 /* 0x2 also marks an invalid address */
186#define L0_TABLE 0x3 /* A next-level table */
187
188/* Level 1 table, 1GiB/64GiB per entry */
189#define L1_SIZE (UINT64_C(1) << L1_SHIFT)
190#define L1_OFFSET (L1_SIZE - 1)
191#define L1_INVAL L0_INVAL
192#define L1_BLOCK 0x1
193#define L1_TABLE L0_TABLE
194
195/* Level 2 table, 2MiB/32MiB per entry */
196#define L2_SIZE (UINT64_C(1) << L2_SHIFT)
197#define L2_OFFSET (L2_SIZE - 1)
198#define L2_INVAL L1_INVAL
199#define L2_BLOCK 0x1
200#define L2_TABLE L1_TABLE
201
202/* Level 3 table, 4KiB/16KiB per entry */
203#define L3_SIZE (1 << L3_SHIFT)
204#define L3_OFFSET (L3_SIZE - 1)
205#define L3_INVAL 0x0
206 /* 0x1 is reserved */
207 /* 0x2 also marks an invalid address */
208#define L3_PAGE 0x3
209
210/*
211 * A substantial portion of this is to make sure that we can cope with 4K
212 * framebuffers in early boot, assuming a common 4K resolution @ 32-bit depth.
213 */
214#define PMAP_MAPDEV_EARLY_SIZE (L2_SIZE * 20)
215
216#if PAGE_SIZE == PAGE_SIZE_4K
217#define L0_ENTRIES_SHIFT 9
218#define Ln_ENTRIES_SHIFT 9
219#elif PAGE_SIZE == PAGE_SIZE_16K
220#define L0_ENTRIES_SHIFT 1
221#define Ln_ENTRIES_SHIFT 11
222#else
223#error Unsupported page size
224#endif
225
226#define L0_ENTRIES (1 << L0_ENTRIES_SHIFT)
227#define L0_ADDR_MASK (L0_ENTRIES - 1)
228
229#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
230#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
231#define Ln_TABLE_MASK ((1 << 12) - 1)
232
233/*
234 * The number of contiguous Level 3 entries (with ATTR_CONTIGUOUS set) that
235 * can be coalesced into a single TLB entry
236 */
237#if PAGE_SIZE == PAGE_SIZE_4K
238#define L2C_ENTRIES 16
239#define L3C_ENTRIES 16
240#elif PAGE_SIZE == PAGE_SIZE_16K
241#define L2C_ENTRIES 32
242#define L3C_ENTRIES 128
243#else
244#error Unsupported page size
245#endif
246
247#define L2C_SIZE (L2C_ENTRIES * L2_SIZE)
248#define L2C_OFFSET (L2C_SIZE - 1)
249
250#define L3C_SIZE (L3C_ENTRIES * L3_SIZE)
251#define L3C_OFFSET (L3C_SIZE - 1)
252
253#define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
254#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
255#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
256#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
257
258#endif /* !_MACHINE_PTE_H_ */
259
260/* End of pte.h */
261
262#endif /* !__arm__ */