1/* $NetBSD: armreg.h,v 1.67 2025/02/27 08:39:54 andvar Exp $ */
2
3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _AARCH64_ARMREG_H_
33#define _AARCH64_ARMREG_H_
34
35#include <arm/cputypes.h>
36#include <sys/types.h>
37
38#ifdef __clang__
39#define ATTR_ARCH(arch) ".arch " arch ";"
40#define ATTR_TARGET_ARCH(x)
41#define ASM_ARCH(x) x
42#else
43#define ATTR_ARCH(arch) __attribute__((target("arch=" arch)))
44#define ATTR_TARGET_ARCH(x) x
45#define ASM_ARCH(x)
46#endif
47
48#define AARCH64REG_READ_INLINE3(regname, regdesc, arch) \
49static __inline uint64_t ATTR_TARGET_ARCH(arch) \
50reg_##regname##_read(void) \
51{ \
52 uint64_t __rv; \
53 __asm __volatile( \
54 ASM_ARCH(arch) \
55 "mrs %0, " #regdesc : "=r"(__rv) \
56 ); \
57 return __rv; \
58}
59
60#define AARCH64REG_READ_INLINE2(regname, regdesc) \
61 AARCH64REG_READ_INLINE3(regname, regdesc, )
62
63#define AARCH64REG_WRITE_INLINE3(regname, regdesc, arch) \
64static __inline void ATTR_TARGET_ARCH(arch) \
65reg_##regname##_write(uint64_t __val) \
66{ \
67 __asm __volatile( \
68 ASM_ARCH(arch) \
69 "msr " #regdesc ", %0" :: "r"(__val) : "memory" \
70 ); \
71}
72
73#define AARCH64REG_WRITE_INLINE2(regname, regdesc) \
74 AARCH64REG_WRITE_INLINE3(regname, regdesc, )
75
76#define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \
77static __inline void __always_inline \
78reg_##regname##_write(const uint64_t __val) \
79{ \
80 __asm __volatile( \
81 "msr " #regdesc ", %0" :: "n"(__val) : "memory" \
82 ); \
83}
84
85#define AARCH64REG_READ_INLINE(regname) \
86 AARCH64REG_READ_INLINE2(regname, regname)
87
88#define AARCH64REG_WRITE_INLINE(regname) \
89 AARCH64REG_WRITE_INLINE2(regname, regname)
90
91#define AARCH64REG_WRITEIMM_INLINE(regname) \
92 AARCH64REG_WRITEIMM_INLINE2(regname, regname)
93
94#define AARCH64REG_READWRITE_INLINE2(regname, regdesc) \
95 AARCH64REG_READ_INLINE2(regname, regdesc) \
96 AARCH64REG_WRITE_INLINE2(regname, regdesc)
97
98#define AARCH64REG_ATWRITE_INLINE2(regname, regdesc) \
99static __inline void \
100reg_##regname##_write(uint64_t __val) \
101{ \
102 __asm __volatile( \
103 "at " #regdesc ", %0" :: "r"(__val) : "memory" \
104 ); \
105}
106
107#define AARCH64REG_ATWRITE_INLINE(regname) \
108 AARCH64REG_ATWRITE_INLINE2(regname, regname)
109
110/*
111 * System registers available at EL0 (user)
112 */
113AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register
114
115#define CTR_EL0_TMIN_LINE __BITS(37,32) // Tag MIN LINE size
116#define CTR_EL0_DIC __BIT(29) // Instruction cache requirement
117#define CTR_EL0_IDC __BIT(28) // Data Cache clean requirement
118#define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule
119#define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule
120#define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2)
121#define CTR_EL0_L1IP_MASK __BITS(15,14)
122#define CTR_EL0_L1IP_VPIPT 0 // VMID-aware Physical Index, Physical Tag
123#define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag
124#define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag
125#define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag
126#define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2)
127
128AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register
129
130#define DCZID_DZP __BIT(4) // Data Zero Prohibited
131#define DCZID_BS __BITS(3,0) // Block Size (log2 - 2)
132
133AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register
134AARCH64REG_WRITE_INLINE(fpcr)
135
136#define FPCR_AHP __BIT(26) // Alternative Half Precision
137#define FPCR_DN __BIT(25) // Default Nan Control
138#define FPCR_FZ __BIT(24) // Flush-To-Zero
139#define FPCR_RMODE __BITS(23,22) // Rounding Mode
140#define FPCR_RN 0 // Round Nearest
141#define FPCR_RP 1 // Round towards Plus infinity
142#define FPCR_RM 2 // Round towards Minus infinity
143#define FPCR_RZ 3 // Round towards Zero
144#define FPCR_STRIDE __BITS(21,20)
145#define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16
146#define FPCR_LEN __BITS(18,16)
147#define FPCR_IDE __BIT(15) // Input Denormal Exception enable
148#define FPCR_IXE __BIT(12) // IneXact Exception enable
149#define FPCR_UFE __BIT(11) // UnderFlow Exception enable
150#define FPCR_OFE __BIT(10) // OverFlow Exception enable
151#define FPCR_DZE __BIT(9) // Divide by Zero Exception enable
152#define FPCR_IOE __BIT(8) // Invalid Operation Exception enable
153#define FPCR_ESUM 0x1F00
154
155AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register
156AARCH64REG_WRITE_INLINE(fpsr)
157
158#define FPSR_N32 __BIT(31) // AARCH32 Negative
159#define FPSR_Z32 __BIT(30) // AARCH32 Zero
160#define FPSR_C32 __BIT(29) // AARCH32 Carry
161#define FPSR_V32 __BIT(28) // AARCH32 Overflow
162#define FPSR_QC __BIT(27) // SIMD Saturation
163#define FPSR_IDC __BIT(7) // Input Denormal Cumulative status
164#define FPSR_IXC __BIT(4) // IneXact Cumulative status
165#define FPSR_UFC __BIT(3) // UnderFlow Cumulative status
166#define FPSR_OFC __BIT(2) // OverFlow Cumulative status
167#define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status
168#define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status
169#define FPSR_CSUM 0x1F
170
171AARCH64REG_READ_INLINE(nzcv) // condition codes
172AARCH64REG_WRITE_INLINE(nzcv)
173
174#define NZCV_N __BIT(31) // Negative
175#define NZCV_Z __BIT(30) // Zero
176#define NZCV_C __BIT(29) // Carry
177#define NZCV_V __BIT(28) // Overflow
178
179AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW)
180AARCH64REG_WRITE_INLINE(tpidr_el0)
181
182AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO)
183
184/*
185 * From here on, these can only be accessed at EL1 (kernel)
186 */
187
188/*
189 * These are readonly registers
190 */
191AARCH64REG_READ_INLINE(aidr_el1)
192
193AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57
194
195#define CBAR_PA __BITS(47,18)
196
197AARCH64REG_READ_INLINE(ccsidr_el1)
198
199/* 32bit format CCSIDR_EL1 */
200#define CCSIDR_WT __BIT(31) // OBSOLETE: Write-through supported
201#define CCSIDR_WB __BIT(30) // OBSOLETE: Write-back supported
202#define CCSIDR_RA __BIT(29) // OBSOLETE: Read-allocation supported
203#define CCSIDR_WA __BIT(28) // OBSOLETE: Write-allocation supported
204#define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1
205#define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1
206#define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line
207
208/* 64bit format CCSIDR_EL1 (ARMv8.3-CCIDX is implemented) */
209#define CCSIDR64_NUMSET __BITS(55,32) // (Number of sets in cache) - 1
210#define CCSIDR64_ASSOC __BITS(23,3) // (Associativity of cache) - 1
211#define CCSIDR64_LINESIZE __BITS(2,0) // Number of bytes in cache line
212
213AARCH64REG_READ_INLINE(clidr_el1)
214
215#define CLIDR_ICB __BITS(32,30) // Inner cache boundary
216#define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor
217#define CLIDR_LOC __BITS(26,24) // Level of Coherency
218#define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/
219#define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7
220#define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6
221#define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5
222#define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4
223#define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3
224#define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2
225#define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1
226#define CLIDR_TYPE_NOCACHE 0 // No cache
227#define CLIDR_TYPE_ICACHE 1 // Instruction cache only
228#define CLIDR_TYPE_DCACHE 2 // Data cache only
229#define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches
230#define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache
231
232AARCH64REG_READ_INLINE(contextidr_el1)
233AARCH64REG_WRITE_INLINE(contextidr_el1)
234
235AARCH64REG_READ_INLINE(currentel)
236
237#define CURRENTEL_EL __BITS(3,2) // Current exception Level
238
239AARCH64REG_READ_INLINE(id_aa64afr0_el1)
240AARCH64REG_READ_INLINE(id_aa64afr1_el1)
241AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
242
243#define ID_AA64DFR0_EL1_TRACEFILT __BITS(43,40)
244#define ID_AA64DFR0_EL1_TRACEFILT_NONE 0
245#define ID_AA64DFR0_EL1_TRACEFILT_IMPL 1
246#define ID_AA64DFR0_EL1_DBLLOCK __BITS(39,36)
247#define ID_AA64DFR0_EL1_DBLLOCK_IMPL 0
248#define ID_AA64DFR0_EL1_DBLLOCK_NONE 15
249#define ID_AA64DFR0_EL1_PMSVER __BITS(35,32)
250#define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28)
251#define ID_AA64DFR0_EL1_WRPS __BITS(20,23)
252#define ID_AA64DFR0_EL1_BRPS __BITS(12,15)
253#define ID_AA64DFR0_EL1_PMUVER __BITS(8,11)
254#define ID_AA64DFR0_EL1_PMUVER_NONE 0
255#define ID_AA64DFR0_EL1_PMUVER_V3 1
256#define ID_AA64DFR0_EL1_PMUVER_NOV3 2
257#define ID_AA64DFR0_EL1_PMUVER_V3P1 4
258#define ID_AA64DFR0_EL1_PMUVER_V3P4 5
259#define ID_AA64DFR0_EL1_PMUVER_V3P5 6
260#define ID_AA64DFR0_EL1_PMUVER_V3P7 7
261#define ID_AA64DFR0_EL1_PMUVER_IMPL 15
262#define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)
263#define ID_AA64DFR0_EL1_TRACEVER_NONE 0
264#define ID_AA64DFR0_EL1_TRACEVER_IMPL 1
265#define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3)
266#define ID_AA64DFR0_EL1_DEBUGVER_V8A 6
267
268AARCH64REG_READ_INLINE(id_aa64dfr1_el1)
269
270AARCH64REG_READ_INLINE(id_aa64isar0_el1)
271
272#define ID_AA64ISAR0_EL1_RNDR __BITS(63,60)
273#define ID_AA64ISAR0_EL1_RNDR_NONE 0
274#define ID_AA64ISAR0_EL1_RNDR_RNDRRS 1
275#define ID_AA64ISAR0_EL1_TLB __BITS(59,56)
276#define ID_AA64ISAR0_EL1_TLB_NONE 0
277#define ID_AA64ISAR0_EL1_TLB_OS 1
278#define ID_AA64ISAR0_EL1_TLB_OS_TLB 2
279#define ID_AA64ISAR0_EL1_TS __BITS(55,52)
280#define ID_AA64ISAR0_EL1_TS_NONE 0
281#define ID_AA64ISAR0_EL1_TS_CFINV 1
282#define ID_AA64ISAR0_EL1_TS_AXFLAG 2
283#define ID_AA64ISAR0_EL1_FHM __BITS(51,48)
284#define ID_AA64ISAR0_EL1_FHM_NONE 0
285#define ID_AA64ISAR0_EL1_FHM_FMLAL 1
286#define ID_AA64ISAR0_EL1_DP __BITS(47,44)
287#define ID_AA64ISAR0_EL1_DP_NONE 0
288#define ID_AA64ISAR0_EL1_DP_UDOT 1
289#define ID_AA64ISAR0_EL1_SM4 __BITS(43,40)
290#define ID_AA64ISAR0_EL1_SM4_NONE 0
291#define ID_AA64ISAR0_EL1_SM4_SM4 1
292#define ID_AA64ISAR0_EL1_SM3 __BITS(39,36)
293#define ID_AA64ISAR0_EL1_SM3_NONE 0
294#define ID_AA64ISAR0_EL1_SM3_SM3 1
295#define ID_AA64ISAR0_EL1_SHA3 __BITS(35,32)
296#define ID_AA64ISAR0_EL1_SHA3_NONE 0
297#define ID_AA64ISAR0_EL1_SHA3_EOR3 1
298#define ID_AA64ISAR0_EL1_RDM __BITS(31,28)
299#define ID_AA64ISAR0_EL1_RDM_NONE 0
300#define ID_AA64ISAR0_EL1_RDM_SQRDML 1
301#define ID_AA64ISAR0_EL1_ATOMIC __BITS(23,20)
302#define ID_AA64ISAR0_EL1_ATOMIC_NONE 0
303#define ID_AA64ISAR0_EL1_ATOMIC_SWP 2
304#define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16)
305#define ID_AA64ISAR0_EL1_CRC32_NONE 0
306#define ID_AA64ISAR0_EL1_CRC32_CRC32X 1
307#define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12)
308#define ID_AA64ISAR0_EL1_SHA2_NONE 0
309#define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1
310#define ID_AA64ISAR0_EL1_SHA2_SHA512HSU 2
311#define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8)
312#define ID_AA64ISAR0_EL1_SHA1_NONE 0
313#define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1
314#define ID_AA64ISAR0_EL1_AES __BITS(7,4)
315#define ID_AA64ISAR0_EL1_AES_NONE 0
316#define ID_AA64ISAR0_EL1_AES_AES 1
317#define ID_AA64ISAR0_EL1_AES_PMUL 2
318
319AARCH64REG_READ_INLINE(id_aa64isar1_el1)
320
321#define ID_AA64ISAR1_EL1_I8MM __BITS(55,52)
322#define ID_AA64ISAR1_EL1_I8MM_NONE 0
323#define ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
324#define ID_AA64ISAR1_EL1_DGH __BITS(51,48)
325#define ID_AA64ISAR1_EL1_DGH_NONE 0
326#define ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
327#define ID_AA64ISAR1_EL1_BF16 __BITS(47,44)
328#define ID_AA64ISAR1_EL1_BF16_NONE 0
329#define ID_AA64ISAR1_EL1_BF16_BFDOT 1
330#define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)
331#define ID_AA64ISAR1_EL1_SPECRES_NONE 0
332#define ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
333#define ID_AA64ISAR1_EL1_SB __BITS(39,36)
334#define ID_AA64ISAR1_EL1_SB_NONE 0
335#define ID_AA64ISAR1_EL1_SB_SUPPORTED 1
336#define ID_AA64ISAR1_EL1_FRINTTS __BITS(35,32)
337#define ID_AA64ISAR1_EL1_FRINTTS_NONE 0
338#define ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
339#define ID_AA64ISAR1_EL1_GPI __BITS(31,28)
340#define ID_AA64ISAR1_EL1_GPI_NONE 0
341#define ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
342#define ID_AA64ISAR1_EL1_GPA __BITS(27,24)
343#define ID_AA64ISAR1_EL1_GPA_NONE 0
344#define ID_AA64ISAR1_EL1_GPA_QARMA 1
345#define ID_AA64ISAR1_EL1_LRCPC __BITS(23,20)
346#define ID_AA64ISAR1_EL1_LRCPC_NONE 0
347#define ID_AA64ISAR1_EL1_LRCPC_PR 1
348#define ID_AA64ISAR1_EL1_LRCPC_PR_UR 2
349#define ID_AA64ISAR1_EL1_FCMA __BITS(19,16)
350#define ID_AA64ISAR1_EL1_FCMA_NONE 0
351#define ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
352#define ID_AA64ISAR1_EL1_JSCVT __BITS(15,12)
353#define ID_AA64ISAR1_EL1_JSCVT_NONE 0
354#define ID_AA64ISAR1_EL1_JSCVT_SUPPORTED 1
355#define ID_AA64ISAR1_EL1_API __BITS(11,8)
356#define ID_AA64ISAR1_EL1_API_NONE 0
357#define ID_AA64ISAR1_EL1_API_SUPPORTED 1
358#define ID_AA64ISAR1_EL1_API_ENHANCED 2
359#define ID_AA64ISAR1_EL1_APA __BITS(7,4)
360#define ID_AA64ISAR1_EL1_APA_NONE 0
361#define ID_AA64ISAR1_EL1_APA_QARMA 1
362#define ID_AA64ISAR1_EL1_APA_QARMA_ENH 2
363#define ID_AA64ISAR1_EL1_DPB __BITS(3,0)
364#define ID_AA64ISAR1_EL1_DPB_NONE 0
365#define ID_AA64ISAR1_EL1_DPB_CVAP 1
366#define ID_AA64ISAR1_EL1_DPB_CVAP_CVADP 2
367
368AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
369
370#define ID_AA64MMFR0_EL1_EXS __BITS(43,40)
371#define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28)
372#define ID_AA64MMFR0_EL1_TGRAN4_4KB 0
373#define ID_AA64MMFR0_EL1_TGRAN4_NONE 15
374#define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27)
375#define ID_AA64MMFR0_EL1_TGRAN64_64KB 0
376#define ID_AA64MMFR0_EL1_TGRAN64_NONE 15
377#define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23)
378#define ID_AA64MMFR0_EL1_TGRAN16_NONE 0
379#define ID_AA64MMFR0_EL1_TGRAN16_16KB 1
380#define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19)
381#define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0
382#define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1
383#define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15)
384#define ID_AA64MMFR0_EL1_SNSMEM_NONE 0
385#define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1
386#define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11)
387#define ID_AA64MMFR0_EL1_BIGEND_NONE 0
388#define ID_AA64MMFR0_EL1_BIGEND_MIX 1
389#define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7)
390#define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0
391#define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2
392#define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3)
393#define ID_AA64MMFR0_EL1_PARANGE_4G 0
394#define ID_AA64MMFR0_EL1_PARANGE_64G 1
395#define ID_AA64MMFR0_EL1_PARANGE_1T 2
396#define ID_AA64MMFR0_EL1_PARANGE_4T 3
397#define ID_AA64MMFR0_EL1_PARANGE_16T 4
398#define ID_AA64MMFR0_EL1_PARANGE_256T 5
399#define ID_AA64MMFR0_EL1_PARANGE_4P 6
400
401AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
402
403#define ID_AA64MMFR1_EL1_XNX __BITS(31,28)
404#define ID_AA64MMFR1_EL1_XNX_NONE 0
405#define ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
406#define ID_AA64MMFR1_EL1_SPECSEI __BITS(27,24)
407#define ID_AA64MMFR1_EL1_SPECSEI_NONE 0
408#define ID_AA64MMFR1_EL1_SPECSEI_EXTINT 1
409#define ID_AA64MMFR1_EL1_PAN __BITS(23,20)
410#define ID_AA64MMFR1_EL1_PAN_NONE 0
411#define ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
412#define ID_AA64MMFR1_EL1_PAN_S1E1 2
413#define ID_AA64MMFR1_EL1_LO __BITS(19,16)
414#define ID_AA64MMFR1_EL1_LO_NONE 0
415#define ID_AA64MMFR1_EL1_LO_SUPPORTED 1
416#define ID_AA64MMFR1_EL1_HPDS __BITS(15,12)
417#define ID_AA64MMFR1_EL1_HPDS_NONE 0
418#define ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
419#define ID_AA64MMFR1_EL1_HPDS_EXTRA_PTD 2
420#define ID_AA64MMFR1_EL1_VH __BITS(11,8)
421#define ID_AA64MMFR1_EL1_VH_NONE 0
422#define ID_AA64MMFR1_EL1_VH_SUPPORTED 1
423#define ID_AA64MMFR1_EL1_VMIDBITS __BITS(7,4)
424#define ID_AA64MMFR1_EL1_VMIDBITS_8BIT 0
425#define ID_AA64MMFR1_EL1_VMIDBITS_16BIT 2
426#define ID_AA64MMFR1_EL1_HAFDBS __BITS(3,0)
427#define ID_AA64MMFR1_EL1_HAFDBS_NONE 0
428#define ID_AA64MMFR1_EL1_HAFDBS_A 1
429#define ID_AA64MMFR1_EL1_HAFDBS_AD 2
430
431AARCH64REG_READ_INLINE3(id_aa64mmfr2_el1, id_aa64mmfr2_el1,
432 ATTR_ARCH("armv8.2-a"))
433
434#define ID_AA64MMFR2_EL1_E0PD __BITS(63,60)
435#define ID_AA64MMFR2_EL1_E0PD_NONE 0
436#define ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
437#define ID_AA64MMFR2_EL1_EVT __BITS(59,56)
438#define ID_AA64MMFR2_EL1_EVT_NONE 0
439#define ID_AA64MMFR2_EL1_EVT_TO_TI 1
440#define ID_AA64MMFR2_EL1_EVT_TO_TI_TTL 2
441#define ID_AA64MMFR2_EL1_BBM __BITS(55,52)
442#define ID_AA64MMFR2_EL1_BBM_L0 0
443#define ID_AA64MMFR2_EL1_BBM_L1 1
444#define ID_AA64MMFR2_EL1_BBM_L2 2
445#define ID_AA64MMFR2_EL1_TTL __BITS(51,48)
446#define ID_AA64MMFR2_EL1_TTL_NONE 0
447#define ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
448#define ID_AA64MMFR2_EL1_FWB __BITS(43,40)
449#define ID_AA64MMFR2_EL1_FWB_NONE 0
450#define ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
451#define ID_AA64MMFR2_EL1_IDS __BITS(39,36)
452#define ID_AA64MMFR2_EL1_IDS_0X0 0
453#define ID_AA64MMFR2_EL1_IDS_0X18 1
454#define ID_AA64MMFR2_EL1_AT __BITS(35,32)
455#define ID_AA64MMFR2_EL1_AT_NONE 0
456#define ID_AA64MMFR2_EL1_AT_16BIT 1
457#define ID_AA64MMFR2_EL1_ST __BITS(31,28)
458#define ID_AA64MMFR2_EL1_ST_39 0
459#define ID_AA64MMFR2_EL1_ST_48 1
460#define ID_AA64MMFR2_EL1_NV __BITS(27,24)
461#define ID_AA64MMFR2_EL1_NV_NONE 0
462#define ID_AA64MMFR2_EL1_NV_HCR 1
463#define ID_AA64MMFR2_EL1_NV_HCR_VNCR 2
464#define ID_AA64MMFR2_EL1_CCIDX __BITS(23,20)
465#define ID_AA64MMFR2_EL1_CCIDX_32BIT 0
466#define ID_AA64MMFR2_EL1_CCIDX_64BIT 1
467#define ID_AA64MMFR2_EL1_VARANGE __BITS(19,16)
468#define ID_AA64MMFR2_EL1_VARANGE_48BIT 0
469#define ID_AA64MMFR2_EL1_VARANGE_52BIT 1
470#define ID_AA64MMFR2_EL1_IESB __BITS(15,12)
471#define ID_AA64MMFR2_EL1_IESB_NONE 0
472#define ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
473#define ID_AA64MMFR2_EL1_LSM __BITS(11,8)
474#define ID_AA64MMFR2_EL1_LSM_NONE 0
475#define ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
476#define ID_AA64MMFR2_EL1_UAO __BITS(7,4)
477#define ID_AA64MMFR2_EL1_UAO_NONE 0
478#define ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
479#define ID_AA64MMFR2_EL1_CNP __BITS(3,0)
480#define ID_AA64MMFR2_EL1_CNP_NONE 0
481#define ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
482
483AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
484AARCH64REG_READ_INLINE(id_aa64pfr0_el1)
485AARCH64REG_READ_INLINE(id_aa64pfr1_el1)
486
487#define ID_AA64PFR1_EL1_RASFRAC __BITS(15,12)
488#define ID_AA64PFR1_EL1_RASFRAC_NORMAL 0
489#define ID_AA64PFR1_EL1_RASFRAC_EXTRA 1
490#define ID_AA64PFR1_EL1_MTE __BITS(11,8)
491#define ID_AA64PFR1_EL1_MTE_NONE 0
492#define ID_AA64PFR1_EL1_MTE_PARTIAL 1
493#define ID_AA64PFR1_EL1_MTE_SUPPORTED 2
494#define ID_AA64PFR1_EL1_SSBS __BITS(7,4)
495#define ID_AA64PFR1_EL1_SSBS_NONE 0
496#define ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
497#define ID_AA64PFR1_EL1_SSBS_MSR_MRS 2
498#define ID_AA64PFR1_EL1_BT __BITS(3,0)
499#define ID_AA64PFR1_EL1_BT_NONE 0
500#define ID_AA64PFR1_EL1_BT_SUPPORTED 1
501
502AARCH64REG_READ_INLINE(id_aa64zfr0_el1)
503AARCH64REG_READ_INLINE(id_pfr1_el1)
504AARCH64REG_READ_INLINE(isr_el1)
505AARCH64REG_READ_INLINE(midr_el1)
506AARCH64REG_READ_INLINE(mpidr_el1)
507
508#define MIDR_EL1_IMPL __BITS(31,24) // Implementor
509#define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant
510#define MIDR_EL1_ARCH __BITS(19,16) // Architecture
511#define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum
512#define MIDR_EL1_REVISION __BITS(3,0) // Revision
513
514#define MPIDR_AFF3 __BITS(32,39)
515#define MPIDR_U __BIT(30) // 1 = Uni-Processor System
516#define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical)
517#define MPIDR_AFF2 __BITS(16,23)
518#define MPIDR_AFF1 __BITS(8,15)
519#define MPIDR_AFF0 __BITS(0,7)
520
521AARCH64REG_READ_INLINE(mvfr0_el1)
522
523#define MVFR0_FPROUND __BITS(31,28)
524#define MVFR0_FPROUND_NEAREST 0
525#define MVFR0_FPROUND_ALL 1
526#define MVFR0_FPSHVEC __BITS(27,24)
527#define MVFR0_FPSHVEC_NONE 0
528#define MVFR0_FPSHVEC_SHVEC 1
529#define MVFR0_FPSQRT __BITS(23,20)
530#define MVFR0_FPSQRT_NONE 0
531#define MVFR0_FPSQRT_VSQRT 1
532#define MVFR0_FPDIVIDE __BITS(19,16)
533#define MVFR0_FPDIVIDE_NONE 0
534#define MVFR0_FPDIVIDE_VDIV 1
535#define MVFR0_FPTRAP __BITS(15,12)
536#define MVFR0_FPTRAP_NONE 0
537#define MVFR0_FPTRAP_TRAP 1
538#define MVFR0_FPDP __BITS(11,8)
539#define MVFR0_FPDP_NONE 0
540#define MVFR0_FPDP_VFPV2 1
541#define MVFR0_FPDP_VFPV3 2
542#define MVFR0_FPSP __BITS(7,4)
543#define MVFR0_FPSP_NONE 0
544#define MVFR0_FPSP_VFPV2 1
545#define MVFR0_FPSP_VFPV3 2
546#define MVFR0_SIMDREG __BITS(3,0)
547#define MVFR0_SIMDREG_NONE 0
548#define MVFR0_SIMDREG_16x64 1
549#define MVFR0_SIMDREG_32x64 2
550
551AARCH64REG_READ_INLINE(mvfr1_el1)
552
553#define MVFR1_SIMDFMAC __BITS(31,28)
554#define MVFR1_SIMDFMAC_NONE 0
555#define MVFR1_SIMDFMAC_FMAC 1
556#define MVFR1_FPHP __BITS(27,24)
557#define MVFR1_FPHP_NONE 0
558#define MVFR1_FPHP_HALF_SINGLE 1
559#define MVFR1_FPHP_HALF_DOUBLE 2
560#define MVFR1_FPHP_HALF_ARITH 3
561#define MVFR1_SIMDHP __BITS(23,20)
562#define MVFR1_SIMDHP_NONE 0
563#define MVFR1_SIMDHP_HALF 1
564#define MVFR1_SIMDHP_HALF_ARITH 3
565#define MVFR1_SIMDSP __BITS(19,16)
566#define MVFR1_SIMDSP_NONE 0
567#define MVFR1_SIMDSP_SINGLE 1
568#define MVFR1_SIMDINT __BITS(15,12)
569#define MVFR1_SIMDINT_NONE 0
570#define MVFR1_SIMDINT_INTEGER 1
571#define MVFR1_SIMDLS __BITS(11,8)
572#define MVFR1_SIMDLS_NONE 0
573#define MVFR1_SIMDLS_LOADSTORE 1
574#define MVFR1_FPDNAN __BITS(7,4)
575#define MVFR1_FPDNAN_NONE 0
576#define MVFR1_FPDNAN_NAN 1
577#define MVFR1_FPFTZ __BITS(3,0)
578#define MVFR1_FPFTZ_NONE 0
579#define MVFR1_FPFTZ_DENORMAL 1
580
581AARCH64REG_READ_INLINE(mvfr2_el1)
582
583#define MVFR2_FPMISC __BITS(7,4)
584#define MVFR2_FPMISC_NONE 0
585#define MVFR2_FPMISC_SEL 1
586#define MVFR2_FPMISC_DROUND 2
587#define MVFR2_FPMISC_ROUNDINT 3
588#define MVFR2_FPMISC_MAXMIN 4
589#define MVFR2_SIMDMISC __BITS(3,0)
590#define MVFR2_SIMDMISC_NONE 0
591#define MVFR2_SIMDMISC_DROUND 1
592#define MVFR2_SIMDMISC_ROUNDINT 2
593#define MVFR2_SIMDMISC_MAXMIN 3
594
595AARCH64REG_READ_INLINE(revidr_el1)
596
597/*
598 * These are read/write registers
599 */
600AARCH64REG_READ_INLINE3(APIAKeyLo_EL1, apiakeylo_el1, ATTR_ARCH("armv8.3-a"))
601AARCH64REG_WRITE_INLINE3(APIAKeyLo_EL1, apiakeylo_el1, ATTR_ARCH("armv8.3-a"))
602AARCH64REG_READ_INLINE3(APIAKeyHi_EL1, apiakeyhi_el1, ATTR_ARCH("armv8.3-a"))
603AARCH64REG_WRITE_INLINE3(APIAKeyHi_EL1, apiakeyhi_el1, ATTR_ARCH("armv8.3-a"))
604
605AARCH64REG_READ_INLINE3(APIBKeyLo_EL1, apibkeylo_el1, ATTR_ARCH("armv8.3-a"))
606AARCH64REG_WRITE_INLINE3(APIBKeyLo_EL1, apibkeylo_el1, ATTR_ARCH("armv8.3-a"))
607AARCH64REG_READ_INLINE3(APIBKeyHi_EL1, apibkeyhi_el1, ATTR_ARCH("armv8.3-a"))
608AARCH64REG_WRITE_INLINE3(APIBKeyHi_EL1, apibkeyhi_el1, ATTR_ARCH("armv8.3-a"))
609
610AARCH64REG_READ_INLINE3(APDAKeyLo_EL1, apdakeylo_el1, ATTR_ARCH("armv8.3-a"))
611AARCH64REG_WRITE_INLINE3(APDAKeyLo_EL1, apdakeylo_el1, ATTR_ARCH("armv8.3-a"))
612AARCH64REG_READ_INLINE3(APDAKeyHi_EL1, apdakeyhi_el1, ATTR_ARCH("armv8.3-a"))
613AARCH64REG_WRITE_INLINE3(APDAKeyHi_EL1, apdakeyhi_el1, ATTR_ARCH("armv8.3-a"))
614
615AARCH64REG_READ_INLINE3(APDBKeyLo_EL1, apdbkeylo_el1, ATTR_ARCH("armv8.3-a"))
616AARCH64REG_WRITE_INLINE3(APDBKeyLo_EL1, apdbkeylo_el1, ATTR_ARCH("armv8.3-a"))
617AARCH64REG_READ_INLINE3(APDBKeyHi_EL1, apdbkeyhi_el1, ATTR_ARCH("armv8.3-a"))
618AARCH64REG_WRITE_INLINE3(APDBKeyHi_EL1, apdbkeyhi_el1, ATTR_ARCH("armv8.3-a"))
619
620AARCH64REG_READ_INLINE3(APGAKeyLo_EL1, apgakeylo_el1, ATTR_ARCH("armv8.3-a"))
621AARCH64REG_WRITE_INLINE3(APGAKeyLo_EL1, apgakeylo_el1, ATTR_ARCH("armv8.3-a"))
622AARCH64REG_READ_INLINE3(APGAKeyHi_EL1, apgakeyhi_el1, ATTR_ARCH("armv8.3-a"))
623AARCH64REG_WRITE_INLINE3(APGAKeyHi_EL1, apgakeyhi_el1, ATTR_ARCH("armv8.3-a"))
624
625AARCH64REG_READ_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
626AARCH64REG_WRITE_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
627
628AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Register
629AARCH64REG_WRITE_INLINE(cpacr_el1)
630
631#define CPACR_TTA __BIT(28) // System Register Access Traps
632#define CPACR_FPEN __BITS(21,20)
633#define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)
634#define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)
635#define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)
636#define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)
637
638AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register
639AARCH64REG_WRITE_INLINE(csselr_el1)
640
641#define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache
642#define CSSELR_IND __BIT(0) // Instruction not Data bit
643
644AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register
645AARCH64REG_WRITE_INLINE(daif)
646AARCH64REG_WRITEIMM_INLINE(daifclr)
647AARCH64REG_WRITEIMM_INLINE(daifset)
648
649#define DAIF_D __BIT(9) // Debug Exception Mask
650#define DAIF_A __BIT(8) // SError Abort Mask
651#define DAIF_I __BIT(7) // IRQ Mask
652#define DAIF_F __BIT(6) // FIQ Mask
653#define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift
654
655AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register
656AARCH64REG_WRITE_INLINE(elr_el1)
657
658AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register
659AARCH64REG_WRITE_INLINE(esr_el1)
660
661#define ESR_EC __BITS(31,26) // Exception Cause
662#define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason
663#define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution
664#define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0
665#define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0
666#define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14
667#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
668#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
669#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
670#define ESR_EC_PAUTH 0x09 // A64: Pointer auth trap (FEAT_PAUTH)
671#define ESR_EC_LS64 0x0a // AXX: LD64B/ST64B instruction (FEAT_LS64) // XXXNH
672#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
673#define ESR_EC_BTE_A64 0x0d // A64: Branch Target Exception (V8.5)
674#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
675#define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution
676#define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution
677#define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution
678#define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution
679#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
680#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
681#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
682#define ESR_EC_SVE 0x19 // AXX: SVE Instruction Execution (FEAT_SVE)
683#define ESR_EC_PAUTH_ERET 0x1a // A64: ERET/ERETAA/ERETAB (FEAT_PAUTH and FEAT_NV)
684#define ESR_EC_TME 0x1b // A64: TSTART instruction (FEAT_TME)
685#define ESR_EC_FRAC 0x1c // A64: Pointer auth trap (FEAT_FPAC)
686#define ESR_EC_SME 0x1d // AXX: Access to SME (FEAT_SME)
687#define ESR_EC_RME 0x1e // A64: Granule Protection Check (FEAT_RME)
688#define ESR_EC_INSN_ABT_EL_LOW 0x20 // AXX: Instruction Abort from lower level
689#define ESR_EC_INSN_ABT_EL_CUR 0x21 // AXX: Instruction Abort from current level
690#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
691#define ESR_EC_DATA_ABT_EL_LOW 0x24 // AXX: Data Abort from lower level
692#define ESR_EC_DATA_ABT_EL_CUR 0x25 // AXX: Data Abort from current level
693#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
694#define ESR_EC_MOPS 0x27 // A64: Memory Operation Exception (FEAT_MOPS)
695#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
696#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
697#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
698#define ESR_EC_BRKPNT_EL_LOW 0x30 // AXX: Breakpoint Exception from lower level
699#define ESR_EC_BRKPNT_EL_CUR 0x31 // AXX: Breakpoint Exception from current level
700#define ESR_EC_SW_STEP_EL_LOW 0x32 // AXX: Software Step from lower level
701#define ESR_EC_SW_STEP_EL_CUR 0x33 // AXX: Software Step from current level
702#define ESR_EC_WTCHPNT_EL_LOW 0x34 // AXX: Watchpoint from lower level
703#define ESR_EC_WTCHPNT_EL_CUR 0x35 // AXX: Watchpoint from current level
704#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
705#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
706#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
707/* alias for EL1 kernel */
708#define ESR_EC_INSN_ABT_EL0 ESR_EC_INSN_ABT_EL_LOW
709#define ESR_EC_INSN_ABT_EL1 ESR_EC_INSN_ABT_EL_CUR
710#define ESR_EC_DATA_ABT_EL0 ESR_EC_DATA_ABT_EL_LOW
711#define ESR_EC_DATA_ABT_EL1 ESR_EC_DATA_ABT_EL_CUR
712#define ESR_EC_BRKPNT_EL0 ESR_EC_BRKPNT_EL_LOW
713#define ESR_EC_BRKPNT_EL1 ESR_EC_BRKPNT_EL_CUR
714#define ESR_EC_SW_STEP_EL0 ESR_EC_SW_STEP_EL_LOW
715#define ESR_EC_SW_STEP_EL1 ESR_EC_SW_STEP_EL_CUR
716#define ESR_EC_WTCHPNT_EL0 ESR_EC_WTCHPNT_EL_LOW
717#define ESR_EC_WTCHPNT_EL1 ESR_EC_WTCHPNT_EL_CUR
718#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
719#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
720#define ESR_ISS_CV __BIT(24) // common
721#define ESR_ISS_COND __BITS(23,20) // common
722#define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
723#define ESR_ISS_SYSREG_OP0 __BITS(21,20) // for ESR_EC_SYS_REG
724#define ESR_ISS_SYSREG_OP2 __BITS(19,17) // for ESR_EC_SYS_REG
725#define ESR_ISS_SYSREG_OP1 __BITS(16,14) // for ESR_EC_SYS_REG
726#define ESR_ISS_SYSREG_CRN __BITS(13,10) // for ESR_EC_SYS_REG
727#define ESR_ISS_SYSREG_RT __BITS(9,5) // for ESR_EC_SYS_REG
728#define ESR_ISS_SYSREG_CRM __BITS(4,1) // for ESR_EC_SYS_REG
729#define ESR_ISS_SYSREG_DIRECTION __BIT(0) // for ESR_EC_SYS_REG
730#define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT
731#define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT
732#define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT
733#define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT
734#define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT
735#define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT
736#define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT
737#define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT
738#define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT
739#define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT
740#define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT
741#define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC}
742// ...
743#define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01]
744#define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01]
745#define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01]
746#define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01]
747#define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01]
748#define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01]
749#define ESR_ISS_DATAABORT_SRT __BITS(20,16) // for ESC_RC_DATA_ABT_EL[01]
750#define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01]
751#define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01]
752#define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01]
753#define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01]
754#define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01]
755#define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01]
756#define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01]
757
758#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00
759#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01
760#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02
761#define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03
762#define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04
763#define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05
764#define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06
765#define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07
766#define ESR_ISS_FSC_ACCESS_FAULT_0 0x08
767#define ESR_ISS_FSC_ACCESS_FAULT_1 0x09
768#define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a
769#define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b
770#define ESR_ISS_FSC_PERM_FAULT_0 0x0c
771#define ESR_ISS_FSC_PERM_FAULT_1 0x0d
772#define ESR_ISS_FSC_PERM_FAULT_2 0x0e
773#define ESR_ISS_FSC_PERM_FAULT_3 0x0f
774#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10
775#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14
776#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15
777#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16
778#define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17
779#define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18
780#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c
781#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d
782#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e
783#define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f
784#define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21
785#define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30
786#define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34
787#define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35
788#define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d
789#define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e
790
791
792AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
793AARCH64REG_WRITE_INLINE(far_el1)
794AARCH64REG_READ_INLINE(far_el2)
795AARCH64REG_WRITE_INLINE(far_el2)
796
797AARCH64REG_READ_INLINE(hcr_el2) // Hypervisor Configuration Register
798AARCH64REG_WRITE_INLINE(hcr_el2)
799
800#define HCR_EL2_TWEDEL __BITS(63,60) // TWE Delay (FEAT_TWED)
801#define HCR_EL2_TWEDEN __BIT(59) // TWE Delay Enable (FEAT_TWED)
802#define HCR_EL2_TID5 __BIT(58) // Trap ID group 5 (FEAT_MTE2)
803#define HCR_EL2_DCT __BIT(57) // Default Cacheability Tagging (FEAT_MTE2)
804#define HCR_EL2_ATA __BIT(56) // Allocation Tag Access (FEAT_MTE2)
805#define HCR_EL2_TTLBOS __BIT(55) // Trap TLB maintenance OS (FEAT_EVT)
806#define HCR_EL2_TTLBIS __BIT(54) // Trap TLB maintenance IS (FEAT_EVT)
807#define HCR_EL2_ENSCXT __BIT(53) // Enable SCXTNUM_EL[01] access (FEAT_CSV2)
808#define HCR_EL2_TOCU __BIT(52) // Trap PoU cache maintenance
809#define HCR_EL2_AMVOFFEN __BIT(51) // Activity Monitors Virtual Offsets Enable (FEAT_AMUv1p1)
810#define HCR_EL2_TICAB __BIT(50) // Trap IC all broadcast maintenance.
811#define HCR_EL2_TID4 __BIT(49) // Trap ID group 4 (FEAT_EVT)
812#define HCR_EL2_GPF __BIT(48) // Granule Protection Faults (FEAT_RME)
813#define HCR_EL2_FIEN __BIT(47) // Fault Injection Enable (FEAT_RASv1p1)
814#define HCR_EL2_FWB __BIT(46) // Forced Write-Back (FEAT_S2FWB)
815#define HCR_EL2_NV2 __BIT(45) // Nested Virtualization (FEAT_NV2)
816#define HCR_EL2_AT __BIT(44) // Address Translation (FEAT_NV)
817#define HCR_EL2_NV1 __BIT(43) // Nested Virtualization (FEAT_NV2/FEAT_NV)
818#define HCR_EL2_NV __BIT(42) // Nested Virtualization (FEAT_NV2/FEAT_NV)
819#define HCR_EL2_API __BIT(41) // Pointer Authentication instruction (FEAT_PAuth)
820#define HCR_EL2_APK __BIT(40) // Pointer Authentication key (FEAT_PAuth)
821#define HCR_EL2_TME __BIT(39) // TME enable (FEAT_TME)
822#define HCR_EL2_MIOCNCE __BIT(38) // Mismatched Inner/Outer Cacheable Non-Coherency Enable,
823#define HCR_EL2_TEA __BIT(37) // Route synchronous External abort exceptions to EL2 (FEAT_RAS)
824#define HCR_EL2_TERR __BIT(36) // Trap accesses of Error Record registers (FEAT_RAS)
825#define HCR_EL2_TLOR __BIT(35) // Trap LOR registers (FEAT_LOR)
826#define HCR_EL2_VHE __BIT(34) // EL2 Host (FEAT_VHE)
827#define HCR_EL2_ID __BIT(33) // stage2 IC disable
828#define HCR_EL2_CD __BIT(32) // stage2 DC disable
829#define HCR_EL2_RW __BIT(31) // register width
830#define HCR_EL2_TRVM __BIT(30) // trap VM control regs read
831#define HCR_EL2_HCD __BIT(29) // HVC disable
832#define HCR_EL2_TDZ __BIT(28) // trap DC ZVA
833#define HCR_EL2_TGE __BIT(27) // trap general exceptions
834#define HCR_EL2_TVM __BIT(26) // trap VM control regs write
835#define HCR_EL2_TTLB __BIT(25) // trap TLB maintenance op
836#define HCR_EL2_TPU __BIT(24) // trap IC {IVAU,IALLU,IALLUIS},DC CVAU
837#define HCR_EL2_TPC __BIT(23) // trap DC {IVAC,CIVAC,CVAC}
838#define HCR_EL2_TSW __BIT(22) // trap DC {ISW,CSW,CISW}
839#define HCR_EL2_TACR __BIT(21) // trap ACTRL_EL1 access
840#define HCR_EL2_TIDCP __BIT(20) // trap IMPLEMENTATION DEFINED system regs
841#define HCR_EL2_TSC __BIT(19) // trap SMC
842#define HCR_EL2_TID3 __BIT(18) // trap ID group3 regs
843#define HCR_EL2_TID2 __BIT(17) // trap ID group2 regs
844#define HCR_EL2_TID1 __BIT(16) // trap ID group1 regs
845#define HCR_EL2_TID0 __BIT(15) // trap ID group0 regs
846#define HCR_EL2_TWE __BIT(14) // trap WFE
847#define HCR_EL2_TWI __BIT(13) // trap WFI
848#define HCR_EL2_DC __BIT(12) // default cacheablility
849#define HCR_EL2_BSU __BITS(11,10) // barrier shareability upgrade
850#define HCR_EL2_FB __BIT(9) // force broadcast TLBI and IC
851#define HCR_EL2_VSE __BIT(8) // inject Virtual SError
852#define HCR_EL2_VI __BIT(7) // inject Virtual IRQ
853#define HCR_EL2_VF __BIT(6) // inject Virtual FIQ
854#define HCR_EL2_AMO __BIT(5) // trap SError/AsyncAbort
855#define HCR_EL2_IMO __BIT(4) // trap IRQ
856#define HCR_EL2_FMO __BIT(3) // trap FIQ
857#define HCR_EL2_PTW __BIT(2) // Protect table walk
858#define HCR_EL2_SWIO __BIT(1) // override DC ISW to DC CISW
859#define HCR_EL2_VM __BIT(0) // enable stage2 translation
860
861AARCH64REG_READ_INLINE(hpfar_el2) // Hypervisor IPA Fault Address Register
862AARCH64REG_WRITE_INLINE(hpfar_el2)
863
864#define HPFAR_EL2_NS __BIT(63) // Faulting IPA address space (FEAT_SEL2)
865#define HPFAR_EL2_FIPA_D128 __BITS(47,4) // Faulting Intermediate Physical Address Bits [55:12]
866#define HPFAR_EL2_FIPA __BITS(43,4) // Faulting Intermediate Physical Address Bits [51:12]
867#define HPFAR_EL2_FIPA_BITSHIFT 12
868
869
870AARCH64REG_READ_INLINE(hstr_el2) // Hypervisor System Trap Register
871AARCH64REG_WRITE_INLINE(hstr_el2)
872
873#define HSTR_EL2_T15 __BIT(15)
874// __BIT(14) Res0
875#define HSTR_EL2_T13 __BIT(13)
876#define HSTR_EL2_T12 __BIT(12)
877#define HSTR_EL2_T11 __BIT(11)
878#define HSTR_EL2_T10 __BIT(10)
879#define HSTR_EL2_T9 __BIT(9)
880#define HSTR_EL2_T8 __BIT(8)
881#define HSTR_EL2_T7 __BIT(7)
882#define HSTR_EL2_T6 __BIT(6)
883#define HSTR_EL2_T5 __BIT(5)
884// __BIT(4) Res0
885#define HSTR_EL2_T3 __BIT(3)
886#define HSTR_EL2_T2 __BIT(2)
887#define HSTR_EL2_T1 __BIT(1)
888#define HSTR_EL2_T0 __BIT(0)
889
890AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
891AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
892
893#define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores
894#define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection
895#define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection
896#define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency
897#define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency
898
899AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register
900AARCH64REG_WRITE_INLINE(mair_el1)
901AARCH64REG_READ_INLINE(mair_el2)
902AARCH64REG_WRITE_INLINE(mair_el2)
903AARCH64REG_READ_INLINE(amair_el1) // Auxiliary MAIR
904AARCH64REG_WRITE_INLINE(amair_el1)
905AARCH64REG_READ_INLINE(amair_el2)
906AARCH64REG_WRITE_INLINE(amair_el2)
907
908#define MAIR_ATTR0 __BITS(7,0)
909#define MAIR_ATTR1 __BITS(15,8)
910#define MAIR_ATTR2 __BITS(23,16)
911#define MAIR_ATTR3 __BITS(31,24)
912#define MAIR_ATTR4 __BITS(39,32)
913#define MAIR_ATTR5 __BITS(47,40)
914#define MAIR_ATTR6 __BITS(55,48)
915#define MAIR_ATTR7 __BITS(63,56)
916#define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck.
917#define MAIR_DEVICE_nGnRE 0x04 // NoGathering,NoReordering,EarlyWriteAck.
918#define MAIR_NORMAL_NC 0x44
919#define MAIR_NORMAL_WT 0xbb
920#define MAIR_NORMAL_WB 0xff
921
922AARCH64REG_READ_INLINE(par_el1) // Physical Address Register
923AARCH64REG_WRITE_INLINE(par_el1)
924
925#define PAR_ATTR __BITS(63,56) // F=0 memory attributes
926#define PAR_PA __BITS(51,12) // F=0 physical address
927#define PAR_PA_SHIFT 12
928#define PAR_PA_LOWMASK __BITS(11,0)
929#define PAR_NS __BIT(9) // F=0 non-secure
930#define PAR_SH __BITS(8,7) // F=0 shareability attribute
931#define PAR_SH_NONE 0
932#define PAR_SH_OUTER 2
933#define PAR_SH_INNER 3
934
935#define PAR_S __BIT(9) // F=1 failure stage
936#define PAR_PTW __BIT(8) // F=1 partial table walk
937#define PAR_FST __BITS(6,1) // F=1 fault status code
938#define PAR_F __BIT(0) // translation failed
939
940AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register
941AARCH64REG_WRITE_INLINE(rmr_el1)
942
943AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
944AARCH64REG_WRITE_INLINE(rvbar_el1)
945
946AARCH64REG_ATWRITE_INLINE(s1e0r) // Address Translate Stages 1 EL0
947AARCH64REG_ATWRITE_INLINE(s1e0w)
948AARCH64REG_ATWRITE_INLINE(s1e1r) // Address Translate Stages 1 EL1
949AARCH64REG_ATWRITE_INLINE(s1e1w)
950AARCH64REG_ATWRITE_INLINE(s12e0r) // Address Translate Stages 1 and 2 EL0
951AARCH64REG_ATWRITE_INLINE(s12e0w)
952AARCH64REG_ATWRITE_INLINE(s12e1r) // Address Translate Stages 1 and 2 EL1
953AARCH64REG_ATWRITE_INLINE(s12e1w)
954
955AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
956AARCH64REG_WRITE_INLINE(sctlr_el1)
957AARCH64REG_READ_INLINE(sctlr_el2)
958AARCH64REG_WRITE_INLINE(sctlr_el2)
959
960#define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
961#define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
962#define SCTLR_M __BIT(0)
963#define SCTLR_A __BIT(1)
964#define SCTLR_C __BIT(2)
965#define SCTLR_SA __BIT(3)
966#define SCTLR_SA0 __BIT(4)
967#define SCTLR_CP15BEN __BIT(5)
968#define SCTLR_nAA __BIT(6)
969#define SCTLR_ITD __BIT(7)
970#define SCTLR_SED __BIT(8)
971#define SCTLR_UMA __BIT(9)
972#define SCTLR_EnRCTX __BIT(10)
973#define SCTLR_EOS __BIT(11)
974#define SCTLR_I __BIT(12)
975#define SCTLR_EnDB __BIT(13)
976#define SCTLR_DZE __BIT(14)
977#define SCTLR_UCT __BIT(15)
978#define SCTLR_nTWI __BIT(16)
979#define SCTLR_nTWE __BIT(18)
980#define SCTLR_WXN __BIT(19)
981#define SCTLR_TSCXT __BIT(20)
982#define SCTLR_IESB __BIT(21)
983#define SCTLR_EIS __BIT(22)
984#define SCTLR_SPAN __BIT(23)
985#define SCTLR_E0E __BIT(24)
986#define SCTLR_EE __BIT(25)
987#define SCTLR_UCI __BIT(26)
988#define SCTLR_EnDA __BIT(27)
989#define SCTLR_nTLSMD __BIT(28)
990#define SCTLR_LSMAOE __BIT(29)
991#define SCTLR_EnIB __BIT(30)
992#define SCTLR_EnIA __BIT(31)
993#define SCTLR_BT0 __BIT(35)
994#define SCTLR_BT1 __BIT(36)
995#define SCTLR_ITFSB __BIT(37)
996#define SCTLR_TCF0 __BITS(39,38)
997#define SCTLR_TCF __BITS(41,40)
998#define SCTLR_ATA0 __BIT(42)
999#define SCTLR_ATA __BIT(43)
1000#define SCTLR_DSSBS __BIT(44)
1001
1002// current EL stack pointer
1003static __inline uint64_t
1004reg_sp_read(void)
1005{
1006 uint64_t __rv;
1007 __asm __volatile ("mov %0, sp" : "=r"(__rv));
1008 return __rv;
1009}
1010
1011AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer
1012AARCH64REG_WRITE_INLINE(sp_el0)
1013AARCH64REG_READ_INLINE(sp_el1) // EL1 Stack Pointer
1014AARCH64REG_WRITE_INLINE(sp_el1)
1015
1016AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select
1017AARCH64REG_WRITE_INLINE(spsel)
1018
1019#define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels
1020
1021AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register
1022AARCH64REG_WRITE_INLINE(spsr_el1)
1023
1024#define SPSR_NZCV __BITS(31,28) // mask of N Z C V
1025#define SPSR_N __BIT(31) // Negative
1026#define SPSR_Z __BIT(30) // Zero
1027#define SPSR_C __BIT(29) // Carry
1028#define SPSR_V __BIT(28) // oVerflow
1029#define SPSR_A32_Q __BIT(27) // A32: Overflow
1030#define SPSR_A32_IT1 __BIT(26) // A32: IT[1]
1031#define SPSR_A32_IT0 __BIT(25) // A32: IT[0]
1032#define SPSR_PAN __BIT(22) // Privileged Access Never
1033#define SPSR_SS __BIT(21) // Software Step
1034#define SPSR_SS_SHIFT 21
1035#define SPSR_IL __BIT(20) // Instruction Length
1036#define SPSR_GE __BITS(19,16) // A32: SIMD GE
1037#define SPSR_IT7 __BIT(15) // A32: IT[7]
1038#define SPSR_IT6 __BIT(14) // A32: IT[6]
1039#define SPSR_IT5 __BIT(13) // A32: IT[5]
1040#define SPSR_IT4 __BIT(12) // A32: IT[4]
1041#define SPSR_IT3 __BIT(11) // A32: IT[3]
1042#define SPSR_IT2 __BIT(10) // A32: IT[2]
1043#define SPSR_A64_BTYPE __BITS(11,10) // A64: BTYPE
1044#define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask
1045#define SPSR_A32_E __BIT(9) // A32: BE Endian Mode
1046#define SPSR_A __BIT(8) // Async abort (SError) Mask
1047#define SPSR_I __BIT(7) // IRQ Mask
1048#define SPSR_F __BIT(6) // FIQ Mask
1049#define SPSR_A32_T __BIT(5) // A32 Thumb Mode
1050#define SPSR_A32 __BIT(4) // A32 Mode (a part of SPSR_M)
1051#define SPSR_M __BITS(4,0) // Execution State
1052#define SPSR_M_EL3H 0x0d
1053#define SPSR_M_EL3T 0x0c
1054#define SPSR_M_EL2H 0x09
1055#define SPSR_M_EL2T 0x08
1056#define SPSR_M_EL1H 0x05
1057#define SPSR_M_EL1T 0x04
1058#define SPSR_M_EL0T 0x00
1059#define SPSR_M_SYS32 0x1f
1060#define SPSR_M_UND32 0x1b
1061#define SPSR_M_ABT32 0x17
1062#define SPSR_M_SVC32 0x13
1063#define SPSR_M_IRQ32 0x12
1064#define SPSR_M_FIQ32 0x11
1065#define SPSR_M_USR32 0x10
1066
1067#define SPSR_USER_P(spsr) (((spsr) & (SPSR_M & ~SPSR_A32)) == 0)
1068#define SPSR_PRIVILEGED_P(spsr) (!SPSR_USER_P((spsr)))
1069
1070AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
1071AARCH64REG_WRITE_INLINE(tcr_el1)
1072
1073/* TCR_EL1 - Translation Control Register */
1074#define TCR_TCMA1 __BIT(58) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b11111 */
1075#define TCR_TCMA0 __BIT(57) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b00000 */
1076#define TCR_E0PD1 __BIT(56) /* ARMv8.5-E0PD Faulting control for EL0 by TTBR1 */
1077#define TCR_E0PD0 __BIT(55) /* ARMv8.5-E0PD Faulting control for EL0 by TTBR0 */
1078#define TCR_NFD1 __BIT(54) /* SVE Non-fault translation table walk disable (TTBR1) */
1079#define TCR_NFD0 __BIT(53) /* SVE Non-fault translation table walk disable (TTBR0) */
1080#define TCR_TBID1 __BIT(52) /* ARMv8.3-PAuth TBI for instruction addr (TTBR1) */
1081#define TCR_TBID0 __BIT(51) /* ARMv8.3-PAuth TBI for instruction addr (TTBR0) */
1082#define TCR_HWU162 __BIT(50) /* ARMv8.1-TTPBHA bit[62] of PTE (TTBR1) */
1083#define TCR_HWU161 __BIT(49) /* ARMv8.1-TTPBHA bit[61] of PTE (TTBR1) */
1084#define TCR_HWU160 __BIT(48) /* ARMv8.1-TTPBHA bit[60] of PTE (TTBR1) */
1085#define TCR_HWU159 __BIT(47) /* ARMv8.1-TTPBHA bit[59] of PTE (TTBR1) */
1086#define TCR_HWU062 __BIT(46) /* ARMv8.1-TTPBHA bit[62] of PTE (TTBR0) */
1087#define TCR_HWU061 __BIT(45) /* ARMv8.1-TTPBHA bit[61] of PTE (TTBR0) */
1088#define TCR_HWU060 __BIT(44) /* ARMv8.1-TTPBHA bit[60] of PTE (TTBR0) */
1089#define TCR_HWU059 __BIT(43) /* ARMv8.1-TTPBHA bit[59] of PTE (TTBR0) */
1090#define TCR_HPD1 __BIT(42) /* ARMv8.1-HPD Hierarchical Permission (TTBR1) */
1091#define TCR_HPD0 __BIT(41) /* ARMv8.1-HPD Hierarchical Permission (TTBR0) */
1092#define TCR_HD __BIT(40) /* ARMv8.1-TTHM Hardware Dirty flag */
1093#define TCR_HA __BIT(39) /* ARMv8.1-TTHM Hardware Access flag */
1094#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
1095#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
1096#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
1097#define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */
1098#define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */
1099#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */
1100#define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */
1101#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */
1102#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */
1103#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */
1104#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */
1105#define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */
1106#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */
1107#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */
1108#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */
1109#define TCR_SH1 __BITS(29,28)
1110#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)
1111#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)
1112#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)
1113#define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */
1114#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */
1115#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */
1116#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */
1117#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */
1118#define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */
1119#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */
1120#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */
1121#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */
1122#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */
1123#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
1124#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
1125#define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */
1126#define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */
1127#define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */
1128#define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */
1129#define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */
1130#define TCR_SH0 __BITS(13,12)
1131#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)
1132#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)
1133#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)
1134#define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */
1135#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */
1136#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */
1137#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */
1138#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */
1139#define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */
1140#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */
1141#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */
1142#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */
1143#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */
1144#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
1145#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
1146
1147AARCH64REG_READ_INLINE(tcr_el2) // Translation Control Register EL2
1148AARCH64REG_WRITE_INLINE(tcr_el2)
1149
1150/* TCR_EL2 - Translation Control Register */
1151// __BITS(63, 34) // Res0
1152#define TCR_EL2_MTX __BIT(33) // Extended memory tag checking
1153#define TCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
1154// __BIT(31) // Res1
1155#define TCR_EL2_TCMA __BIT(30) // Unchecked accesses control (FEAT_MTE2)
1156#define TCR_EL2_TBID __BIT(29) // Top Byte Instruction address matching (FEAT_PAuth)
1157#define TCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
1158#define TCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
1159#define TCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
1160#define TCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
1161#define TCR_EL2_HPD __BIT(24) // Hierarchical Permission Disables (FEAT_HPDS)
1162// __BIT(23) // Res1
1163#define TCR_EL2_HD __BIT(22) // Hardware management of dirty state (FEAT_HAFDBS)
1164#define TCR_EL2_HA __BIT(21) // Hardware Access flag update (FEAT_HAFDBS)
1165#define TCR_EL2_TBI __BIT(20) // Top Byte Ignored
1166// __BIT(19) // Res1
1167#define TCR_EL2_PS __BITS(18,16) // Physical Address Size
1168#define TCR_EL2_TG0 __BITS(15,14) // TTBR0_EL2 Granule size
1169#define TCR_EL2_TG0_4KB __SHIFTIN(0,TCR_EL2_TG0) // 4KB page size
1170#define TCR_EL2_TG0_64KB __SHIFTIN(1,TCR_EL2_TG0) // 64KB page size
1171#define TCR_EL2_TG0_16KB __SHIFTIN(2,TCR_EL2_TG0) // 16KB page size
1172#define TCR_EL2_SH0 __BITS(13,12) // TTBR0_EL2 Shareability attribute
1173#define TCR_EL2_SH0_NONE __SHIFTIN(0,TCR_EL2_SH0) // non-shareable
1174#define TCR_EL2_SH0_OUTER __SHIFTIN(2,TCR_EL2_SH0) // Outer shareable
1175#define TCR_EL2_SH0_INNER __SHIFTIN(3,TCR_EL2_SH0) // Inner shareable
1176#define TCR_EL2_ORGN0 __BITS(11,10) // TTBR0_EL2 Outer cacheability attribute
1177#define TCR_EL2_ORGN0_NC __SHIFTIN(0,TCR_EL2_ORGN0) // Non Cacheable
1178#define TCR_EL2_ORGN0_WB_WA __SHIFTIN(1,TCR_EL2_ORGN0) // WriteBack WriteAllocate
1179#define TCR_EL2_ORGN0_WT __SHIFTIN(2,TCR_EL2_ORGN0) // WriteThrough
1180#define TCR_EL2_ORGN0_WB __SHIFTIN(3,TCR_EL2_ORGN0) // WriteBack
1181#define TCR_EL2_IRGN0 __BITS(9,8) // TTBR0_EL2 Inner cacheability attribute
1182#define TCR_EL2_IRGN0_NC __SHIFTIN(0,TCR_EL2_IRGN0) // Non Cacheable
1183#define TCR_EL2_IRGN0_WB_WA __SHIFTIN(1,TCR_EL2_IRGN0) // WriteBack WriteAllocate
1184#define TCR_EL2_IRGN0_WT __SHIFTIN(2,TCR_EL2_IRGN0) // WriteThrough
1185#define TCR_EL2_IRGN0_WB __SHIFTIN(3,TCR_EL2_IRGN0) // WriteBack
1186#define TCR_EL2_T0SZ __BITS(5,0) // TTBR0_EL2 Size offset
1187
1188AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
1189AARCH64REG_WRITE_INLINE(tpidr_el1)
1190AARCH64REG_READ_INLINE(tpidr_el2) // Thread ID Register (EL2)
1191AARCH64REG_WRITE_INLINE(tpidr_el2)
1192
1193AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0)
1194
1195AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
1196AARCH64REG_WRITE_INLINE(ttbr0_el1)
1197AARCH64REG_READ_INLINE(ttbr0_el2) // Translation Table Base Register 0 EL2
1198AARCH64REG_WRITE_INLINE(ttbr0_el2)
1199
1200AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
1201AARCH64REG_WRITE_INLINE(ttbr1_el1)
1202
1203#define TTBR_ASID __BITS(63,48)
1204#define TTBR_BADDR __BITS(47,0)
1205
1206AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
1207AARCH64REG_WRITE_INLINE(vbar_el1)
1208AARCH64REG_READ_INLINE(vbar_el2)
1209AARCH64REG_WRITE_INLINE(vbar_el2)
1210
1211AARCH64REG_READ_INLINE(vpidr_el2) // Virtualization Processor ID Register
1212AARCH64REG_WRITE_INLINE(vpidr_el2)
1213AARCH64REG_READ_INLINE(vmpidr_el2) // Virtualization Multiprocessor ID Register
1214AARCH64REG_WRITE_INLINE(vmpidr_el2)
1215AARCH64REG_READ_INLINE(vtcr_el2) // Virtualization Translation Control Register
1216AARCH64REG_WRITE_INLINE(vtcr_el2)
1217
1218#define VTCR_EL2_HAFT __BIT(44) // Hardware managed Access Flag (FEAT_HAFT)
1219// __BITS(43, 42) // Res0
1220#define VTCR_EL2_TL0 __BIT(41) // TopLevel0 permission attribute control (FEAT_THE)
1221#define VTCR_EL2_GCSH __BIT(40) // Assured translations for guarded control stacks (FEAT_THE+FEAT_GCS)
1222// __BIT(39) // Res0
1223#define VTCR_EL2_D128 __BIT(38) // VMSAv9-128 (FEAT_D128)
1224#define VTCR_EL2_S2POE __BIT(37) // Enable stage 2 Permission Overlay (FEAT_S2POE)
1225#define VTCR_EL2_S2PIE __BIT(36) // Select Permission Model. (FEAT_S2PIE)
1226#define VTCR_EL2_TL1 __BIT(35) // TopLevel1 permission attribute control (FEAT_THE)
1227#define VTCR_EL2_AO __BIT(34) // AssuredOnly attribute enable (FEAT_THE)
1228#define VTCR_EL2_SL2 __BIT(33) // Stage 2 starting level (FEAT_LPA2)
1229#define VTCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
1230// __BIT(31) // Res1
1231#define VTCR_EL2_NSA __BIT(30) // Non-secure S2 translation output address space (FEAT_SEL2)
1232#define VTCR_EL2_NSW __BIT(29) // Non-secure S2 translation table address space (FEAT_SEL2)
1233#define VTCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
1234#define VTCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
1235#define VTCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
1236#define VTCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
1237// __BITS(24, 23) // Res0
1238#define VTCR_EL2_HD __BIT(22) // Hardware Dirty state management (FEAT_HAFDBS)
1239#define VTCR_EL2_HA __BIT(21) // Hardware Access flag management (FEAT_HAFDBS)
1240#define VTCR_EL2_VS __BIT(19) // VMID size (FEAT_VMID16)
1241#define VTCR_EL2_PS __BITS(18,16) // Physical address Size
1242#define VTCR_EL2_TG0 __BITS(15,14) // VTTBR_EL2 Granule size
1243#define VTCR_EL2_SH0 __BITS(13,12) // V{,S}TTBR_EL2 shareability attribute
1244#define VTCR_EL2_ORGN0 __BITS(11,10) // V{,S}TTBR_EL2 outer cacheability
1245#define VTCR_EL2_IRGN0 __BITS(9,8) // V{,S}TTBR_EL2 inner cacheability
1246#define VTCR_EL2_SL0 __BITS(7,6) // Start Level of S2 translation lookup.
1247#define VTCR_EL2_T0SZ __BITS(5,0) // VTTBR_EL2 Size offset
1248
1249
1250AARCH64REG_READ_INLINE(vttbr_el2) // Virtualization Translation Table Base Register
1251AARCH64REG_WRITE_INLINE(vttbr_el2)
1252
1253#define VTTBR_VIMD __BITS(55,48)
1254#define VTTBR_BADDR __BITS(47,0)
1255
1256/*
1257 * From here on, these are DEBUG registers
1258 */
1259AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0
1260AARCH64REG_WRITE_INLINE(dbgbcr0_el1)
1261AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1
1262AARCH64REG_WRITE_INLINE(dbgbcr1_el1)
1263AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2
1264AARCH64REG_WRITE_INLINE(dbgbcr2_el1)
1265AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3
1266AARCH64REG_WRITE_INLINE(dbgbcr3_el1)
1267AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4
1268AARCH64REG_WRITE_INLINE(dbgbcr4_el1)
1269AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5
1270AARCH64REG_WRITE_INLINE(dbgbcr5_el1)
1271AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6
1272AARCH64REG_WRITE_INLINE(dbgbcr6_el1)
1273AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7
1274AARCH64REG_WRITE_INLINE(dbgbcr7_el1)
1275AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8
1276AARCH64REG_WRITE_INLINE(dbgbcr8_el1)
1277AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9
1278AARCH64REG_WRITE_INLINE(dbgbcr9_el1)
1279AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10
1280AARCH64REG_WRITE_INLINE(dbgbcr10_el1)
1281AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11
1282AARCH64REG_WRITE_INLINE(dbgbcr11_el1)
1283AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12
1284AARCH64REG_WRITE_INLINE(dbgbcr12_el1)
1285AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13
1286AARCH64REG_WRITE_INLINE(dbgbcr13_el1)
1287AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14
1288AARCH64REG_WRITE_INLINE(dbgbcr14_el1)
1289AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15
1290AARCH64REG_WRITE_INLINE(dbgbcr15_el1)
1291
1292#define DBGBCR_BT __BITS(23,20)
1293#define DBGBCR_LBN __BITS(19,16)
1294#define DBGBCR_SSC __BITS(15,14)
1295#define DBGBCR_HMC __BIT(13)
1296#define DBGBCR_BAS __BITS(8,5)
1297#define DBGBCR_PMC __BITS(2,1)
1298#define DBGBCR_E __BIT(0)
1299
1300AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0
1301AARCH64REG_WRITE_INLINE(dbgbvr0_el1)
1302AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1
1303AARCH64REG_WRITE_INLINE(dbgbvr1_el1)
1304AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2
1305AARCH64REG_WRITE_INLINE(dbgbvr2_el1)
1306AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3
1307AARCH64REG_WRITE_INLINE(dbgbvr3_el1)
1308AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4
1309AARCH64REG_WRITE_INLINE(dbgbvr4_el1)
1310AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5
1311AARCH64REG_WRITE_INLINE(dbgbvr5_el1)
1312AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6
1313AARCH64REG_WRITE_INLINE(dbgbvr6_el1)
1314AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7
1315AARCH64REG_WRITE_INLINE(dbgbvr7_el1)
1316AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8
1317AARCH64REG_WRITE_INLINE(dbgbvr8_el1)
1318AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9
1319AARCH64REG_WRITE_INLINE(dbgbvr9_el1)
1320AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10
1321AARCH64REG_WRITE_INLINE(dbgbvr10_el1)
1322AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11
1323AARCH64REG_WRITE_INLINE(dbgbvr11_el1)
1324AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12
1325AARCH64REG_WRITE_INLINE(dbgbvr12_el1)
1326AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13
1327AARCH64REG_WRITE_INLINE(dbgbvr13_el1)
1328AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14
1329AARCH64REG_WRITE_INLINE(dbgbvr14_el1)
1330AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15
1331AARCH64REG_WRITE_INLINE(dbgbvr15_el1)
1332
1333#define DBGBVR_MASK __BITS(63,2)
1334
1335AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0
1336AARCH64REG_WRITE_INLINE(dbgwcr0_el1)
1337AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1
1338AARCH64REG_WRITE_INLINE(dbgwcr1_el1)
1339AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2
1340AARCH64REG_WRITE_INLINE(dbgwcr2_el1)
1341AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3
1342AARCH64REG_WRITE_INLINE(dbgwcr3_el1)
1343AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4
1344AARCH64REG_WRITE_INLINE(dbgwcr4_el1)
1345AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5
1346AARCH64REG_WRITE_INLINE(dbgwcr5_el1)
1347AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6
1348AARCH64REG_WRITE_INLINE(dbgwcr6_el1)
1349AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7
1350AARCH64REG_WRITE_INLINE(dbgwcr7_el1)
1351AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8
1352AARCH64REG_WRITE_INLINE(dbgwcr8_el1)
1353AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9
1354AARCH64REG_WRITE_INLINE(dbgwcr9_el1)
1355AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10
1356AARCH64REG_WRITE_INLINE(dbgwcr10_el1)
1357AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11
1358AARCH64REG_WRITE_INLINE(dbgwcr11_el1)
1359AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12
1360AARCH64REG_WRITE_INLINE(dbgwcr12_el1)
1361AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13
1362AARCH64REG_WRITE_INLINE(dbgwcr13_el1)
1363AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14
1364AARCH64REG_WRITE_INLINE(dbgwcr14_el1)
1365AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15
1366AARCH64REG_WRITE_INLINE(dbgwcr15_el1)
1367
1368#define DBGWCR_MASK __BITS(28,24)
1369#define DBGWCR_WT __BIT(20)
1370#define DBGWCR_LBN __BITS(19,16)
1371#define DBGWCR_SSC __BITS(15,14)
1372#define DBGWCR_HMC __BIT(13)
1373#define DBGWCR_BAS __BITS(12,5)
1374#define DBGWCR_LSC __BITS(4,3)
1375#define DBGWCR_PAC __BITS(2,1)
1376#define DBGWCR_E __BIT(0)
1377
1378AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0
1379AARCH64REG_WRITE_INLINE(dbgwvr0_el1)
1380AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1
1381AARCH64REG_WRITE_INLINE(dbgwvr1_el1)
1382AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2
1383AARCH64REG_WRITE_INLINE(dbgwvr2_el1)
1384AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3
1385AARCH64REG_WRITE_INLINE(dbgwvr3_el1)
1386AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4
1387AARCH64REG_WRITE_INLINE(dbgwvr4_el1)
1388AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5
1389AARCH64REG_WRITE_INLINE(dbgwvr5_el1)
1390AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6
1391AARCH64REG_WRITE_INLINE(dbgwvr6_el1)
1392AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7
1393AARCH64REG_WRITE_INLINE(dbgwvr7_el1)
1394AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8
1395AARCH64REG_WRITE_INLINE(dbgwvr8_el1)
1396AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9
1397AARCH64REG_WRITE_INLINE(dbgwvr9_el1)
1398AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10
1399AARCH64REG_WRITE_INLINE(dbgwvr10_el1)
1400AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11
1401AARCH64REG_WRITE_INLINE(dbgwvr11_el1)
1402AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12
1403AARCH64REG_WRITE_INLINE(dbgwvr12_el1)
1404AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13
1405AARCH64REG_WRITE_INLINE(dbgwvr13_el1)
1406AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14
1407AARCH64REG_WRITE_INLINE(dbgwvr14_el1)
1408AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15
1409AARCH64REG_WRITE_INLINE(dbgwvr15_el1)
1410
1411#define DBGWVR_MASK __BITS(63,2)
1412
1413
1414AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register
1415AARCH64REG_WRITE_INLINE(mdscr_el1)
1416
1417#define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull
1418#define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull
1419#define MDSCR_RXO __BIT(27) // for EDSCR.RXO
1420#define MDSCR_TXU __BIT(26) // for EDSCR.TXU
1421#define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis
1422#define MDSCR_TDA __BIT(21) // for EDSCR.TDA
1423#define MDSCR_MDE __BIT(15) // Monitor debug events
1424#define MDSCR_HDE __BIT(14) // for EDSCR.HDE
1425#define MDSCR_KDE __BIT(13) // Local debug enable
1426#define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access
1427#define MDSCR_ERR __BIT(6) // for EDSCR.ERR
1428#define MDSCR_SS __BIT(0) // Software step
1429
1430AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register
1431
1432AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register
1433
1434/*
1435 * From here on, these are PMC registers
1436 */
1437
1438AARCH64REG_READ_INLINE(pmccfiltr_el0)
1439AARCH64REG_WRITE_INLINE(pmccfiltr_el0)
1440
1441#define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1
1442#define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0
1443#define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1
1444#define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0
1445#define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2
1446#define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3
1447
1448AARCH64REG_READ_INLINE(pmccntr_el0)
1449
1450AARCH64REG_READ_INLINE(pmceid0_el0)
1451AARCH64REG_READ_INLINE(pmceid1_el0)
1452
1453AARCH64REG_WRITE_INLINE(pmcntenclr_el0)
1454AARCH64REG_WRITE_INLINE(pmcntenset_el0)
1455
1456#define PMCNTEN_C __BIT(31) // Enable the cycle counter
1457#define PMCNTEN_P __BITS(30,0) // Enable event counter bits
1458
1459AARCH64REG_READ_INLINE(pmcr_el0)
1460AARCH64REG_WRITE_INLINE(pmcr_el0)
1461
1462#define PMCR_IMP __BITS(31,24) // Implementor code
1463#define PMCR_IDCODE __BITS(23,16) // Identification code
1464#define PMCR_N __BITS(15,11) // Number of event counters
1465#define PMCR_LP __BIT(7) // Long event counter enable
1466#define PMCR_LC __BIT(6) // Long cycle counter enable
1467#define PMCR_DP __BIT(5) // Disable cycle counter when event
1468 // counting is prohibited
1469#define PMCR_X __BIT(4) // Enable export of events
1470#define PMCR_D __BIT(3) // Clock divider
1471#define PMCR_C __BIT(2) // Cycle counter reset
1472#define PMCR_P __BIT(1) // Event counter reset
1473#define PMCR_E __BIT(0) // Enable
1474
1475
1476AARCH64REG_READ_INLINE(pmevcntr1_el0)
1477AARCH64REG_WRITE_INLINE(pmevcntr1_el0)
1478
1479AARCH64REG_READ_INLINE(pmevtyper1_el0)
1480AARCH64REG_WRITE_INLINE(pmevtyper1_el0)
1481
1482#define PMEVTYPER_P __BIT(31) // Don't count events in EL1
1483#define PMEVTYPER_U __BIT(30) // Don't count events in EL0
1484#define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1
1485#define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0
1486#define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2
1487#define PMEVTYPER_M __BIT(26) // Don't count events in EL3
1488#define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same
1489 // aff1 level
1490#define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count
1491
1492AARCH64REG_WRITE_INLINE(pmintenclr_el1)
1493AARCH64REG_WRITE_INLINE(pmintenset_el1)
1494
1495#define PMINTEN_C __BIT(31) // for the cycle counter
1496#define PMINTEN_P __BITS(30,0) // for event counters (0-30)
1497
1498AARCH64REG_WRITE_INLINE(pmovsclr_el0)
1499AARCH64REG_READ_INLINE(pmovsset_el0)
1500AARCH64REG_WRITE_INLINE(pmovsset_el0)
1501
1502#define PMOVS_C __BIT(31) // for the cycle counter
1503#define PMOVS_P __BITS(30,0) // for event counters (0-30)
1504
1505AARCH64REG_WRITE_INLINE(pmselr_el0)
1506
1507AARCH64REG_WRITE_INLINE(pmswinc_el0)
1508
1509AARCH64REG_READ_INLINE(pmuserenr_el0)
1510AARCH64REG_WRITE_INLINE(pmuserenr_el0)
1511
1512AARCH64REG_READ_INLINE(pmxevcntr_el0)
1513AARCH64REG_WRITE_INLINE(pmxevcntr_el0)
1514
1515AARCH64REG_READ_INLINE(pmxevtyper_el0)
1516AARCH64REG_WRITE_INLINE(pmxevtyper_el0)
1517
1518/*
1519 * Generic timer registers
1520 */
1521
1522AARCH64REG_READ_INLINE(cntfrq_el0)
1523
1524AARCH64REG_READ_INLINE(cnthctl_el2)
1525AARCH64REG_WRITE_INLINE(cnthctl_el2)
1526
1527#define CNTHCTL_EVNTDIR __BIT(3)
1528#define CNTHCTL_EVNTEN __BIT(2)
1529#define CNTHCTL_EL1PCEN __BIT(1)
1530#define CNTHCTL_EL1PCTEN __BIT(0)
1531
1532AARCH64REG_READ_INLINE(cntkctl_el1)
1533AARCH64REG_WRITE_INLINE(cntkctl_el1)
1534
1535#define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL
1536#define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN
1537#define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL
1538#define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN
1539#define CNTKCTL_ELNTI __BITS(7,4)
1540#define CNTKCTL_EVNTDIR __BIT(3)
1541#define CNTKCTL_EVNTEN __BIT(2)
1542#define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ
1543#define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN
1544#define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ
1545#define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN
1546
1547AARCH64REG_READ_INLINE(cntp_ctl_el0)
1548AARCH64REG_WRITE_INLINE(cntp_ctl_el0)
1549AARCH64REG_READ_INLINE(cntp_cval_el0)
1550AARCH64REG_WRITE_INLINE(cntp_cval_el0)
1551AARCH64REG_READ_INLINE(cntp_tval_el0)
1552AARCH64REG_WRITE_INLINE(cntp_tval_el0)
1553AARCH64REG_READ_INLINE(cntpct_el0)
1554AARCH64REG_WRITE_INLINE(cntpct_el0)
1555
1556AARCH64REG_READ_INLINE(cntps_ctl_el1)
1557AARCH64REG_WRITE_INLINE(cntps_ctl_el1)
1558AARCH64REG_READ_INLINE(cntps_cval_el1)
1559AARCH64REG_WRITE_INLINE(cntps_cval_el1)
1560AARCH64REG_READ_INLINE(cntps_tval_el1)
1561AARCH64REG_WRITE_INLINE(cntps_tval_el1)
1562
1563AARCH64REG_READ_INLINE(cntv_ctl_el0)
1564AARCH64REG_WRITE_INLINE(cntv_ctl_el0)
1565AARCH64REG_READ_INLINE(cntv_cval_el0)
1566AARCH64REG_WRITE_INLINE(cntv_cval_el0)
1567AARCH64REG_READ_INLINE(cntv_tval_el0)
1568AARCH64REG_WRITE_INLINE(cntv_tval_el0)
1569AARCH64REG_READ_INLINE(cntvct_el0)
1570AARCH64REG_WRITE_INLINE(cntvct_el0)
1571
1572#define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted
1573#define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
1574#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
1575
1576// ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
1577#define ID_AA64PFR0_EL1_CSV3 __BITS(63,60) // Speculative fault data
1578#define ID_AA64PFR0_EL1_CSV3_NONE 0
1579#define ID_AA64PFR0_EL1_CSV3_IMPL 1
1580#define ID_AA64PFR0_EL1_CSV2 __BITS(59,56) // Speculative branches
1581#define ID_AA64PFR0_EL1_CSV2_NONE 0
1582#define ID_AA64PFR0_EL1_CSV2_IMPL 1
1583// reserved [55:52]
1584#define ID_AA64PFR0_EL1_DIT __BITS(51,48) // Data-indep. timing
1585#define ID_AA64PFR0_EL1_DIT_NONE 0
1586#define ID_AA64PFR0_EL1_DIT_IMPL 1
1587#define ID_AA64PFR0_EL1_AMU __BITS(47,44) // Activity monitors ext.
1588#define ID_AA64PFR0_EL1_AMU_NONE 0
1589#define ID_AA64PFR0_EL1_AMU_IMPLv8_4 1
1590#define ID_AA64PFR0_EL1_AMU_IMPLv8_6 2
1591#define ID_AA64PFR0_EL1_MPAM __BITS(43,40) // MPAM Extension
1592#define ID_AA64PFR0_EL1_MPAM_NONE 0
1593#define ID_AA64PFR0_EL1_MPAM_IMPL 1
1594#define ID_AA64PFR0_EL1_SEL2 __BITS(43,40) // Secure EL2
1595#define ID_AA64PFR0_EL1_SEL2_NONE 0
1596#define ID_AA64PFR0_EL1_SEL2_IMPL 1
1597#define ID_AA64PFR0_EL1_SVE __BITS(35,32) // Scalable Vector
1598#define ID_AA64PFR0_EL1_SVE_NONE 0
1599#define ID_AA64PFR0_EL1_SVE_IMPL 1
1600#define ID_AA64PFR0_EL1_RAS __BITS(31,28) // RAS Extension
1601#define ID_AA64PFR0_EL1_RAS_NONE 0
1602#define ID_AA64PFR0_EL1_RAS_IMPL 1
1603#define ID_AA64PFR0_EL1_RAS_ERX 2
1604#define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF
1605#define ID_AA64PFR0_EL1_GIC_SHIFT 24
1606#define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1
1607#define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0
1608#define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD
1609#define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0
1610#define ID_AA64PFR0_EL1_ADV_SIMD_HP 0x1
1611#define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf
1612#define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP
1613#define ID_AA64PFR0_EL1_FP_IMPL 0x0
1614#define ID_AA64PFR0_EL1_FP_HP 0x1
1615#define ID_AA64PFR0_EL1_FP_NONE 0xf
1616#define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling
1617#define ID_AA64PFR0_EL1_EL3_NONE 0
1618#define ID_AA64PFR0_EL1_EL3_64 1
1619#define ID_AA64PFR0_EL1_EL3_64_32 2
1620#define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling
1621#define ID_AA64PFR0_EL1_EL2_NONE 0
1622#define ID_AA64PFR0_EL1_EL2_64 1
1623#define ID_AA64PFR0_EL1_EL2_64_32 2
1624#define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling
1625#define ID_AA64PFR0_EL1_EL1_64 1
1626#define ID_AA64PFR0_EL1_EL1_64_32 2
1627#define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling
1628#define ID_AA64PFR0_EL1_EL0_64 1
1629#define ID_AA64PFR0_EL1_EL0_64_32 2
1630
1631/*
1632 * GICv3 system registers
1633 */
1634AARCH64REG_READWRITE_INLINE2(icc_sre_el1, s3_0_c12_c12_5)
1635AARCH64REG_READWRITE_INLINE2(icc_ctlr_el1, s3_0_c12_c12_4)
1636AARCH64REG_READWRITE_INLINE2(icc_pmr_el1, s3_0_c4_c6_0)
1637AARCH64REG_READWRITE_INLINE2(icc_bpr0_el1, s3_0_c12_c8_3)
1638AARCH64REG_READWRITE_INLINE2(icc_bpr1_el1, s3_0_c12_c12_3)
1639AARCH64REG_READWRITE_INLINE2(icc_igrpen0_el1, s3_0_c12_c12_6)
1640AARCH64REG_READWRITE_INLINE2(icc_igrpen1_el1, s3_0_c12_c12_7)
1641AARCH64REG_READWRITE_INLINE2(icc_eoir0_el1, s3_0_c12_c8_1)
1642AARCH64REG_READWRITE_INLINE2(icc_eoir1_el1, s3_0_c12_c12_1)
1643AARCH64REG_READWRITE_INLINE2(icc_sgi1r_el1, s3_0_c12_c11_5)
1644AARCH64REG_READ_INLINE2(icc_iar1_el1, s3_0_c12_c12_0)
1645
1646// ICC_SRE_EL1: Interrupt Controller System Register Enable register
1647#define ICC_SRE_EL1_DIB __BIT(2)
1648#define ICC_SRE_EL1_DFB __BIT(1)
1649#define ICC_SRE_EL1_SRE __BIT(0)
1650
1651// ICC_SRE_EL2: Interrupt Controller System Register Enable register
1652#define ICC_SRE_EL2_EN __BIT(3)
1653#define ICC_SRE_EL2_DIB __BIT(2)
1654#define ICC_SRE_EL2_DFB __BIT(1)
1655#define ICC_SRE_EL2_SRE __BIT(0)
1656
1657// ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1
1658#define ICC_BPR_EL1_BinaryPoint __BITS(2,0)
1659
1660// ICC_CTLR_EL1: Interrupt Controller Control Register
1661#define ICC_CTLR_EL1_A3V __BIT(15)
1662#define ICC_CTLR_EL1_SEIS __BIT(14)
1663#define ICC_CTLR_EL1_IDbits __BITS(13,11)
1664#define ICC_CTLR_EL1_PRIbits __BITS(10,8)
1665#define ICC_CTLR_EL1_PMHE __BIT(6)
1666#define ICC_CTLR_EL1_EOImode __BIT(1)
1667#define ICC_CTLR_EL1_CBPR __BIT(0)
1668
1669// ICC_IGRPEN[01]_EL1: Interrupt Controller Interrupt Group 0/1 Enable register
1670#define ICC_IGRPEN_EL1_Enable __BIT(0)
1671
1672// ICC_SGI[01]R_EL1: Interrupt Controller Software Generated Interrupt Group 0/1 Register
1673#define ICC_SGIR_EL1_Aff3 __BITS(55,48)
1674#define ICC_SGIR_EL1_IRM __BIT(40)
1675#define ICC_SGIR_EL1_Aff2 __BITS(39,32)
1676#define ICC_SGIR_EL1_INTID __BITS(27,24)
1677#define ICC_SGIR_EL1_Aff1 __BITS(23,16)
1678#define ICC_SGIR_EL1_TargetList __BITS(15,0)
1679#define ICC_SGIR_EL1_Aff (ICC_SGIR_EL1_Aff3|ICC_SGIR_EL1_Aff2|ICC_SGIR_EL1_Aff1)
1680
1681// ICC_IAR[01]_EL1: Interrupt Controller Interrupt Acknowledge Register 0/1
1682#define ICC_IAR_INTID __BITS(23,0)
1683#define ICC_IAR_INTID_SPURIOUS 1023
1684
1685/*
1686 * GICv3 REGISTER ACCESS
1687 */
1688
1689#define icc_sre_read reg_icc_sre_el1_read
1690#define icc_sre_write reg_icc_sre_el1_write
1691#define icc_pmr_read reg_icc_pmr_el1_read
1692#define icc_pmr_write reg_icc_pmr_el1_write
1693#define icc_bpr0_write reg_icc_bpr0_el1_write
1694#define icc_bpr1_write reg_icc_bpr1_el1_write
1695#define icc_ctlr_read reg_icc_ctlr_el1_read
1696#define icc_ctlr_write reg_icc_ctlr_el1_write
1697#define icc_igrpen1_write reg_icc_igrpen1_el1_write
1698#define icc_sgi1r_write reg_icc_sgi1r_el1_write
1699#define icc_iar1_read reg_icc_iar1_el1_read
1700#define icc_eoi1r_write reg_icc_eoir1_el1_write
1701
1702#if defined(_KERNEL)
1703
1704/*
1705 * CPU REGISTER ACCESS
1706 */
1707static __inline register_t
1708cpu_mpidr_aff_read(void)
1709{
1710
1711 return reg_mpidr_el1_read() &
1712 (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0);
1713}
1714
1715/*
1716 * GENERIC TIMER REGISTER ACCESS
1717 */
1718static __inline uint32_t
1719gtmr_cntfrq_read(void)
1720{
1721
1722 return reg_cntfrq_el0_read();
1723}
1724
1725static __inline uint32_t
1726gtmr_cntk_ctl_read(void)
1727{
1728
1729 return reg_cntkctl_el1_read();
1730}
1731
1732static __inline void
1733gtmr_cntk_ctl_write(uint32_t val)
1734{
1735
1736 reg_cntkctl_el1_write(val);
1737}
1738
1739/*
1740 * Counter-timer Virtual Count timer
1741 */
1742static __inline uint64_t
1743gtmr_cntpct_read(void)
1744{
1745
1746 return reg_cntpct_el0_read();
1747}
1748
1749static __inline uint64_t
1750gtmr_cntvct_read(void)
1751{
1752
1753 return reg_cntvct_el0_read();
1754}
1755
1756/*
1757 * Counter-timer Virtual Timer Control register
1758 */
1759static __inline uint64_t
1760gtmr_cntv_ctl_read(void)
1761{
1762
1763 return reg_cntv_ctl_el0_read();
1764}
1765
1766static __inline void
1767gtmr_cntv_ctl_write(uint64_t val)
1768{
1769
1770 reg_cntv_ctl_el0_write(val);
1771}
1772
1773/*
1774 * Counter-timer Physical Timer Control register
1775 */
1776static __inline uint32_t
1777gtmr_cntp_ctl_read(void)
1778{
1779
1780 return reg_cntp_ctl_el0_read();
1781}
1782
1783static __inline void
1784gtmr_cntp_ctl_write(uint32_t val)
1785{
1786
1787 reg_cntp_ctl_el0_write(val);
1788}
1789
1790/*
1791 * Counter-timer Physical Timer TimerValue register
1792 */
1793static __inline uint32_t
1794gtmr_cntp_tval_read(void)
1795{
1796
1797 return reg_cntp_tval_el0_read();
1798}
1799
1800static __inline void
1801gtmr_cntp_tval_write(uint32_t val)
1802{
1803
1804 reg_cntp_tval_el0_write(val);
1805}
1806
1807/*
1808 * Counter-timer Virtual Timer TimerValue register
1809 */
1810static __inline uint32_t
1811gtmr_cntv_tval_read(void)
1812{
1813
1814 return reg_cntv_tval_el0_read();
1815}
1816
1817static __inline void
1818gtmr_cntv_tval_write(uint32_t val)
1819{
1820
1821 reg_cntv_tval_el0_write(val);
1822}
1823
1824/*
1825 * Counter-timer Physical Timer CompareValue register
1826 */
1827static __inline uint64_t
1828gtmr_cntp_cval_read(void)
1829{
1830
1831 return reg_cntp_cval_el0_read();
1832}
1833
1834static __inline void
1835gtmr_cntp_cval_write(uint64_t val)
1836{
1837
1838 reg_cntp_cval_el0_write(val);
1839}
1840
1841/*
1842 * Counter-timer Virtual Timer CompareValue register
1843 */
1844static __inline uint64_t
1845gtmr_cntv_cval_read(void)
1846{
1847
1848 return reg_cntv_cval_el0_read();
1849}
1850
1851static __inline void
1852gtmr_cntv_cval_write(uint64_t val)
1853{
1854
1855 reg_cntv_cval_el0_write(val);
1856}
1857#endif /* _KERNEL */
1858
1859/*
1860 * Structure attached to machdep.cpuN.cpu_id sysctl node.
1861 * Always add new members to the end, and avoid arrays.
1862 */
1863struct aarch64_sysctl_cpu_id {
1864 uint64_t ac_midr; /* Main ID Register */
1865 uint64_t ac_revidr; /* Revision ID Register */
1866 uint64_t ac_mpidr; /* Multiprocessor Affinity Register */
1867
1868 uint64_t ac_aa64dfr0; /* A64 Debug Feature Register 0 */
1869 uint64_t ac_aa64dfr1; /* A64 Debug Feature Register 1 */
1870
1871 uint64_t ac_aa64isar0; /* A64 Instruction Set Attribute Register 0 */
1872 uint64_t ac_aa64isar1; /* A64 Instruction Set Attribute Register 1 */
1873
1874 uint64_t ac_aa64mmfr0; /* A64 Memory Model Feature Register 0 */
1875 uint64_t ac_aa64mmfr1; /* A64 Memory Model Feature Register 1 */
1876 uint64_t ac_aa64mmfr2; /* A64 Memory Model Feature Register 2 */
1877
1878 uint64_t ac_aa64pfr0; /* A64 Processor Feature Register 0 */
1879 uint64_t ac_aa64pfr1; /* A64 Processor Feature Register 1 */
1880
1881 uint64_t ac_aa64zfr0; /* A64 SVE Feature ID Register 0 */
1882
1883 uint32_t ac_mvfr0; /* Media and VFP Feature Register 0 */
1884 uint32_t ac_mvfr1; /* Media and VFP Feature Register 1 */
1885 uint32_t ac_mvfr2; /* Media and VFP Feature Register 2 */
1886 uint32_t ac_pad;
1887
1888 uint64_t ac_clidr; /* Cache Level ID Register */
1889 uint64_t ac_ctr; /* Cache Type Register */
1890};
1891
1892#endif /* _AARCH64_ARMREG_H_ */