1/*
2 * Copyright (c) 2004-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32#ifndef _MACH_I386__STRUCTS_H_
33#define _MACH_I386__STRUCTS_H_
34
35#if defined (__i386__) || defined (__x86_64__)
36
37#include <sys/cdefs.h> /* __DARWIN_UNIX03 */
38#include <machine/types.h> /* __uint8_t */
39
40/*
41 * i386 is the structure that is exported to user threads for
42 * use in status/mutate calls. This structure should never change.
43 *
44 */
45
46#if __DARWIN_UNIX03
47#define _STRUCT_X86_THREAD_STATE32 struct __darwin_i386_thread_state
48_STRUCT_X86_THREAD_STATE32
49{
50 unsigned int __eax;
51 unsigned int __ebx;
52 unsigned int __ecx;
53 unsigned int __edx;
54 unsigned int __edi;
55 unsigned int __esi;
56 unsigned int __ebp;
57 unsigned int __esp;
58 unsigned int __ss;
59 unsigned int __eflags;
60 unsigned int __eip;
61 unsigned int __cs;
62 unsigned int __ds;
63 unsigned int __es;
64 unsigned int __fs;
65 unsigned int __gs;
66};
67#else /* !__DARWIN_UNIX03 */
68#define _STRUCT_X86_THREAD_STATE32 struct i386_thread_state
69_STRUCT_X86_THREAD_STATE32
70{
71 unsigned int eax;
72 unsigned int ebx;
73 unsigned int ecx;
74 unsigned int edx;
75 unsigned int edi;
76 unsigned int esi;
77 unsigned int ebp;
78 unsigned int esp;
79 unsigned int ss;
80 unsigned int eflags;
81 unsigned int eip;
82 unsigned int cs;
83 unsigned int ds;
84 unsigned int es;
85 unsigned int fs;
86 unsigned int gs;
87};
88#endif /* !__DARWIN_UNIX03 */
89
90/* This structure should be double-word aligned for performance */
91
92#if __DARWIN_UNIX03
93#define _STRUCT_FP_CONTROL struct __darwin_fp_control
94_STRUCT_FP_CONTROL
95{
96 unsigned short __invalid :1,
97 __denorm :1,
98 __zdiv :1,
99 __ovrfl :1,
100 __undfl :1,
101 __precis :1,
102 :2,
103 __pc :2,
104#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
105#define FP_PREC_24B 0
106#define FP_PREC_53B 2
107#define FP_PREC_64B 3
108#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
109 __rc :2,
110#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
111#define FP_RND_NEAR 0
112#define FP_RND_DOWN 1
113#define FP_RND_UP 2
114#define FP_CHOP 3
115#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
116 /*inf*/ :1,
117 :3;
118};
119typedef _STRUCT_FP_CONTROL __darwin_fp_control_t;
120#else /* !__DARWIN_UNIX03 */
121#define _STRUCT_FP_CONTROL struct fp_control
122_STRUCT_FP_CONTROL
123{
124 unsigned short invalid :1,
125 denorm :1,
126 zdiv :1,
127 ovrfl :1,
128 undfl :1,
129 precis :1,
130 :2,
131 pc :2,
132#define FP_PREC_24B 0
133#define FP_PREC_53B 2
134#define FP_PREC_64B 3
135 rc :2,
136#define FP_RND_NEAR 0
137#define FP_RND_DOWN 1
138#define FP_RND_UP 2
139#define FP_CHOP 3
140 /*inf*/ :1,
141 :3;
142};
143typedef _STRUCT_FP_CONTROL fp_control_t;
144#endif /* !__DARWIN_UNIX03 */
145
146/*
147 * Status word.
148 */
149
150#if __DARWIN_UNIX03
151#define _STRUCT_FP_STATUS struct __darwin_fp_status
152_STRUCT_FP_STATUS
153{
154 unsigned short __invalid :1,
155 __denorm :1,
156 __zdiv :1,
157 __ovrfl :1,
158 __undfl :1,
159 __precis :1,
160 __stkflt :1,
161 __errsumm :1,
162 __c0 :1,
163 __c1 :1,
164 __c2 :1,
165 __tos :3,
166 __c3 :1,
167 __busy :1;
168};
169typedef _STRUCT_FP_STATUS __darwin_fp_status_t;
170#else /* !__DARWIN_UNIX03 */
171#define _STRUCT_FP_STATUS struct fp_status
172_STRUCT_FP_STATUS
173{
174 unsigned short invalid :1,
175 denorm :1,
176 zdiv :1,
177 ovrfl :1,
178 undfl :1,
179 precis :1,
180 stkflt :1,
181 errsumm :1,
182 c0 :1,
183 c1 :1,
184 c2 :1,
185 tos :3,
186 c3 :1,
187 busy :1;
188};
189typedef _STRUCT_FP_STATUS fp_status_t;
190#endif /* !__DARWIN_UNIX03 */
191
192/* defn of 80bit x87 FPU or MMX register */
193
194#if __DARWIN_UNIX03
195#define _STRUCT_MMST_REG struct __darwin_mmst_reg
196_STRUCT_MMST_REG
197{
198 char __mmst_reg[10];
199 char __mmst_rsrv[6];
200};
201#else /* !__DARWIN_UNIX03 */
202#define _STRUCT_MMST_REG struct mmst_reg
203_STRUCT_MMST_REG
204{
205 char mmst_reg[10];
206 char mmst_rsrv[6];
207};
208#endif /* !__DARWIN_UNIX03 */
209
210
211/* defn of 128 bit XMM regs */
212
213#if __DARWIN_UNIX03
214#define _STRUCT_XMM_REG struct __darwin_xmm_reg
215_STRUCT_XMM_REG
216{
217 char __xmm_reg[16];
218};
219#else /* !__DARWIN_UNIX03 */
220#define _STRUCT_XMM_REG struct xmm_reg
221_STRUCT_XMM_REG
222{
223 char xmm_reg[16];
224};
225#endif /* !__DARWIN_UNIX03 */
226
227/* defn of 256 bit YMM regs */
228
229#if __DARWIN_UNIX03
230#define _STRUCT_YMM_REG struct __darwin_ymm_reg
231_STRUCT_YMM_REG
232{
233 char __ymm_reg[32];
234};
235#else /* !__DARWIN_UNIX03 */
236#define _STRUCT_YMM_REG struct ymm_reg
237_STRUCT_YMM_REG
238{
239 char ymm_reg[32];
240};
241#endif /* !__DARWIN_UNIX03 */
242
243/* defn of 512 bit ZMM regs */
244
245#if __DARWIN_UNIX03
246#define _STRUCT_ZMM_REG struct __darwin_zmm_reg
247_STRUCT_ZMM_REG
248{
249 char __zmm_reg[64];
250};
251#else /* !__DARWIN_UNIX03 */
252#define _STRUCT_ZMM_REG struct zmm_reg
253_STRUCT_ZMM_REG
254{
255 char zmm_reg[64];
256};
257#endif /* !__DARWIN_UNIX03 */
258
259#if __DARWIN_UNIX03
260#define _STRUCT_OPMASK_REG struct __darwin_opmask_reg
261_STRUCT_OPMASK_REG
262{
263 char __opmask_reg[8];
264};
265#else /* !__DARWIN_UNIX03 */
266#define _STRUCT_OPMASK_REG struct opmask_reg
267_STRUCT_OPMASK_REG
268{
269 char opmask_reg[8];
270};
271#endif /* !__DARWIN_UNIX03 */
272
273/*
274 * Floating point state.
275 */
276
277#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
278#define FP_STATE_BYTES 512 /* number of chars worth of data from fpu_fcw */
279#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
280
281#if __DARWIN_UNIX03
282#define _STRUCT_X86_FLOAT_STATE32 struct __darwin_i386_float_state
283_STRUCT_X86_FLOAT_STATE32
284{
285 int __fpu_reserved[2];
286 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
287 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
288 __uint8_t __fpu_ftw; /* x87 FPU tag word */
289 __uint8_t __fpu_rsrv1; /* reserved */
290 __uint16_t __fpu_fop; /* x87 FPU Opcode */
291 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
292 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
293 __uint16_t __fpu_rsrv2; /* reserved */
294 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
295 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
296 __uint16_t __fpu_rsrv3; /* reserved */
297 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
298 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
299 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
300 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
301 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
302 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
303 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
304 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
305 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
306 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
307 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
308 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
309 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
310 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
311 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
312 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
313 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
314 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
315 char __fpu_rsrv4[14*16]; /* reserved */
316 int __fpu_reserved1;
317};
318
319#define _STRUCT_X86_AVX_STATE32 struct __darwin_i386_avx_state
320_STRUCT_X86_AVX_STATE32
321{
322 int __fpu_reserved[2];
323 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
324 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
325 __uint8_t __fpu_ftw; /* x87 FPU tag word */
326 __uint8_t __fpu_rsrv1; /* reserved */
327 __uint16_t __fpu_fop; /* x87 FPU Opcode */
328 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
329 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
330 __uint16_t __fpu_rsrv2; /* reserved */
331 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
332 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
333 __uint16_t __fpu_rsrv3; /* reserved */
334 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
335 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
336 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
337 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
338 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
339 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
340 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
341 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
342 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
343 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
344 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
345 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
346 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
347 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
348 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
349 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
350 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
351 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
352 char __fpu_rsrv4[14*16]; /* reserved */
353 int __fpu_reserved1;
354 char __avx_reserved1[64];
355 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
356 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
357 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
358 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
359 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
360 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
361 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
362 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
363};
364
365#define _STRUCT_X86_AVX512_STATE32 struct __darwin_i386_avx512_state
366_STRUCT_X86_AVX512_STATE32
367{
368 int __fpu_reserved[2];
369 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
370 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
371 __uint8_t __fpu_ftw; /* x87 FPU tag word */
372 __uint8_t __fpu_rsrv1; /* reserved */
373 __uint16_t __fpu_fop; /* x87 FPU Opcode */
374 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
375 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
376 __uint16_t __fpu_rsrv2; /* reserved */
377 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
378 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
379 __uint16_t __fpu_rsrv3; /* reserved */
380 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
381 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
382 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
383 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
384 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
385 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
386 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
387 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
388 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
389 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
390 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
391 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
392 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
393 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
394 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
395 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
396 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
397 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
398 char __fpu_rsrv4[14*16]; /* reserved */
399 int __fpu_reserved1;
400 char __avx_reserved1[64];
401 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
402 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
403 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
404 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
405 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
406 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
407 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
408 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
409 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
410 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
411 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
412 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
413 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
414 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
415 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
416 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
417 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
418 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
419 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
420 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
421 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
422 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
423 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
424 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
425};
426
427#else /* !__DARWIN_UNIX03 */
428#define _STRUCT_X86_FLOAT_STATE32 struct i386_float_state
429_STRUCT_X86_FLOAT_STATE32
430{
431 int fpu_reserved[2];
432 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
433 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
434 __uint8_t fpu_ftw; /* x87 FPU tag word */
435 __uint8_t fpu_rsrv1; /* reserved */
436 __uint16_t fpu_fop; /* x87 FPU Opcode */
437 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
438 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
439 __uint16_t fpu_rsrv2; /* reserved */
440 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
441 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
442 __uint16_t fpu_rsrv3; /* reserved */
443 __uint32_t fpu_mxcsr; /* MXCSR Register state */
444 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
445 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
446 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
447 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
448 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
449 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
450 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
451 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
452 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
453 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
454 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
455 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
456 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
457 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
458 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
459 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
460 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
461 char fpu_rsrv4[14*16]; /* reserved */
462 int fpu_reserved1;
463};
464
465#define _STRUCT_X86_AVX_STATE32 struct i386_avx_state
466_STRUCT_X86_AVX_STATE32
467{
468 int fpu_reserved[2];
469 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
470 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
471 __uint8_t fpu_ftw; /* x87 FPU tag word */
472 __uint8_t fpu_rsrv1; /* reserved */
473 __uint16_t fpu_fop; /* x87 FPU Opcode */
474 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
475 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
476 __uint16_t fpu_rsrv2; /* reserved */
477 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
478 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
479 __uint16_t fpu_rsrv3; /* reserved */
480 __uint32_t fpu_mxcsr; /* MXCSR Register state */
481 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
482 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
483 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
484 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
485 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
486 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
487 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
488 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
489 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
490 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
491 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
492 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
493 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
494 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
495 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
496 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
497 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
498 char fpu_rsrv4[14*16]; /* reserved */
499 int fpu_reserved1;
500 char avx_reserved1[64];
501 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
502 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
503 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
504 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
505 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
506 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
507 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
508 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
509};
510
511#define _STRUCT_X86_AVX512_STATE32 struct i386_avx512_state
512_STRUCT_X86_AVX512_STATE32
513{
514 int fpu_reserved[2];
515 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
516 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
517 __uint8_t fpu_ftw; /* x87 FPU tag word */
518 __uint8_t fpu_rsrv1; /* reserved */
519 __uint16_t fpu_fop; /* x87 FPU Opcode */
520 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
521 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
522 __uint16_t fpu_rsrv2; /* reserved */
523 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
524 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
525 __uint16_t fpu_rsrv3; /* reserved */
526 __uint32_t fpu_mxcsr; /* MXCSR Register state */
527 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
528 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
529 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
530 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
531 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
532 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
533 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
534 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
535 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
536 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
537 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
538 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
539 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
540 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
541 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
542 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
543 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
544 char fpu_rsrv4[14*16]; /* reserved */
545 int fpu_reserved1;
546 char avx_reserved1[64];
547 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
548 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
549 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
550 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
551 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
552 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
553 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
554 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
555 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
556 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
557 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
558 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
559 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
560 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
561 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
562 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
563 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
564 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
565 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
566 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
567 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
568 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
569 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
570 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
571};
572
573#endif /* !__DARWIN_UNIX03 */
574
575#if __DARWIN_UNIX03
576#define _STRUCT_X86_EXCEPTION_STATE32 struct __darwin_i386_exception_state
577_STRUCT_X86_EXCEPTION_STATE32
578{
579 __uint16_t __trapno;
580 __uint16_t __cpu;
581 __uint32_t __err;
582 __uint32_t __faultvaddr;
583};
584#else /* !__DARWIN_UNIX03 */
585#define _STRUCT_X86_EXCEPTION_STATE32 struct i386_exception_state
586_STRUCT_X86_EXCEPTION_STATE32
587{
588 __uint16_t trapno;
589 __uint16_t cpu;
590 __uint32_t err;
591 __uint32_t faultvaddr;
592};
593#endif /* !__DARWIN_UNIX03 */
594
595#if __DARWIN_UNIX03
596#define _STRUCT_X86_DEBUG_STATE32 struct __darwin_x86_debug_state32
597_STRUCT_X86_DEBUG_STATE32
598{
599 unsigned int __dr0;
600 unsigned int __dr1;
601 unsigned int __dr2;
602 unsigned int __dr3;
603 unsigned int __dr4;
604 unsigned int __dr5;
605 unsigned int __dr6;
606 unsigned int __dr7;
607};
608
609#define _STRUCT_X86_INSTRUCTION_STATE struct __x86_instruction_state
610_STRUCT_X86_INSTRUCTION_STATE
611{
612 int __insn_stream_valid_bytes;
613 int __insn_offset;
614 int __out_of_synch; /*
615 * non-zero when the cacheline that includes the insn_offset
616 * is replaced in the insn_bytes array due to a mismatch
617 * detected when comparing it with the same cacheline in memory
618 */
619#define _X86_INSTRUCTION_STATE_MAX_INSN_BYTES (2448 - 64 - 4)
620 __uint8_t __insn_bytes[_X86_INSTRUCTION_STATE_MAX_INSN_BYTES];
621#define _X86_INSTRUCTION_STATE_CACHELINE_SIZE 64
622 __uint8_t __insn_cacheline[_X86_INSTRUCTION_STATE_CACHELINE_SIZE];
623};
624
625#define _STRUCT_LAST_BRANCH_RECORD struct __last_branch_record
626_STRUCT_LAST_BRANCH_RECORD
627{
628 __uint64_t __from_ip;
629 __uint64_t __to_ip;
630 __uint32_t __mispredict : 1,
631 __tsx_abort : 1,
632 __in_tsx : 1,
633 __cycle_count: 16,
634 __reserved : 13;
635};
636
637#define _STRUCT_LAST_BRANCH_STATE struct __last_branch_state
638_STRUCT_LAST_BRANCH_STATE
639{
640 int __lbr_count;
641 __uint32_t __lbr_supported_tsx : 1,
642 __lbr_supported_cycle_count : 1,
643 __reserved : 30;
644#define __LASTBRANCH_MAX 32
645 _STRUCT_LAST_BRANCH_RECORD __lbrs[__LASTBRANCH_MAX];
646};
647
648#else /* !__DARWIN_UNIX03 */
649
650#define _STRUCT_X86_DEBUG_STATE32 struct x86_debug_state32
651_STRUCT_X86_DEBUG_STATE32
652{
653 unsigned int dr0;
654 unsigned int dr1;
655 unsigned int dr2;
656 unsigned int dr3;
657 unsigned int dr4;
658 unsigned int dr5;
659 unsigned int dr6;
660 unsigned int dr7;
661};
662
663#define _STRUCT_X86_INSTRUCTION_STATE struct __x86_instruction_state
664_STRUCT_X86_INSTRUCTION_STATE
665{
666 int insn_stream_valid_bytes;
667 int insn_offset;
668 int out_of_synch; /*
669 * non-zero when the cacheline that includes the insn_offset
670 * is replaced in the insn_bytes array due to a mismatch
671 * detected when comparing it with the same cacheline in memory
672 */
673#define x86_INSTRUCTION_STATE_MAX_INSN_BYTES (2448 - 64 - 4)
674 __uint8_t insn_bytes[x86_INSTRUCTION_STATE_MAX_INSN_BYTES];
675#define x86_INSTRUCTION_STATE_CACHELINE_SIZE 64
676 __uint8_t insn_cacheline[x86_INSTRUCTION_STATE_CACHELINE_SIZE];
677};
678
679#define _STRUCT_LAST_BRANCH_RECORD struct __last_branch_record
680_STRUCT_LAST_BRANCH_RECORD
681{
682 __uint64_t from_ip;
683 __uint64_t to_ip;
684 __uint32_t mispredict : 1,
685 tsx_abort : 1,
686 in_tsx : 1,
687 cycle_count: 16,
688 reserved : 13;
689};
690
691#define _STRUCT_LAST_BRANCH_STATE struct __last_branch_state
692_STRUCT_LAST_BRANCH_STATE
693{
694 int lbr_count;
695 __uint32_t lbr_supported_tsx : 1,
696 lbr_supported_cycle_count : 1,
697 reserved : 30;
698#define __LASTBRANCH_MAX 32
699 _STRUCT_LAST_BRANCH_RECORD lbrs[__LASTBRANCH_MAX];
700};
701#endif /* !__DARWIN_UNIX03 */
702
703#define _STRUCT_X86_PAGEIN_STATE struct __x86_pagein_state
704_STRUCT_X86_PAGEIN_STATE
705{
706 int __pagein_error;
707};
708
709/*
710 * 64 bit versions of the above
711 */
712
713#if __DARWIN_UNIX03
714#define _STRUCT_X86_THREAD_STATE64 struct __darwin_x86_thread_state64
715_STRUCT_X86_THREAD_STATE64
716{
717 __uint64_t __rax;
718 __uint64_t __rbx;
719 __uint64_t __rcx;
720 __uint64_t __rdx;
721 __uint64_t __rdi;
722 __uint64_t __rsi;
723 __uint64_t __rbp;
724 __uint64_t __rsp;
725 __uint64_t __r8;
726 __uint64_t __r9;
727 __uint64_t __r10;
728 __uint64_t __r11;
729 __uint64_t __r12;
730 __uint64_t __r13;
731 __uint64_t __r14;
732 __uint64_t __r15;
733 __uint64_t __rip;
734 __uint64_t __rflags;
735 __uint64_t __cs;
736 __uint64_t __fs;
737 __uint64_t __gs;
738};
739#else /* !__DARWIN_UNIX03 */
740#define _STRUCT_X86_THREAD_STATE64 struct x86_thread_state64
741_STRUCT_X86_THREAD_STATE64
742{
743 __uint64_t rax;
744 __uint64_t rbx;
745 __uint64_t rcx;
746 __uint64_t rdx;
747 __uint64_t rdi;
748 __uint64_t rsi;
749 __uint64_t rbp;
750 __uint64_t rsp;
751 __uint64_t r8;
752 __uint64_t r9;
753 __uint64_t r10;
754 __uint64_t r11;
755 __uint64_t r12;
756 __uint64_t r13;
757 __uint64_t r14;
758 __uint64_t r15;
759 __uint64_t rip;
760 __uint64_t rflags;
761 __uint64_t cs;
762 __uint64_t fs;
763 __uint64_t gs;
764};
765#endif /* !__DARWIN_UNIX03 */
766
767/*
768 * 64 bit versions of the above (complete)
769 */
770
771#if __DARWIN_UNIX03
772#define _STRUCT_X86_THREAD_FULL_STATE64 struct __darwin_x86_thread_full_state64
773_STRUCT_X86_THREAD_FULL_STATE64
774{
775 _STRUCT_X86_THREAD_STATE64 __ss64;
776 __uint64_t __ds;
777 __uint64_t __es;
778 __uint64_t __ss;
779 __uint64_t __gsbase;
780};
781#else /* !__DARWIN_UNIX03 */
782#define _STRUCT_X86_THREAD_FULL_STATE64 struct x86_thread_full_state64
783_STRUCT_X86_THREAD_FULL_STATE64
784{
785 _STRUCT_X86_THREAD_STATE64 ss64;
786 __uint64_t ds;
787 __uint64_t es;
788 __uint64_t ss;
789 __uint64_t gsbase;
790};
791#endif /* !__DARWIN_UNIX03 */
792
793
794#if __DARWIN_UNIX03
795#define _STRUCT_X86_FLOAT_STATE64 struct __darwin_x86_float_state64
796_STRUCT_X86_FLOAT_STATE64
797{
798 int __fpu_reserved[2];
799 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
800 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
801 __uint8_t __fpu_ftw; /* x87 FPU tag word */
802 __uint8_t __fpu_rsrv1; /* reserved */
803 __uint16_t __fpu_fop; /* x87 FPU Opcode */
804
805 /* x87 FPU Instruction Pointer */
806 __uint32_t __fpu_ip; /* offset */
807 __uint16_t __fpu_cs; /* Selector */
808
809 __uint16_t __fpu_rsrv2; /* reserved */
810
811 /* x87 FPU Instruction Operand(Data) Pointer */
812 __uint32_t __fpu_dp; /* offset */
813 __uint16_t __fpu_ds; /* Selector */
814
815 __uint16_t __fpu_rsrv3; /* reserved */
816 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
817 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
818 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
819 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
820 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
821 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
822 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
823 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
824 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
825 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
826 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
827 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
828 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
829 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
830 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
831 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
832 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
833 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
834 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
835 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
836 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
837 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
838 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
839 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
840 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
841 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
842 char __fpu_rsrv4[6*16]; /* reserved */
843 int __fpu_reserved1;
844};
845
846#define _STRUCT_X86_AVX_STATE64 struct __darwin_x86_avx_state64
847_STRUCT_X86_AVX_STATE64
848{
849 int __fpu_reserved[2];
850 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
851 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
852 __uint8_t __fpu_ftw; /* x87 FPU tag word */
853 __uint8_t __fpu_rsrv1; /* reserved */
854 __uint16_t __fpu_fop; /* x87 FPU Opcode */
855
856 /* x87 FPU Instruction Pointer */
857 __uint32_t __fpu_ip; /* offset */
858 __uint16_t __fpu_cs; /* Selector */
859
860 __uint16_t __fpu_rsrv2; /* reserved */
861
862 /* x87 FPU Instruction Operand(Data) Pointer */
863 __uint32_t __fpu_dp; /* offset */
864 __uint16_t __fpu_ds; /* Selector */
865
866 __uint16_t __fpu_rsrv3; /* reserved */
867 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
868 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
869 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
870 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
871 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
872 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
873 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
874 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
875 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
876 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
877 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
878 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
879 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
880 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
881 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
882 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
883 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
884 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
885 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
886 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
887 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
888 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
889 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
890 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
891 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
892 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
893 char __fpu_rsrv4[6*16]; /* reserved */
894 int __fpu_reserved1;
895 char __avx_reserved1[64];
896 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
897 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
898 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
899 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
900 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
901 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
902 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
903 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
904 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
905 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
906 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
907 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
908 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
909 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
910 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
911 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
912};
913
914#define _STRUCT_X86_AVX512_STATE64 struct __darwin_x86_avx512_state64
915_STRUCT_X86_AVX512_STATE64
916{
917 int __fpu_reserved[2];
918 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
919 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
920 __uint8_t __fpu_ftw; /* x87 FPU tag word */
921 __uint8_t __fpu_rsrv1; /* reserved */
922 __uint16_t __fpu_fop; /* x87 FPU Opcode */
923
924 /* x87 FPU Instruction Pointer */
925 __uint32_t __fpu_ip; /* offset */
926 __uint16_t __fpu_cs; /* Selector */
927
928 __uint16_t __fpu_rsrv2; /* reserved */
929
930 /* x87 FPU Instruction Operand(Data) Pointer */
931 __uint32_t __fpu_dp; /* offset */
932 __uint16_t __fpu_ds; /* Selector */
933
934 __uint16_t __fpu_rsrv3; /* reserved */
935 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
936 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
937 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
938 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
939 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
940 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
941 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
942 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
943 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
944 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
945 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
946 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
947 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
948 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
949 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
950 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
951 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
952 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
953 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
954 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
955 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
956 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
957 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
958 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
959 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
960 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
961 char __fpu_rsrv4[6*16]; /* reserved */
962 int __fpu_reserved1;
963 char __avx_reserved1[64];
964 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
965 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
966 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
967 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
968 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
969 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
970 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
971 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
972 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
973 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
974 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
975 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
976 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
977 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
978 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
979 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
980 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
981 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
982 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
983 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
984 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
985 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
986 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
987 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
988 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
989 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
990 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
991 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
992 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
993 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
994 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
995 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
996 _STRUCT_YMM_REG __fpu_zmmh8; /* ZMMH 8 */
997 _STRUCT_YMM_REG __fpu_zmmh9; /* ZMMH 9 */
998 _STRUCT_YMM_REG __fpu_zmmh10; /* ZMMH 10 */
999 _STRUCT_YMM_REG __fpu_zmmh11; /* ZMMH 11 */
1000 _STRUCT_YMM_REG __fpu_zmmh12; /* ZMMH 12 */
1001 _STRUCT_YMM_REG __fpu_zmmh13; /* ZMMH 13 */
1002 _STRUCT_YMM_REG __fpu_zmmh14; /* ZMMH 14 */
1003 _STRUCT_YMM_REG __fpu_zmmh15; /* ZMMH 15 */
1004 _STRUCT_ZMM_REG __fpu_zmm16; /* ZMM 16 */
1005 _STRUCT_ZMM_REG __fpu_zmm17; /* ZMM 17 */
1006 _STRUCT_ZMM_REG __fpu_zmm18; /* ZMM 18 */
1007 _STRUCT_ZMM_REG __fpu_zmm19; /* ZMM 19 */
1008 _STRUCT_ZMM_REG __fpu_zmm20; /* ZMM 20 */
1009 _STRUCT_ZMM_REG __fpu_zmm21; /* ZMM 21 */
1010 _STRUCT_ZMM_REG __fpu_zmm22; /* ZMM 22 */
1011 _STRUCT_ZMM_REG __fpu_zmm23; /* ZMM 23 */
1012 _STRUCT_ZMM_REG __fpu_zmm24; /* ZMM 24 */
1013 _STRUCT_ZMM_REG __fpu_zmm25; /* ZMM 25 */
1014 _STRUCT_ZMM_REG __fpu_zmm26; /* ZMM 26 */
1015 _STRUCT_ZMM_REG __fpu_zmm27; /* ZMM 27 */
1016 _STRUCT_ZMM_REG __fpu_zmm28; /* ZMM 28 */
1017 _STRUCT_ZMM_REG __fpu_zmm29; /* ZMM 29 */
1018 _STRUCT_ZMM_REG __fpu_zmm30; /* ZMM 30 */
1019 _STRUCT_ZMM_REG __fpu_zmm31; /* ZMM 31 */
1020};
1021
1022#else /* !__DARWIN_UNIX03 */
1023#define _STRUCT_X86_FLOAT_STATE64 struct x86_float_state64
1024_STRUCT_X86_FLOAT_STATE64
1025{
1026 int fpu_reserved[2];
1027 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1028 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1029 __uint8_t fpu_ftw; /* x87 FPU tag word */
1030 __uint8_t fpu_rsrv1; /* reserved */
1031 __uint16_t fpu_fop; /* x87 FPU Opcode */
1032
1033 /* x87 FPU Instruction Pointer */
1034 __uint32_t fpu_ip; /* offset */
1035 __uint16_t fpu_cs; /* Selector */
1036
1037 __uint16_t fpu_rsrv2; /* reserved */
1038
1039 /* x87 FPU Instruction Operand(Data) Pointer */
1040 __uint32_t fpu_dp; /* offset */
1041 __uint16_t fpu_ds; /* Selector */
1042
1043 __uint16_t fpu_rsrv3; /* reserved */
1044 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1045 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1046 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1047 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1048 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1049 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1050 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1051 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1052 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1053 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1054 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1055 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1056 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1057 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1058 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1059 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1060 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1061 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1062 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1063 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1064 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1065 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1066 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1067 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1068 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1069 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1070 char fpu_rsrv4[6*16]; /* reserved */
1071 int fpu_reserved1;
1072};
1073
1074#define _STRUCT_X86_AVX_STATE64 struct x86_avx_state64
1075_STRUCT_X86_AVX_STATE64
1076{
1077 int fpu_reserved[2];
1078 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1079 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1080 __uint8_t fpu_ftw; /* x87 FPU tag word */
1081 __uint8_t fpu_rsrv1; /* reserved */
1082 __uint16_t fpu_fop; /* x87 FPU Opcode */
1083
1084 /* x87 FPU Instruction Pointer */
1085 __uint32_t fpu_ip; /* offset */
1086 __uint16_t fpu_cs; /* Selector */
1087
1088 __uint16_t fpu_rsrv2; /* reserved */
1089
1090 /* x87 FPU Instruction Operand(Data) Pointer */
1091 __uint32_t fpu_dp; /* offset */
1092 __uint16_t fpu_ds; /* Selector */
1093
1094 __uint16_t fpu_rsrv3; /* reserved */
1095 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1096 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1097 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1098 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1099 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1100 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1101 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1102 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1103 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1104 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1105 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1106 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1107 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1108 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1109 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1110 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1111 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1112 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1113 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1114 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1115 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1116 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1117 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1118 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1119 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1120 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1121 char fpu_rsrv4[6*16]; /* reserved */
1122 int fpu_reserved1;
1123 char avx_reserved1[64];
1124 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1125 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1126 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1127 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1128 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1129 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1130 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1131 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1132 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1133 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1134 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1135 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1136 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1137 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1138 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1139 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1140};
1141
1142#define _STRUCT_X86_AVX512_STATE64 struct x86_avx512_state64
1143_STRUCT_X86_AVX512_STATE64
1144{
1145 int fpu_reserved[2];
1146 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1147 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1148 __uint8_t fpu_ftw; /* x87 FPU tag word */
1149 __uint8_t fpu_rsrv1; /* reserved */
1150 __uint16_t fpu_fop; /* x87 FPU Opcode */
1151
1152 /* x87 FPU Instruction Pointer */
1153 __uint32_t fpu_ip; /* offset */
1154 __uint16_t fpu_cs; /* Selector */
1155
1156 __uint16_t fpu_rsrv2; /* reserved */
1157
1158 /* x87 FPU Instruction Operand(Data) Pointer */
1159 __uint32_t fpu_dp; /* offset */
1160 __uint16_t fpu_ds; /* Selector */
1161
1162 __uint16_t fpu_rsrv3; /* reserved */
1163 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1164 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1165 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1166 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1167 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1168 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1169 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1170 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1171 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1172 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1173 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1174 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1175 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1176 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1177 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1178 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1179 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1180 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1181 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1182 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1183 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1184 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1185 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1186 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1187 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1188 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1189 char fpu_rsrv4[6*16]; /* reserved */
1190 int fpu_reserved1;
1191 char avx_reserved1[64];
1192 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1193 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1194 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1195 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1196 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1197 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1198 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1199 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1200 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1201 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1202 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1203 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1204 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1205 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1206 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1207 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1208 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
1209 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
1210 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
1211 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
1212 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
1213 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
1214 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
1215 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
1216 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
1217 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
1218 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
1219 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
1220 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
1221 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
1222 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
1223 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
1224 _STRUCT_YMM_REG fpu_zmmh8; /* ZMMH 8 */
1225 _STRUCT_YMM_REG fpu_zmmh9; /* ZMMH 9 */
1226 _STRUCT_YMM_REG fpu_zmmh10; /* ZMMH 10 */
1227 _STRUCT_YMM_REG fpu_zmmh11; /* ZMMH 11 */
1228 _STRUCT_YMM_REG fpu_zmmh12; /* ZMMH 12 */
1229 _STRUCT_YMM_REG fpu_zmmh13; /* ZMMH 13 */
1230 _STRUCT_YMM_REG fpu_zmmh14; /* ZMMH 14 */
1231 _STRUCT_YMM_REG fpu_zmmh15; /* ZMMH 15 */
1232 _STRUCT_ZMM_REG fpu_zmm16; /* ZMM 16 */
1233 _STRUCT_ZMM_REG fpu_zmm17; /* ZMM 17 */
1234 _STRUCT_ZMM_REG fpu_zmm18; /* ZMM 18 */
1235 _STRUCT_ZMM_REG fpu_zmm19; /* ZMM 19 */
1236 _STRUCT_ZMM_REG fpu_zmm20; /* ZMM 20 */
1237 _STRUCT_ZMM_REG fpu_zmm21; /* ZMM 21 */
1238 _STRUCT_ZMM_REG fpu_zmm22; /* ZMM 22 */
1239 _STRUCT_ZMM_REG fpu_zmm23; /* ZMM 23 */
1240 _STRUCT_ZMM_REG fpu_zmm24; /* ZMM 24 */
1241 _STRUCT_ZMM_REG fpu_zmm25; /* ZMM 25 */
1242 _STRUCT_ZMM_REG fpu_zmm26; /* ZMM 26 */
1243 _STRUCT_ZMM_REG fpu_zmm27; /* ZMM 27 */
1244 _STRUCT_ZMM_REG fpu_zmm28; /* ZMM 28 */
1245 _STRUCT_ZMM_REG fpu_zmm29; /* ZMM 29 */
1246 _STRUCT_ZMM_REG fpu_zmm30; /* ZMM 30 */
1247 _STRUCT_ZMM_REG fpu_zmm31; /* ZMM 31 */
1248};
1249
1250#endif /* !__DARWIN_UNIX03 */
1251
1252#if __DARWIN_UNIX03
1253#define _STRUCT_X86_EXCEPTION_STATE64 struct __darwin_x86_exception_state64
1254_STRUCT_X86_EXCEPTION_STATE64
1255{
1256 __uint16_t __trapno;
1257 __uint16_t __cpu;
1258 __uint32_t __err;
1259 __uint64_t __faultvaddr;
1260};
1261#else /* !__DARWIN_UNIX03 */
1262#define _STRUCT_X86_EXCEPTION_STATE64 struct x86_exception_state64
1263_STRUCT_X86_EXCEPTION_STATE64
1264{
1265 __uint16_t trapno;
1266 __uint16_t cpu;
1267 __uint32_t err;
1268 __uint64_t faultvaddr;
1269};
1270#endif /* !__DARWIN_UNIX03 */
1271
1272#if __DARWIN_UNIX03
1273#define _STRUCT_X86_DEBUG_STATE64 struct __darwin_x86_debug_state64
1274_STRUCT_X86_DEBUG_STATE64
1275{
1276 __uint64_t __dr0;
1277 __uint64_t __dr1;
1278 __uint64_t __dr2;
1279 __uint64_t __dr3;
1280 __uint64_t __dr4;
1281 __uint64_t __dr5;
1282 __uint64_t __dr6;
1283 __uint64_t __dr7;
1284};
1285#else /* !__DARWIN_UNIX03 */
1286#define _STRUCT_X86_DEBUG_STATE64 struct x86_debug_state64
1287_STRUCT_X86_DEBUG_STATE64
1288{
1289 __uint64_t dr0;
1290 __uint64_t dr1;
1291 __uint64_t dr2;
1292 __uint64_t dr3;
1293 __uint64_t dr4;
1294 __uint64_t dr5;
1295 __uint64_t dr6;
1296 __uint64_t dr7;
1297};
1298#endif /* !__DARWIN_UNIX03 */
1299
1300#if __DARWIN_UNIX03
1301#define _STRUCT_X86_CPMU_STATE64 struct __darwin_x86_cpmu_state64
1302_STRUCT_X86_CPMU_STATE64
1303{
1304 __uint64_t __ctrs[16];
1305};
1306#else /* __DARWIN_UNIX03 */
1307#define _STRUCT_X86_CPMU_STATE64 struct x86_cpmu_state64
1308_STRUCT_X86_CPMU_STATE64
1309{
1310 __uint64_t ctrs[16];
1311};
1312#endif /* !__DARWIN_UNIX03 */
1313
1314#endif /* defined (__i386__) || defined (__x86_64__) */
1315
1316#endif /* _MACH_I386__STRUCTS_H_ */