1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#ifndef __MSM_DRM_H__
26#define __MSM_DRM_H__
27
28#include "drm.h"
29
30#if defined(__cplusplus)
31extern "C" {
32#endif
33
34/* Please note that modifications to all structs defined here are
35 * subject to backwards-compatibility constraints:
36 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
37 * user/kernel compatibility
38 * 2) Keep fields aligned to their size
39 * 3) Because of how drm_ioctl() works, we can add new fields at
40 * the end of an ioctl if some care is taken: drm_ioctl() will
41 * zero out the new fields at the tail of the ioctl, so a zero
42 * value should have a backwards compatible meaning. And for
43 * output params, userspace won't see the newly added output
44 * fields.. so that has to be somehow ok.
45 */
46
47#define MSM_PIPE_NONE 0x00
48#define MSM_PIPE_2D0 0x01
49#define MSM_PIPE_2D1 0x02
50#define MSM_PIPE_3D0 0x10
51
52/* The pipe-id just uses the lower bits, so can be OR'd with flags in
53 * the upper 16 bits (which could be extended further, if needed, maybe
54 * we extend/overload the pipe-id some day to deal with multiple rings,
55 * but even then I don't think we need the full lower 16 bits).
56 */
57#define MSM_PIPE_ID_MASK 0xffff
58#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
59#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
60
61/* timeouts are specified in clock-monotonic absolute times (to simplify
62 * restarting interrupted ioctls). The following struct is logically the
63 * same as 'struct timespec' but 32/64b ABI safe.
64 */
65struct drm_msm_timespec {
66 __s64 tv_sec; /* seconds */
67 __s64 tv_nsec; /* nanoseconds */
68};
69
70/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
71 * "RW" indicates a param that can be both read (GET_PARAM) and written
72 * (SET_PARAM)
73 */
74#define MSM_PARAM_GPU_ID 0x01 /* RO */
75#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
76#define MSM_PARAM_CHIP_ID 0x03 /* RO */
77#define MSM_PARAM_MAX_FREQ 0x04 /* RO */
78#define MSM_PARAM_TIMESTAMP 0x05 /* RO */
79#define MSM_PARAM_GMEM_BASE 0x06 /* RO */
80#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
81#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
82#define MSM_PARAM_FAULTS 0x09 /* RO */
83#define MSM_PARAM_SUSPENDS 0x0a /* RO */
84#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
85#define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */
86#define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */
87#define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */
88#define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */
89#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
90#define MSM_PARAM_RAYTRACING 0x11 /* RO */
91#define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */
92#define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */
93#define MSM_PARAM_UCHE_TRAP_BASE 0x14 /* RO */
94/* PRR (Partially Resident Region) is required for sparse residency: */
95#define MSM_PARAM_HAS_PRR 0x15 /* RO */
96/* MSM_PARAM_EN_VM_BIND is set to 1 to enable VM_BIND ops.
97 *
98 * With VM_BIND enabled, userspace is required to allocate iova and use the
99 * VM_BIND ops for map/unmap ioctls. MSM_INFO_SET_IOVA and MSM_INFO_GET_IOVA
100 * will be rejected. (The latter does not have a sensible meaning when a BO
101 * can have multiple and/or partial mappings.)
102 *
103 * With VM_BIND enabled, userspace does not include a submit_bo table in the
104 * SUBMIT ioctl (this will be rejected), the resident set is determined by
105 * the the VM_BIND ops.
106 *
107 * Enabling VM_BIND will fail on devices which do not have per-process pgtables.
108 * And it is not allowed to disable VM_BIND once it has been enabled.
109 *
110 * Enabling VM_BIND should be done (attempted) prior to allocating any BOs or
111 * submitqueues of type MSM_SUBMITQUEUE_VM_BIND.
112 *
113 * Relatedly, when VM_BIND mode is enabled, the kernel will not try to recover
114 * from GPU faults or failed async VM_BIND ops, in particular because it is
115 * difficult to communicate to userspace which op failed so that userspace
116 * could rewind and try again. When the VM is marked unusable, the SUBMIT
117 * ioctl will throw -EPIPE.
118 */
119#define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */
120#define MSM_PARAM_AQE 0x17 /* RO */
121
122/* For backwards compat. The original support for preemption was based on
123 * a single ring per priority level so # of priority levels equals the #
124 * of rings. With drm/scheduler providing additional levels of priority,
125 * the number of priorities is greater than the # of rings. The param is
126 * renamed to better reflect this.
127 */
128#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
129
130struct drm_msm_param {
131 __u32 pipe; /* in, MSM_PIPE_x */
132 __u32 param; /* in, MSM_PARAM_x */
133 __u64 value; /* out (get_param) or in (set_param) */
134 __u32 len; /* zero for non-pointer params */
135 __u32 pad; /* must be zero */
136};
137
138/*
139 * GEM buffers:
140 */
141
142#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
143#define MSM_BO_GPU_READONLY 0x00000002
144/* Private buffers do not need to be explicitly listed in the SUBMIT
145 * ioctl, unless referenced by a drm_msm_gem_submit_cmd. Private
146 * buffers may NOT be imported/exported or used for scanout (or any
147 * other situation where buffers can be indefinitely pinned, but
148 * cases other than scanout are all kernel owned BOs which are not
149 * visible to userspace).
150 *
151 * In exchange for those constraints, all private BOs associated with
152 * a single context (drm_file) share a single dma_resv, and if there
153 * has been no eviction since the last submit, there are no per-BO
154 * bookeeping to do, significantly cutting the SUBMIT overhead.
155 */
156#define MSM_BO_NO_SHARE 0x00000004
157#define MSM_BO_CACHE_MASK 0x000f0000
158/* cache modes */
159#define MSM_BO_CACHED 0x00010000
160#define MSM_BO_WC 0x00020000
161#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
162#define MSM_BO_CACHED_COHERENT 0x080000
163
164#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
165 MSM_BO_GPU_READONLY | \
166 MSM_BO_NO_SHARE | \
167 MSM_BO_CACHE_MASK)
168
169struct drm_msm_gem_new {
170 __u64 size; /* in */
171 __u32 flags; /* in, mask of MSM_BO_x */
172 __u32 handle; /* out */
173};
174
175/* Get or set GEM buffer info. The requested value can be passed
176 * directly in 'value', or for data larger than 64b 'value' is a
177 * pointer to userspace buffer, with 'len' specifying the number of
178 * bytes copied into that buffer. For info returned by pointer,
179 * calling the GEM_INFO ioctl with null 'value' will return the
180 * required buffer size in 'len'
181 */
182#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
183#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
184#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
185#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
186#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
187#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
188#define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */
189#define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */
190
191struct drm_msm_gem_info {
192 __u32 handle; /* in */
193 __u32 info; /* in - one of MSM_INFO_* */
194 __u64 value; /* in or out */
195 __u32 len; /* in or out */
196 __u32 pad;
197};
198
199#define MSM_PREP_READ 0x01
200#define MSM_PREP_WRITE 0x02
201#define MSM_PREP_NOSYNC 0x04
202#define MSM_PREP_BOOST 0x08
203
204#define MSM_PREP_FLAGS (MSM_PREP_READ | \
205 MSM_PREP_WRITE | \
206 MSM_PREP_NOSYNC | \
207 MSM_PREP_BOOST | \
208 0)
209
210struct drm_msm_gem_cpu_prep {
211 __u32 handle; /* in */
212 __u32 op; /* in, mask of MSM_PREP_x */
213 struct drm_msm_timespec timeout; /* in */
214};
215
216struct drm_msm_gem_cpu_fini {
217 __u32 handle; /* in */
218};
219
220/*
221 * Cmdstream Submission:
222 */
223
224#define MSM_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
225#define MSM_SYNCOBJ_FLAGS ( \
226 MSM_SYNCOBJ_RESET | \
227 0)
228
229struct drm_msm_syncobj {
230 __u32 handle; /* in, syncobj handle. */
231 __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
232 __u64 point; /* in, timepoint for timeline syncobjs. */
233};
234
235/* The value written into the cmdstream is logically:
236 *
237 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
238 *
239 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
240 * with this by emit'ing two reloc entries with appropriate shift
241 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
242 *
243 * NOTE that reloc's must be sorted by order of increasing submit_offset,
244 * otherwise EINVAL.
245 */
246struct drm_msm_gem_submit_reloc {
247 __u32 submit_offset; /* in, offset from submit_bo */
248#ifdef __cplusplus
249 __u32 _or; /* in, value OR'd with result */
250#else
251 __u32 or; /* in, value OR'd with result */
252#endif
253 __s32 shift; /* in, amount of left shift (can be negative) */
254 __u32 reloc_idx; /* in, index of reloc_bo buffer */
255 __u64 reloc_offset; /* in, offset from start of reloc_bo */
256};
257
258/* submit-types:
259 * BUF - this cmd buffer is executed normally.
260 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
261 * processed normally, but the kernel does not setup an IB to
262 * this buffer in the first-level ringbuffer
263 * CTX_RESTORE_BUF - only executed if there has been a GPU context
264 * switch since the last SUBMIT ioctl
265 */
266#define MSM_SUBMIT_CMD_BUF 0x0001
267#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
268#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
269struct drm_msm_gem_submit_cmd {
270 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
271 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
272 __u32 submit_offset; /* in, offset into submit_bo */
273 __u32 size; /* in, cmdstream size */
274 __u32 pad;
275 __u32 nr_relocs; /* in, number of submit_reloc's */
276 union {
277 __u64 relocs; /* in, ptr to array of submit_reloc's */
278 __u64 iova; /* cmdstream address (for VM_BIND contexts) */
279 };
280};
281
282/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
283 * cmdstream buffer(s) themselves or reloc entries) has one (and only
284 * one) entry in the submit->bos[] table.
285 *
286 * As a optimization, the current buffer (gpu virtual address) can be
287 * passed back through the 'presumed' field. If on a subsequent reloc,
288 * userspace passes back a 'presumed' address that is still valid,
289 * then patching the cmdstream for this entry is skipped. This can
290 * avoid kernel needing to map/access the cmdstream bo in the common
291 * case.
292 */
293#define MSM_SUBMIT_BO_READ 0x0001
294#define MSM_SUBMIT_BO_WRITE 0x0002
295#define MSM_SUBMIT_BO_DUMP 0x0004
296#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
297
298#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
299 MSM_SUBMIT_BO_WRITE | \
300 MSM_SUBMIT_BO_DUMP | \
301 MSM_SUBMIT_BO_NO_IMPLICIT)
302
303struct drm_msm_gem_submit_bo {
304 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
305 __u32 handle; /* in, GEM handle */
306 __u64 presumed; /* in/out, presumed buffer address */
307};
308
309/* Valid submit ioctl flags: */
310#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
311#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
312#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
313#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
314#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
315#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
316#define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */
317#define MSM_SUBMIT_FLAGS ( \
318 MSM_SUBMIT_NO_IMPLICIT | \
319 MSM_SUBMIT_FENCE_FD_IN | \
320 MSM_SUBMIT_FENCE_FD_OUT | \
321 MSM_SUBMIT_SUDO | \
322 MSM_SUBMIT_SYNCOBJ_IN | \
323 MSM_SUBMIT_SYNCOBJ_OUT | \
324 MSM_SUBMIT_FENCE_SN_IN | \
325 0)
326
327/* Each cmdstream submit consists of a table of buffers involved, and
328 * one or more cmdstream buffers. This allows for conditional execution
329 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
330 */
331struct drm_msm_gem_submit {
332 __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
333 __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
334 __u32 nr_bos; /* in, number of submit_bo's */
335 __u32 nr_cmds; /* in, number of submit_cmd's */
336 __u64 bos; /* in, ptr to array of submit_bo's */
337 __u64 cmds; /* in, ptr to array of submit_cmd's */
338 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
339 __u32 queueid; /* in, submitqueue id */
340 __u64 in_syncobjs; /* in, ptr to array of drm_msm_syncobj */
341 __u64 out_syncobjs; /* in, ptr to array of drm_msm_syncobj */
342 __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
343 __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
344 __u32 syncobj_stride; /* in, stride of syncobj arrays. */
345 __u32 pad; /*in, reserved for future use, always 0. */
346};
347
348#define MSM_VM_BIND_OP_UNMAP 0
349#define MSM_VM_BIND_OP_MAP 1
350#define MSM_VM_BIND_OP_MAP_NULL 2
351
352#define MSM_VM_BIND_OP_DUMP 1
353#define MSM_VM_BIND_OP_FLAGS ( \
354 MSM_VM_BIND_OP_DUMP | \
355 0)
356
357/**
358 * struct drm_msm_vm_bind_op - bind/unbind op to run
359 */
360struct drm_msm_vm_bind_op {
361 /** @op: one of MSM_VM_BIND_OP_x */
362 __u32 op;
363 /** @handle: GEM object handle, MBZ for UNMAP or MAP_NULL */
364 __u32 handle;
365 /** @obj_offset: Offset into GEM object, MBZ for UNMAP or MAP_NULL */
366 __u64 obj_offset;
367 /** @iova: Address to operate on */
368 __u64 iova;
369 /** @range: Number of bites to to map/unmap */
370 __u64 range;
371 /** @flags: Bitmask of MSM_VM_BIND_OP_FLAG_x */
372 __u32 flags;
373 /** @pad: MBZ */
374 __u32 pad;
375};
376
377#define MSM_VM_BIND_FENCE_FD_IN 0x00000001
378#define MSM_VM_BIND_FENCE_FD_OUT 0x00000002
379#define MSM_VM_BIND_FLAGS ( \
380 MSM_VM_BIND_FENCE_FD_IN | \
381 MSM_VM_BIND_FENCE_FD_OUT | \
382 0)
383
384/**
385 * struct drm_msm_vm_bind - Input of &DRM_IOCTL_MSM_VM_BIND
386 */
387struct drm_msm_vm_bind {
388 /** @flags: in, bitmask of MSM_VM_BIND_x */
389 __u32 flags;
390 /** @nr_ops: the number of bind ops in this ioctl */
391 __u32 nr_ops;
392 /** @fence_fd: in/out fence fd (see MSM_VM_BIND_FENCE_FD_IN/OUT) */
393 __s32 fence_fd;
394 /** @queue_id: in, submitqueue id */
395 __u32 queue_id;
396 /** @in_syncobjs: in, ptr to array of drm_msm_gem_syncobj */
397 __u64 in_syncobjs;
398 /** @out_syncobjs: in, ptr to array of drm_msm_gem_syncobj */
399 __u64 out_syncobjs;
400 /** @nr_in_syncobjs: in, number of entries in in_syncobj */
401 __u32 nr_in_syncobjs;
402 /** @nr_out_syncobjs: in, number of entries in out_syncobj */
403 __u32 nr_out_syncobjs;
404 /** @syncobj_stride: in, stride of syncobj arrays */
405 __u32 syncobj_stride;
406 /** @op_stride: sizeof each struct drm_msm_vm_bind_op in @ops */
407 __u32 op_stride;
408 union {
409 /** @op: used if num_ops == 1 */
410 struct drm_msm_vm_bind_op op;
411 /** @ops: userptr to array of drm_msm_vm_bind_op if num_ops > 1 */
412 __u64 ops;
413 };
414};
415
416#define MSM_WAIT_FENCE_BOOST 0x00000001
417#define MSM_WAIT_FENCE_FLAGS ( \
418 MSM_WAIT_FENCE_BOOST | \
419 0)
420
421/* The normal way to synchronize with the GPU is just to CPU_PREP on
422 * a buffer if you need to access it from the CPU (other cmdstream
423 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
424 * handle the required synchronization under the hood). This ioctl
425 * mainly just exists as a way to implement the gallium pipe_fence
426 * APIs without requiring a dummy bo to synchronize on.
427 */
428struct drm_msm_wait_fence {
429 __u32 fence; /* in */
430 __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */
431 struct drm_msm_timespec timeout; /* in */
432 __u32 queueid; /* in, submitqueue id */
433};
434
435/* madvise provides a way to tell the kernel in case a buffers contents
436 * can be discarded under memory pressure, which is useful for userspace
437 * bo cache where we want to optimistically hold on to buffer allocate
438 * and potential mmap, but allow the pages to be discarded under memory
439 * pressure.
440 *
441 * Typical usage would involve madvise(DONTNEED) when buffer enters BO
442 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
443 * In the WILLNEED case, 'retained' indicates to userspace whether the
444 * backing pages still exist.
445 */
446#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
447#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
448#define __MSM_MADV_PURGED 2 /* internal state */
449
450struct drm_msm_gem_madvise {
451 __u32 handle; /* in, GEM handle */
452 __u32 madv; /* in, MSM_MADV_x */
453 __u32 retained; /* out, whether backing store still exists */
454};
455
456/*
457 * Draw queues allow the user to set specific submission parameter. Command
458 * submissions specify a specific submitqueue to use. ID 0 is reserved for
459 * backwards compatibility as a "default" submitqueue.
460 *
461 * Because VM_BIND async updates happen on the CPU, they must run on a
462 * virtual queue created with the flag MSM_SUBMITQUEUE_VM_BIND. If we had
463 * a way to do pgtable updates on the GPU, we could drop this restriction.
464 */
465
466#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001
467#define MSM_SUBMITQUEUE_VM_BIND 0x00000002 /* virtual queue for VM_BIND ops */
468
469#define MSM_SUBMITQUEUE_FLAGS ( \
470 MSM_SUBMITQUEUE_ALLOW_PREEMPT | \
471 MSM_SUBMITQUEUE_VM_BIND | \
472 0)
473
474/*
475 * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
476 * a lower numeric value is higher priority.
477 */
478struct drm_msm_submitqueue {
479 __u32 flags; /* in, MSM_SUBMITQUEUE_x */
480 __u32 prio; /* in, Priority level */
481 __u32 id; /* out, identifier */
482};
483
484#define MSM_SUBMITQUEUE_PARAM_FAULTS 0
485
486struct drm_msm_submitqueue_query {
487 __u64 data;
488 __u32 id;
489 __u32 param;
490 __u32 len;
491 __u32 pad;
492};
493
494#define MSM_PERFCNTR_STREAM 0x00000001
495#define MSM_PERFCNTR_UPDATE 0x00000002
496#define MSM_PERFCNTR_FLAGS ( \
497 MSM_PERFCNTR_STREAM | \
498 MSM_PERFCNTR_UPDATE | \
499 0)
500
501struct drm_msm_perfcntr_group {
502 char group_name[16];
503 __u32 nr_countables;
504 __u32 pad; /* mbz */
505 __u64 countables; /* pointer to an array of nr_countables u32 */
506};
507
508/*
509 * Note, for MSM_PERFCNTR_STREAM, the ioctl returns an fd to read recorded
510 * counters. This only works because the ioctl is DRM_IOW(), if we returned
511 * a out param in the ioctl struct the copy_to_user() (in drm_ioctl())
512 * could fault, causing us to leak the fd.
513 *
514 * If the ioctl returns with error E2BIG, that means more counters/countables
515 * are requested than are currently available. If MSM_PERFCNTR_UPDATE flag
516 * is set, drm_msm_perfcntr_group::nr_countables will be updated to return
517 * the actual # of counters available.
518 *
519 * The data read from the has the following format for each sampling period:
520 *
521 * uint64_t timestamp; // CP_ALWAYS_ON_COUNTER captured at sample time
522 * uint32_t seqno; // increments by 1 each period, reset to 0 on discontinuity
523 * uint32_t mbz; // pad out counters to 64b
524 * struct {
525 * uint64_t counter[nr_countables];
526 * } groups[nr_groups];
527 *
528 * The ordering of groups and counters matches the order in PERFCNTR_CONFIG
529 * ioctl.
530 */
531struct drm_msm_perfcntr_config {
532 __u32 flags; /* bitmask of MSM_PERFCNTR_x */
533 __u32 nr_groups; /* # of entries in groups array */
534 __u64 groups; /* pointer to array of drm_msm_perfcntr_group */
535 __u64 period; /* sampling period in ns */
536 __u32 bufsz_shift; /* sample buffer size in bytes is 1<<bufsz_shift */
537 __u32 group_stride; /* sizeof(struct drm_msm_perfcntr_group) */
538};
539
540#define DRM_MSM_GET_PARAM 0x00
541#define DRM_MSM_SET_PARAM 0x01
542#define DRM_MSM_GEM_NEW 0x02
543#define DRM_MSM_GEM_INFO 0x03
544#define DRM_MSM_GEM_CPU_PREP 0x04
545#define DRM_MSM_GEM_CPU_FINI 0x05
546#define DRM_MSM_GEM_SUBMIT 0x06
547#define DRM_MSM_WAIT_FENCE 0x07
548#define DRM_MSM_GEM_MADVISE 0x08
549/* placeholder:
550#define DRM_MSM_GEM_SVM_NEW 0x09
551 */
552#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
553#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
554#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
555#define DRM_MSM_VM_BIND 0x0D
556#define DRM_MSM_PERFCNTR_CONFIG 0x0E
557
558#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
559#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
560#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
561#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
562#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
563#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
564#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
565#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
566#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
567#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
568#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
569#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
570#define DRM_IOCTL_MSM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind)
571#define DRM_IOCTL_MSM_PERFCNTR_CONFIG DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_PERFCNTR_CONFIG, struct drm_msm_perfcntr_config)
572
573#if defined(__cplusplus)
574}
575#endif
576
577#endif /* __MSM_DRM_H__ */