1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2/* Do not edit directly, auto-generated from: */
3/* Documentation/netlink/specs/dpll.yaml */
4/* YNL-GEN uapi header */
5/* To regenerate run: tools/net/ynl/ynl-regen.sh */
6
7#ifndef _LINUX_DPLL_H
8#define _LINUX_DPLL_H
9
10#define DPLL_FAMILY_NAME "dpll"
11#define DPLL_FAMILY_VERSION 1
12
13/**
14 * enum dpll_mode - working modes a dpll can support, differentiates if and how
15 * dpll selects one of its inputs to syntonize with it, valid values for
16 * DPLL_A_MODE attribute
17 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
18 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
19 */
20enum dpll_mode {
21 DPLL_MODE_MANUAL = 1,
22 DPLL_MODE_AUTOMATIC,
23
24 /* private: */
25 __DPLL_MODE_MAX,
26 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
27};
28
29/**
30 * enum dpll_lock_status - provides information of dpll device lock status,
31 * valid values for DPLL_A_LOCK_STATUS attribute
32 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
33 * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
34 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
35 * available
36 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
37 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
38 * was forced by disconnecting all the pins (latter possible only when dpll
39 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
40 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
41 * DPLL_LOCK_STATUS_UNLOCKED)
42 */
43enum dpll_lock_status {
44 DPLL_LOCK_STATUS_UNLOCKED = 1,
45 DPLL_LOCK_STATUS_LOCKED,
46 DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
47 DPLL_LOCK_STATUS_HOLDOVER,
48
49 /* private: */
50 __DPLL_LOCK_STATUS_MAX,
51 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
52};
53
54/**
55 * enum dpll_lock_status_error - if previous status change was done due to a
56 * failure, this provides information of dpll device lock status error. Valid
57 * values for DPLL_A_LOCK_STATUS_ERROR attribute
58 * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without
59 * any error
60 * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due
61 * to undefined error. Driver fills this value up in case it is not able to
62 * obtain suitable exact error type.
63 * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed
64 * because of associated media got down. This may happen for example if dpll
65 * device was previously locked on an input pin of type
66 * PIN_TYPE_SYNCE_ETH_PORT.
67 * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO
68 * (Fractional Frequency Offset) between the RX and TX symbol rate on the
69 * media got too high. This may happen for example if dpll device was
70 * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
71 */
72enum dpll_lock_status_error {
73 DPLL_LOCK_STATUS_ERROR_NONE = 1,
74 DPLL_LOCK_STATUS_ERROR_UNDEFINED,
75 DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN,
76 DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH,
77
78 /* private: */
79 __DPLL_LOCK_STATUS_ERROR_MAX,
80 DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)
81};
82
83/*
84 * level of quality of a clock device. This mainly applies when the dpll
85 * lock-status is DPLL_LOCK_STATUS_HOLDOVER. The current list is defined
86 * according to the table 11-7 contained in ITU-T G.8264/Y.1364 document. One
87 * may extend this list freely by other ITU-T defined clock qualities, or
88 * different ones defined by another standardization body (for those, please
89 * use different prefix).
90 */
91enum dpll_clock_quality_level {
92 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRC = 1,
93 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_A,
94 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_B,
95 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEC1,
96 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRTC,
97 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRTC,
98 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEEC,
99 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRC,
100
101 /* private: */
102 __DPLL_CLOCK_QUALITY_LEVEL_MAX,
103 DPLL_CLOCK_QUALITY_LEVEL_MAX = (__DPLL_CLOCK_QUALITY_LEVEL_MAX - 1)
104};
105
106#define DPLL_TEMP_DIVIDER 1000
107
108/**
109 * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
110 * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
111 * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
112 * @DPLL_TYPE_GENERIC: generic dpll type for devices outside PPS/EEC classes
113 */
114enum dpll_type {
115 DPLL_TYPE_PPS = 1,
116 DPLL_TYPE_EEC,
117 DPLL_TYPE_GENERIC,
118
119 /* private: */
120 __DPLL_TYPE_MAX,
121 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
122};
123
124/**
125 * enum dpll_pin_type - defines possible types of a pin, valid values for
126 * DPLL_A_PIN_TYPE attribute
127 * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
128 * @DPLL_PIN_TYPE_EXT: external input
129 * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
130 * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
131 * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
132 */
133enum dpll_pin_type {
134 DPLL_PIN_TYPE_MUX = 1,
135 DPLL_PIN_TYPE_EXT,
136 DPLL_PIN_TYPE_SYNCE_ETH_PORT,
137 DPLL_PIN_TYPE_INT_OSCILLATOR,
138 DPLL_PIN_TYPE_GNSS,
139
140 /* private: */
141 __DPLL_PIN_TYPE_MAX,
142 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
143};
144
145/**
146 * enum dpll_pin_direction - defines possible direction of a pin, valid values
147 * for DPLL_A_PIN_DIRECTION attribute
148 * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal
149 * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal
150 */
151enum dpll_pin_direction {
152 DPLL_PIN_DIRECTION_INPUT = 1,
153 DPLL_PIN_DIRECTION_OUTPUT,
154
155 /* private: */
156 __DPLL_PIN_DIRECTION_MAX,
157 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
158};
159
160#define DPLL_PIN_FREQUENCY_1_HZ 1
161#define DPLL_PIN_FREQUENCY_10_KHZ 10000
162#define DPLL_PIN_FREQUENCY_77_5_KHZ 77500
163#define DPLL_PIN_FREQUENCY_10_MHZ 10000000
164
165/**
166 * enum dpll_pin_state - defines possible states of a pin, valid values for
167 * DPLL_A_PIN_STATE attribute
168 * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop
169 * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid
170 * input
171 * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection
172 */
173enum dpll_pin_state {
174 DPLL_PIN_STATE_CONNECTED = 1,
175 DPLL_PIN_STATE_DISCONNECTED,
176 DPLL_PIN_STATE_SELECTABLE,
177
178 /* private: */
179 __DPLL_PIN_STATE_MAX,
180 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
181};
182
183/**
184 * enum dpll_pin_operstate - defines possible operational states of a pin with
185 * respect to its parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE
186 * attribute
187 * @DPLL_PIN_OPERSTATE_ACTIVE: pin is qualified and actively used by the DPLL
188 * @DPLL_PIN_OPERSTATE_STANDBY: pin is qualified but not actively used by the
189 * DPLL
190 * @DPLL_PIN_OPERSTATE_NO_SIGNAL: pin does not have a valid signal
191 * @DPLL_PIN_OPERSTATE_QUAL_FAILED: pin signal failed qualification (e.g.
192 * frequency or phase monitor)
193 */
194enum dpll_pin_operstate {
195 DPLL_PIN_OPERSTATE_ACTIVE = 1,
196 DPLL_PIN_OPERSTATE_STANDBY,
197 DPLL_PIN_OPERSTATE_NO_SIGNAL,
198 DPLL_PIN_OPERSTATE_QUAL_FAILED,
199
200 /* private: */
201 __DPLL_PIN_OPERSTATE_MAX,
202 DPLL_PIN_OPERSTATE_MAX = (__DPLL_PIN_OPERSTATE_MAX - 1)
203};
204
205/**
206 * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid
207 * flags on DPLL_A_PIN_CAPABILITIES attribute
208 * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed
209 * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed
210 * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed
211 */
212enum dpll_pin_capabilities {
213 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
214 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
215 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
216};
217
218#define DPLL_PHASE_OFFSET_DIVIDER 1000
219#define DPLL_PIN_MEASURED_FREQUENCY_DIVIDER 1000
220
221/**
222 * enum dpll_feature_state - Allow control (enable/disable) and status checking
223 * over features.
224 * @DPLL_FEATURE_STATE_DISABLE: feature shall be disabled
225 * @DPLL_FEATURE_STATE_ENABLE: feature shall be enabled
226 */
227enum dpll_feature_state {
228 DPLL_FEATURE_STATE_DISABLE,
229 DPLL_FEATURE_STATE_ENABLE,
230};
231
232enum dpll_a {
233 DPLL_A_ID = 1,
234 DPLL_A_MODULE_NAME,
235 DPLL_A_PAD,
236 DPLL_A_CLOCK_ID,
237 DPLL_A_MODE,
238 DPLL_A_MODE_SUPPORTED,
239 DPLL_A_LOCK_STATUS,
240 DPLL_A_TEMP,
241 DPLL_A_TYPE,
242 DPLL_A_LOCK_STATUS_ERROR,
243 DPLL_A_CLOCK_QUALITY_LEVEL,
244 DPLL_A_PHASE_OFFSET_MONITOR,
245 DPLL_A_PHASE_OFFSET_AVG_FACTOR,
246 DPLL_A_FREQUENCY_MONITOR,
247
248 __DPLL_A_MAX,
249 DPLL_A_MAX = (__DPLL_A_MAX - 1)
250};
251
252enum dpll_a_pin {
253 DPLL_A_PIN_ID = 1,
254 DPLL_A_PIN_PARENT_ID,
255 DPLL_A_PIN_MODULE_NAME,
256 DPLL_A_PIN_PAD,
257 DPLL_A_PIN_CLOCK_ID,
258 DPLL_A_PIN_BOARD_LABEL,
259 DPLL_A_PIN_PANEL_LABEL,
260 DPLL_A_PIN_PACKAGE_LABEL,
261 DPLL_A_PIN_TYPE,
262 DPLL_A_PIN_DIRECTION,
263 DPLL_A_PIN_FREQUENCY,
264 DPLL_A_PIN_FREQUENCY_SUPPORTED,
265 DPLL_A_PIN_FREQUENCY_MIN,
266 DPLL_A_PIN_FREQUENCY_MAX,
267 DPLL_A_PIN_PRIO,
268 DPLL_A_PIN_STATE,
269 DPLL_A_PIN_CAPABILITIES,
270 DPLL_A_PIN_PARENT_DEVICE,
271 DPLL_A_PIN_PARENT_PIN,
272 DPLL_A_PIN_PHASE_ADJUST_MIN,
273 DPLL_A_PIN_PHASE_ADJUST_MAX,
274 DPLL_A_PIN_PHASE_ADJUST,
275 DPLL_A_PIN_PHASE_OFFSET,
276 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,
277 DPLL_A_PIN_ESYNC_FREQUENCY,
278 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
279 DPLL_A_PIN_ESYNC_PULSE,
280 DPLL_A_PIN_REFERENCE_SYNC,
281 DPLL_A_PIN_PHASE_ADJUST_GRAN,
282 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT,
283 DPLL_A_PIN_MEASURED_FREQUENCY,
284 DPLL_A_PIN_OPERSTATE,
285
286 __DPLL_A_PIN_MAX,
287 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
288};
289
290enum dpll_cmd {
291 DPLL_CMD_DEVICE_ID_GET = 1,
292 DPLL_CMD_DEVICE_GET,
293 DPLL_CMD_DEVICE_SET,
294 DPLL_CMD_DEVICE_CREATE_NTF,
295 DPLL_CMD_DEVICE_DELETE_NTF,
296 DPLL_CMD_DEVICE_CHANGE_NTF,
297 DPLL_CMD_PIN_ID_GET,
298 DPLL_CMD_PIN_GET,
299 DPLL_CMD_PIN_SET,
300 DPLL_CMD_PIN_CREATE_NTF,
301 DPLL_CMD_PIN_DELETE_NTF,
302 DPLL_CMD_PIN_CHANGE_NTF,
303
304 __DPLL_CMD_MAX,
305 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
306};
307
308#define DPLL_MCGRP_MONITOR "monitor"
309
310#endif /* _LINUX_DPLL_H */