1/* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#ifndef _USR_IDXD_H_
4#define _USR_IDXD_H_
5
6#include <linux/types.h>
7
8/* Driver command error status */
9enum idxd_scmd_stat {
10 IDXD_SCMD_DEV_ENABLED = 0x80000010,
11 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
12 IDXD_SCMD_WQ_ENABLED = 0x80000021,
13 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
14 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
15 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
16 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
17 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
18 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
19 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
20 IDXD_SCMD_PERCPU_ERR = 0x80090000,
21 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
22 IDXD_SCMD_CDEV_ERR = 0x800b0000,
23 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
24 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
25 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
26 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
27 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
28 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
29 IDXD_SCMD_DEV_EVL_ERR = 0x80120000,
30 IDXD_SCMD_WQ_NO_DRV_NAME = 0x80200000,
31};
32
33#define IDXD_SCMD_SOFTERR_MASK 0x80000000
34#define IDXD_SCMD_SOFTERR_SHIFT 16
35
36/* Descriptor flags */
37#define IDXD_OP_FLAG_FENCE 0x0001
38#define IDXD_OP_FLAG_BOF 0x0002
39#define IDXD_OP_FLAG_CRAV 0x0004
40#define IDXD_OP_FLAG_RCR 0x0008
41#define IDXD_OP_FLAG_RCI 0x0010
42#define IDXD_OP_FLAG_CRSTS 0x0020
43#define IDXD_OP_FLAG_CR 0x0080
44#define IDXD_OP_FLAG_CC 0x0100
45#define IDXD_OP_FLAG_ADDR1_TCS 0x0200
46#define IDXD_OP_FLAG_ADDR2_TCS 0x0400
47#define IDXD_OP_FLAG_ADDR3_TCS 0x0800
48#define IDXD_OP_FLAG_CR_TCS 0x1000
49#define IDXD_OP_FLAG_STORD 0x2000
50#define IDXD_OP_FLAG_DRDBK 0x4000
51#define IDXD_OP_FLAG_DSTS 0x8000
52
53/* IAX */
54#define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000
55#define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000
56#define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000
57#define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000
58#define IDXD_OP_FLAG_SRC2_STS 0x100000
59#define IDXD_OP_FLAG_CRC_RFC3720 0x200000
60
61/* Opcode */
62enum dsa_opcode {
63 DSA_OPCODE_NOOP = 0,
64 DSA_OPCODE_BATCH,
65 DSA_OPCODE_DRAIN,
66 DSA_OPCODE_MEMMOVE,
67 DSA_OPCODE_MEMFILL,
68 DSA_OPCODE_COMPARE,
69 DSA_OPCODE_COMPVAL,
70 DSA_OPCODE_CR_DELTA,
71 DSA_OPCODE_AP_DELTA,
72 DSA_OPCODE_DUALCAST,
73 DSA_OPCODE_TRANSL_FETCH,
74 DSA_OPCODE_CRCGEN = 0x10,
75 DSA_OPCODE_COPY_CRC,
76 DSA_OPCODE_DIF_CHECK,
77 DSA_OPCODE_DIF_INS,
78 DSA_OPCODE_DIF_STRP,
79 DSA_OPCODE_DIF_UPDT,
80 DSA_OPCODE_DIX_GEN = 0x17,
81 DSA_OPCODE_CFLUSH = 0x20,
82};
83
84enum iax_opcode {
85 IAX_OPCODE_NOOP = 0,
86 IAX_OPCODE_DRAIN = 2,
87 IAX_OPCODE_MEMMOVE,
88 IAX_OPCODE_DECOMPRESS = 0x42,
89 IAX_OPCODE_COMPRESS,
90 IAX_OPCODE_CRC64,
91 IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
92 IAX_OPCODE_ZERO_DECOMP_16,
93 IAX_OPCODE_ZERO_COMP_32 = 0x4c,
94 IAX_OPCODE_ZERO_COMP_16,
95 IAX_OPCODE_SCAN = 0x50,
96 IAX_OPCODE_SET_MEMBER,
97 IAX_OPCODE_EXTRACT,
98 IAX_OPCODE_SELECT,
99 IAX_OPCODE_RLE_BURST,
100 IAX_OPCODE_FIND_UNIQUE,
101 IAX_OPCODE_EXPAND,
102};
103
104/* Completion record status */
105enum dsa_completion_status {
106 DSA_COMP_NONE = 0,
107 DSA_COMP_SUCCESS,
108 DSA_COMP_SUCCESS_PRED,
109 DSA_COMP_PAGE_FAULT_NOBOF,
110 DSA_COMP_PAGE_FAULT_IR,
111 DSA_COMP_BATCH_FAIL,
112 DSA_COMP_BATCH_PAGE_FAULT,
113 DSA_COMP_DR_OFFSET_NOINC,
114 DSA_COMP_DR_OFFSET_ERANGE,
115 DSA_COMP_DIF_ERR,
116 DSA_COMP_BAD_OPCODE = 0x10,
117 DSA_COMP_INVALID_FLAGS,
118 DSA_COMP_NOZERO_RESERVE,
119 DSA_COMP_XFER_ERANGE,
120 DSA_COMP_DESC_CNT_ERANGE,
121 DSA_COMP_DR_ERANGE,
122 DSA_COMP_OVERLAP_BUFFERS,
123 DSA_COMP_DCAST_ERR,
124 DSA_COMP_DESCLIST_ALIGN,
125 DSA_COMP_INT_HANDLE_INVAL,
126 DSA_COMP_CRA_XLAT,
127 DSA_COMP_CRA_ALIGN,
128 DSA_COMP_ADDR_ALIGN,
129 DSA_COMP_PRIV_BAD,
130 DSA_COMP_TRAFFIC_CLASS_CONF,
131 DSA_COMP_PFAULT_RDBA,
132 DSA_COMP_HW_ERR1,
133 DSA_COMP_HW_ERR_DRB,
134 DSA_COMP_TRANSLATION_FAIL,
135 DSA_COMP_DRAIN_EVL = 0x26,
136 DSA_COMP_BATCH_EVL_ERR,
137};
138
139enum iax_completion_status {
140 IAX_COMP_NONE = 0,
141 IAX_COMP_SUCCESS,
142 IAX_COMP_PAGE_FAULT_IR = 0x04,
143 IAX_COMP_ANALYTICS_ERROR = 0x0a,
144 IAX_COMP_OUTBUF_OVERFLOW,
145 IAX_COMP_BAD_OPCODE = 0x10,
146 IAX_COMP_INVALID_FLAGS,
147 IAX_COMP_NOZERO_RESERVE,
148 IAX_COMP_INVALID_SIZE,
149 IAX_COMP_OVERLAP_BUFFERS = 0x16,
150 IAX_COMP_INT_HANDLE_INVAL = 0x19,
151 IAX_COMP_CRA_XLAT,
152 IAX_COMP_CRA_ALIGN,
153 IAX_COMP_ADDR_ALIGN,
154 IAX_COMP_PRIV_BAD,
155 IAX_COMP_TRAFFIC_CLASS_CONF,
156 IAX_COMP_PFAULT_RDBA,
157 IAX_COMP_HW_ERR1,
158 IAX_COMP_HW_ERR_DRB,
159 IAX_COMP_TRANSLATION_FAIL,
160 IAX_COMP_PRS_TIMEOUT,
161 IAX_COMP_WATCHDOG,
162 IAX_COMP_INVALID_COMP_FLAG = 0x30,
163 IAX_COMP_INVALID_FILTER_FLAG,
164 IAX_COMP_INVALID_INPUT_SIZE,
165 IAX_COMP_INVALID_NUM_ELEMS,
166 IAX_COMP_INVALID_SRC1_WIDTH,
167 IAX_COMP_INVALID_INVERT_OUT,
168};
169
170#define DSA_COMP_STATUS_MASK 0x7f
171#define DSA_COMP_STATUS_WRITE 0x80
172#define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK)
173
174struct dsa_hw_desc {
175 __u32 pasid:20;
176 __u32 rsvd:11;
177 __u32 priv:1;
178 __u32 flags:24;
179 __u32 opcode:8;
180 __u64 completion_addr;
181 union {
182 __u64 src_addr;
183 __u64 rdback_addr;
184 __u64 pattern;
185 __u64 desc_list_addr;
186 __u64 pattern_lower;
187 __u64 transl_fetch_addr;
188 };
189 union {
190 __u64 dst_addr;
191 __u64 rdback_addr2;
192 __u64 src2_addr;
193 __u64 comp_pattern;
194 };
195 union {
196 __u32 xfer_size;
197 __u32 desc_count;
198 __u32 region_size;
199 };
200 __u16 int_handle;
201 __u16 rsvd1;
202 union {
203 __u8 expected_res;
204 /* create delta record */
205 struct {
206 __u64 delta_addr;
207 __u32 max_delta_size;
208 __u32 delt_rsvd;
209 __u8 expected_res_mask;
210 };
211 __u32 delta_rec_size;
212 __u64 dest2;
213 /* CRC */
214 struct {
215 __u32 crc_seed;
216 __u32 crc_rsvd;
217 __u64 seed_addr;
218 };
219 /* DIF check or strip */
220 struct {
221 __u8 src_dif_flags;
222 __u8 dif_chk_res;
223 __u8 dif_chk_flags;
224 __u8 dif_chk_res2[5];
225 __u32 chk_ref_tag_seed;
226 __u16 chk_app_tag_mask;
227 __u16 chk_app_tag_seed;
228 };
229 /* DIF insert */
230 struct {
231 __u8 dif_ins_res;
232 __u8 dest_dif_flag;
233 __u8 dif_ins_flags;
234 __u8 dif_ins_res2[13];
235 __u32 ins_ref_tag_seed;
236 __u16 ins_app_tag_mask;
237 __u16 ins_app_tag_seed;
238 };
239 /* DIF update */
240 struct {
241 __u8 src_upd_flags;
242 __u8 upd_dest_flags;
243 __u8 dif_upd_flags;
244 __u8 dif_upd_res[5];
245 __u32 src_ref_tag_seed;
246 __u16 src_app_tag_mask;
247 __u16 src_app_tag_seed;
248 __u32 dest_ref_tag_seed;
249 __u16 dest_app_tag_mask;
250 __u16 dest_app_tag_seed;
251 };
252
253 /* Fill */
254 __u64 pattern_upper;
255
256 /* Translation fetch */
257 struct {
258 __u64 transl_fetch_res;
259 __u32 region_stride;
260 };
261
262 /* DIX generate */
263 struct {
264 __u8 dix_gen_res;
265 __u8 dest_dif_flags;
266 __u8 dif_flags;
267 __u8 dix_gen_res2[13];
268 __u32 ref_tag_seed;
269 __u16 app_tag_mask;
270 __u16 app_tag_seed;
271 };
272
273 __u8 op_specific[24];
274 };
275} __attribute__((packed));
276
277struct iax_hw_desc {
278 __u32 pasid:20;
279 __u32 rsvd:11;
280 __u32 priv:1;
281 __u32 flags:24;
282 __u32 opcode:8;
283 __u64 completion_addr;
284 __u64 src1_addr;
285 __u64 dst_addr;
286 __u32 src1_size;
287 __u16 int_handle;
288 union {
289 __u16 compr_flags;
290 __u16 decompr_flags;
291 };
292 __u64 src2_addr;
293 __u32 max_dst_size;
294 __u32 src2_size;
295 __u32 filter_flags;
296 __u32 num_inputs;
297} __attribute__((packed));
298
299struct dsa_raw_desc {
300 __u64 field[8];
301} __attribute__((packed));
302
303/*
304 * The status field will be modified by hardware, therefore it should be
305 * __volatile__ and prevent the compiler from optimize the read.
306 */
307struct dsa_completion_record {
308 __volatile__ __u8 status;
309 union {
310 __u8 result;
311 __u8 dif_status;
312 };
313 __u8 fault_info;
314 __u8 rsvd;
315 union {
316 __u32 bytes_completed;
317 __u32 descs_completed;
318 };
319 __u64 fault_addr;
320 union {
321 /* common record */
322 struct {
323 __u32 invalid_flags:24;
324 __u32 rsvd2:8;
325 };
326
327 __u32 delta_rec_size;
328 __u64 crc_val;
329
330 /* DIF check & strip */
331 struct {
332 __u32 dif_chk_ref_tag;
333 __u16 dif_chk_app_tag_mask;
334 __u16 dif_chk_app_tag;
335 };
336
337 /* DIF insert */
338 struct {
339 __u64 dif_ins_res;
340 __u32 dif_ins_ref_tag;
341 __u16 dif_ins_app_tag_mask;
342 __u16 dif_ins_app_tag;
343 };
344
345 /* DIF update */
346 struct {
347 __u32 dif_upd_src_ref_tag;
348 __u16 dif_upd_src_app_tag_mask;
349 __u16 dif_upd_src_app_tag;
350 __u32 dif_upd_dest_ref_tag;
351 __u16 dif_upd_dest_app_tag_mask;
352 __u16 dif_upd_dest_app_tag;
353 };
354
355 /* DIX generate */
356 struct {
357 __u64 dix_gen_res;
358 __u32 dix_ref_tag;
359 __u16 dix_app_tag_mask;
360 __u16 dix_app_tag;
361 };
362
363 __u8 op_specific[16];
364 };
365} __attribute__((packed));
366
367struct dsa_raw_completion_record {
368 __u64 field[4];
369} __attribute__((packed));
370
371struct iax_completion_record {
372 __volatile__ __u8 status;
373 __u8 error_code;
374 __u8 fault_info;
375 __u8 rsvd;
376 __u32 bytes_completed;
377 __u64 fault_addr;
378 __u32 invalid_flags;
379 __u32 rsvd2;
380 __u32 output_size;
381 __u8 output_bits;
382 __u8 rsvd3;
383 __u16 xor_csum;
384 __u32 crc;
385 __u32 min;
386 __u32 max;
387 __u32 sum;
388 __u64 rsvd4[2];
389} __attribute__((packed));
390
391struct iax_raw_completion_record {
392 __u64 field[8];
393} __attribute__((packed));
394
395#endif