Meg's Mirrors

zig

1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2	/* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES.
3	*/
4	#ifndef _IOMMUFD_H
5	#define _IOMMUFD_H
6
7	#include <linux/ioctl.h>
8	#include <linux/types.h>
9
10	#define IOMMUFD_TYPE (';')
11
12	/**
13	* DOC: General ioctl format
14	*
15	* The ioctl interface follows a general format to allow for extensibility. Each
16	* ioctl is passed in a structure pointer as the argument providing the size of
17	* the structure in the first u32. The kernel checks that any structure space
18	* beyond what it understands is 0. This allows userspace to use the backward
19	* compatible portion while consistently using the newer, larger, structures.
20	*
21	* ioctls use a standard meaning for common errnos:
22	*
23	* - ENOTTY: The IOCTL number itself is not supported at all
24	* - E2BIG: The IOCTL number is supported, but the provided structure has
25	* non-zero in a part the kernel does not understand.
26	* - EOPNOTSUPP: The IOCTL number is supported, and the structure is
27	* understood, however a known field has a value the kernel does not
28	* understand or support.
29	* - EINVAL: Everything about the IOCTL was understood, but a field is not
30	* correct.
31	* - ENOENT: An ID or IOVA provided does not exist.
32	* - ENOMEM: Out of memory.
33	* - EOVERFLOW: Mathematics overflowed.
34	*
35	* As well as additional errnos, within specific ioctls.
36	*/
37	enum {
38	IOMMUFD_CMD_BASE = 0x80,
39	IOMMUFD_CMD_DESTROY = IOMMUFD_CMD_BASE,
40	IOMMUFD_CMD_IOAS_ALLOC = 0x81,
41	IOMMUFD_CMD_IOAS_ALLOW_IOVAS = 0x82,
42	IOMMUFD_CMD_IOAS_COPY = 0x83,
43	IOMMUFD_CMD_IOAS_IOVA_RANGES = 0x84,
44	IOMMUFD_CMD_IOAS_MAP = 0x85,
45	IOMMUFD_CMD_IOAS_UNMAP = 0x86,
46	IOMMUFD_CMD_OPTION = 0x87,
47	IOMMUFD_CMD_VFIO_IOAS = 0x88,
48	IOMMUFD_CMD_HWPT_ALLOC = 0x89,
49	IOMMUFD_CMD_GET_HW_INFO = 0x8a,
50	IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING = 0x8b,
51	IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP = 0x8c,
52	IOMMUFD_CMD_HWPT_INVALIDATE = 0x8d,
53	IOMMUFD_CMD_FAULT_QUEUE_ALLOC = 0x8e,
54	IOMMUFD_CMD_IOAS_MAP_FILE = 0x8f,
55	IOMMUFD_CMD_VIOMMU_ALLOC = 0x90,
56	IOMMUFD_CMD_VDEVICE_ALLOC = 0x91,
57	IOMMUFD_CMD_IOAS_CHANGE_PROCESS = 0x92,
58	IOMMUFD_CMD_VEVENTQ_ALLOC = 0x93,
59	IOMMUFD_CMD_HW_QUEUE_ALLOC = 0x94,
60	};
61
62	/**
63	* struct iommu_destroy - ioctl(IOMMU_DESTROY)
64	* @size: sizeof(struct iommu_destroy)
65	* @id: iommufd object ID to destroy. Can be any destroyable object type.
66	*
67	* Destroy any object held within iommufd.
68	*/
69	struct iommu_destroy {
70	__u32 size;
71	__u32 id;
72	};
73	#define IOMMU_DESTROY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DESTROY)
74
75	/**
76	* struct iommu_ioas_alloc - ioctl(IOMMU_IOAS_ALLOC)
77	* @size: sizeof(struct iommu_ioas_alloc)
78	* @flags: Must be 0
79	* @out_ioas_id: Output IOAS ID for the allocated object
80	*
81	* Allocate an IO Address Space (IOAS) which holds an IO Virtual Address (IOVA)
82	* to memory mapping.
83	*/
84	struct iommu_ioas_alloc {
85	__u32 size;
86	__u32 flags;
87	__u32 out_ioas_id;
88	};
89	#define IOMMU_IOAS_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_ALLOC)
90
91	/**
92	* struct iommu_iova_range - ioctl(IOMMU_IOVA_RANGE)
93	* @start: First IOVA
94	* @last: Inclusive last IOVA
95	*
96	* An interval in IOVA space.
97	*/
98	struct iommu_iova_range {
99	__aligned_u64 start;
100	__aligned_u64 last;
101	};
102
103	/**
104	* struct iommu_ioas_iova_ranges - ioctl(IOMMU_IOAS_IOVA_RANGES)
105	* @size: sizeof(struct iommu_ioas_iova_ranges)
106	* @ioas_id: IOAS ID to read ranges from
107	* @num_iovas: Input/Output total number of ranges in the IOAS
108	* @__reserved: Must be 0
109	* @allowed_iovas: Pointer to the output array of struct iommu_iova_range
110	* @out_iova_alignment: Minimum alignment required for mapping IOVA
111	*
112	* Query an IOAS for ranges of allowed IOVAs. Mapping IOVA outside these ranges
113	* is not allowed. num_iovas will be set to the total number of iovas and
114	* the allowed_iovas[] will be filled in as space permits.
115	*
116	* The allowed ranges are dependent on the HW path the DMA operation takes, and
117	* can change during the lifetime of the IOAS. A fresh empty IOAS will have a
118	* full range, and each attached device will narrow the ranges based on that
119	* device's HW restrictions. Detaching a device can widen the ranges. Userspace
120	* should query ranges after every attach/detach to know what IOVAs are valid
121	* for mapping.
122	*
123	* On input num_iovas is the length of the allowed_iovas array. On output it is
124	* the total number of iovas filled in. The ioctl will return -EMSGSIZE and set
125	* num_iovas to the required value if num_iovas is too small. In this case the
126	* caller should allocate a larger output array and re-issue the ioctl.
127	*
128	* out_iova_alignment returns the minimum IOVA alignment that can be given
129	* to IOMMU_IOAS_MAP/COPY. IOVA's must satisfy::
130	*
131	* starting_iova % out_iova_alignment == 0
132	* (starting_iova + length) % out_iova_alignment == 0
133	*
134	* out_iova_alignment can be 1 indicating any IOVA is allowed. It cannot
135	* be higher than the system PAGE_SIZE.
136	*/
137	struct iommu_ioas_iova_ranges {
138	__u32 size;
139	__u32 ioas_id;
140	__u32 num_iovas;
141	__u32 __reserved;
142	__aligned_u64 allowed_iovas;
143	__aligned_u64 out_iova_alignment;
144	};
145	#define IOMMU_IOAS_IOVA_RANGES _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_IOVA_RANGES)
146
147	/**
148	* struct iommu_ioas_allow_iovas - ioctl(IOMMU_IOAS_ALLOW_IOVAS)
149	* @size: sizeof(struct iommu_ioas_allow_iovas)
150	* @ioas_id: IOAS ID to allow IOVAs from
151	* @num_iovas: Input/Output total number of ranges in the IOAS
152	* @__reserved: Must be 0
153	* @allowed_iovas: Pointer to array of struct iommu_iova_range
154	*
155	* Ensure a range of IOVAs are always available for allocation. If this call
156	* succeeds then IOMMU_IOAS_IOVA_RANGES will never return a list of IOVA ranges
157	* that are narrower than the ranges provided here. This call will fail if
158	* IOMMU_IOAS_IOVA_RANGES is currently narrower than the given ranges.
159	*
160	* When an IOAS is first created the IOVA_RANGES will be maximally sized, and as
161	* devices are attached the IOVA will narrow based on the device restrictions.
162	* When an allowed range is specified any narrowing will be refused, ie device
163	* attachment can fail if the device requires limiting within the allowed range.
164	*
165	* Automatic IOVA allocation is also impacted by this call. MAP will only
166	* allocate within the allowed IOVAs if they are present.
167	*
168	* This call replaces the entire allowed list with the given list.
169	*/
170	struct iommu_ioas_allow_iovas {
171	__u32 size;
172	__u32 ioas_id;
173	__u32 num_iovas;
174	__u32 __reserved;
175	__aligned_u64 allowed_iovas;
176	};
177	#define IOMMU_IOAS_ALLOW_IOVAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_ALLOW_IOVAS)
178
179	/**
180	* enum iommufd_ioas_map_flags - Flags for map and copy
181	* @IOMMU_IOAS_MAP_FIXED_IOVA: If clear the kernel will compute an appropriate
182	* IOVA to place the mapping at
183	* @IOMMU_IOAS_MAP_WRITEABLE: DMA is allowed to write to this mapping
184	* @IOMMU_IOAS_MAP_READABLE: DMA is allowed to read from this mapping
185	*/
186	enum iommufd_ioas_map_flags {
187	IOMMU_IOAS_MAP_FIXED_IOVA = 1 << 0,
188	IOMMU_IOAS_MAP_WRITEABLE = 1 << 1,
189	IOMMU_IOAS_MAP_READABLE = 1 << 2,
190	};
191
192	/**
193	* struct iommu_ioas_map - ioctl(IOMMU_IOAS_MAP)
194	* @size: sizeof(struct iommu_ioas_map)
195	* @flags: Combination of enum iommufd_ioas_map_flags
196	* @ioas_id: IOAS ID to change the mapping of
197	* @__reserved: Must be 0
198	* @user_va: Userspace pointer to start mapping from
199	* @length: Number of bytes to map
200	* @iova: IOVA the mapping was placed at. If IOMMU_IOAS_MAP_FIXED_IOVA is set
201	* then this must be provided as input.
202	*
203	* Set an IOVA mapping from a user pointer. If FIXED_IOVA is specified then the
204	* mapping will be established at iova, otherwise a suitable location based on
205	* the reserved and allowed lists will be automatically selected and returned in
206	* iova.
207	*
208	* If IOMMU_IOAS_MAP_FIXED_IOVA is specified then the iova range must currently
209	* be unused, existing IOVA cannot be replaced.
210	*/
211	struct iommu_ioas_map {
212	__u32 size;
213	__u32 flags;
214	__u32 ioas_id;
215	__u32 __reserved;
216	__aligned_u64 user_va;
217	__aligned_u64 length;
218	__aligned_u64 iova;
219	};
220	#define IOMMU_IOAS_MAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP)
221
222	/**
223	* struct iommu_ioas_map_file - ioctl(IOMMU_IOAS_MAP_FILE)
224	* @size: sizeof(struct iommu_ioas_map_file)
225	* @flags: same as for iommu_ioas_map
226	* @ioas_id: same as for iommu_ioas_map
227	* @fd: the memfd or supported dma-buf file to map
228	* @start: byte offset from start of the file to map from
229	* @length: same as for iommu_ioas_map
230	* @iova: same as for iommu_ioas_map
231	*
232	* Set an IOVA mapping from a memfd file. On kernels with dma-buf support,
233	* supported dma-buf files may also be accepted. This is not a generic
234	* dma-buf import path; currently supported dma-bufs include single-range
235	* VFIO PCI dma-bufs exported through VFIO_DEVICE_FEATURE_DMA_BUF, and
236	* other dma-bufs may be rejected. All other arguments and semantics match
237	* those of IOMMU_IOAS_MAP.
238	*/
239	struct iommu_ioas_map_file {
240	__u32 size;
241	__u32 flags;
242	__u32 ioas_id;
243	__s32 fd;
244	__aligned_u64 start;
245	__aligned_u64 length;
246	__aligned_u64 iova;
247	};
248	#define IOMMU_IOAS_MAP_FILE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP_FILE)
249
250	/**
251	* struct iommu_ioas_copy - ioctl(IOMMU_IOAS_COPY)
252	* @size: sizeof(struct iommu_ioas_copy)
253	* @flags: Combination of enum iommufd_ioas_map_flags
254	* @dst_ioas_id: IOAS ID to change the mapping of
255	* @src_ioas_id: IOAS ID to copy from
256	* @length: Number of bytes to copy and map
257	* @dst_iova: IOVA the mapping was placed at. If IOMMU_IOAS_MAP_FIXED_IOVA is
258	* set then this must be provided as input.
259	* @src_iova: IOVA to start the copy
260	*
261	* Copy an already existing mapping from src_ioas_id and establish it in
262	* dst_ioas_id. The src iova/length must exactly match a range used with
263	* IOMMU_IOAS_MAP.
264	*
265	* This may be used to efficiently clone a subset of an IOAS to another, or as a
266	* kind of 'cache' to speed up mapping. Copy has an efficiency advantage over
267	* establishing equivalent new mappings, as internal resources are shared, and
268	* the kernel will pin the user memory only once.
269	*/
270	struct iommu_ioas_copy {
271	__u32 size;
272	__u32 flags;
273	__u32 dst_ioas_id;
274	__u32 src_ioas_id;
275	__aligned_u64 length;
276	__aligned_u64 dst_iova;
277	__aligned_u64 src_iova;
278	};
279	#define IOMMU_IOAS_COPY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_COPY)
280
281	/**
282	* struct iommu_ioas_unmap - ioctl(IOMMU_IOAS_UNMAP)
283	* @size: sizeof(struct iommu_ioas_unmap)
284	* @ioas_id: IOAS ID to change the mapping of
285	* @iova: IOVA to start the unmapping at
286	* @length: Number of bytes to unmap, and return back the bytes unmapped
287	*
288	* Unmap an IOVA range. The iova/length must be a superset of a previously
289	* mapped range used with IOMMU_IOAS_MAP or IOMMU_IOAS_COPY. Splitting or
290	* truncating ranges is not allowed. The values 0 to U64_MAX will unmap
291	* everything.
292	*/
293	struct iommu_ioas_unmap {
294	__u32 size;
295	__u32 ioas_id;
296	__aligned_u64 iova;
297	__aligned_u64 length;
298	};
299	#define IOMMU_IOAS_UNMAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_UNMAP)
300
301	/**
302	* enum iommufd_option - ioctl(IOMMU_OPTION_RLIMIT_MODE) and
303	* ioctl(IOMMU_OPTION_HUGE_PAGES)
304	* @IOMMU_OPTION_RLIMIT_MODE:
305	* Change how RLIMIT_MEMLOCK accounting works. The caller must have privilege
306	* to invoke this. Value 0 (default) is user based accounting, 1 uses process
307	* based accounting. Global option, object_id must be 0
308	* @IOMMU_OPTION_HUGE_PAGES:
309	* Value 1 (default) allows contiguous pages to be combined when generating
310	* iommu mappings. Value 0 disables combining, everything is mapped to
311	* PAGE_SIZE. This can be useful for benchmarking. This is a per-IOAS
312	* option, the object_id must be the IOAS ID.
313	*/
314	enum iommufd_option {
315	IOMMU_OPTION_RLIMIT_MODE = 0,
316	IOMMU_OPTION_HUGE_PAGES = 1,
317	};
318
319	/**
320	* enum iommufd_option_ops - ioctl(IOMMU_OPTION_OP_SET) and
321	* ioctl(IOMMU_OPTION_OP_GET)
322	* @IOMMU_OPTION_OP_SET: Set the option's value
323	* @IOMMU_OPTION_OP_GET: Get the option's value
324	*/
325	enum iommufd_option_ops {
326	IOMMU_OPTION_OP_SET = 0,
327	IOMMU_OPTION_OP_GET = 1,
328	};
329
330	/**
331	* struct iommu_option - iommu option multiplexer
332	* @size: sizeof(struct iommu_option)
333	* @option_id: One of enum iommufd_option
334	* @op: One of enum iommufd_option_ops
335	* @__reserved: Must be 0
336	* @object_id: ID of the object if required
337	* @val64: Option value to set or value returned on get
338	*
339	* Change a simple option value. This multiplexor allows controlling options
340	* on objects. IOMMU_OPTION_OP_SET will load an option and IOMMU_OPTION_OP_GET
341	* will return the current value.
342	*/
343	struct iommu_option {
344	__u32 size;
345	__u32 option_id;
346	__u16 op;
347	__u16 __reserved;
348	__u32 object_id;
349	__aligned_u64 val64;
350	};
351	#define IOMMU_OPTION _IO(IOMMUFD_TYPE, IOMMUFD_CMD_OPTION)
352
353	/**
354	* enum iommufd_vfio_ioas_op - IOMMU_VFIO_IOAS_* ioctls
355	* @IOMMU_VFIO_IOAS_GET: Get the current compatibility IOAS
356	* @IOMMU_VFIO_IOAS_SET: Change the current compatibility IOAS
357	* @IOMMU_VFIO_IOAS_CLEAR: Disable VFIO compatibility
358	*/
359	enum iommufd_vfio_ioas_op {
360	IOMMU_VFIO_IOAS_GET = 0,
361	IOMMU_VFIO_IOAS_SET = 1,
362	IOMMU_VFIO_IOAS_CLEAR = 2,
363	};
364
365	/**
366	* struct iommu_vfio_ioas - ioctl(IOMMU_VFIO_IOAS)
367	* @size: sizeof(struct iommu_vfio_ioas)
368	* @ioas_id: For IOMMU_VFIO_IOAS_SET the input IOAS ID to set
369	* For IOMMU_VFIO_IOAS_GET will output the IOAS ID
370	* @op: One of enum iommufd_vfio_ioas_op
371	* @__reserved: Must be 0
372	*
373	* The VFIO compatibility support uses a single ioas because VFIO APIs do not
374	* support the ID field. Set or Get the IOAS that VFIO compatibility will use.
375	* When VFIO_GROUP_SET_CONTAINER is used on an iommufd it will get the
376	* compatibility ioas, either by taking what is already set, or auto creating
377	* one. From then on VFIO will continue to use that ioas and is not effected by
378	* this ioctl. SET or CLEAR does not destroy any auto-created IOAS.
379	*/
380	struct iommu_vfio_ioas {
381	__u32 size;
382	__u32 ioas_id;
383	__u16 op;
384	__u16 __reserved;
385	};
386	#define IOMMU_VFIO_IOAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VFIO_IOAS)
387
388	/**
389	* enum iommufd_hwpt_alloc_flags - Flags for HWPT allocation
390	* @IOMMU_HWPT_ALLOC_NEST_PARENT: If set, allocate a HWPT that can serve as
391	* the parent HWPT in a nesting configuration.
392	* @IOMMU_HWPT_ALLOC_DIRTY_TRACKING: Dirty tracking support for device IOMMU is
393	* enforced on device attachment
394	* @IOMMU_HWPT_FAULT_ID_VALID: The fault_id field of hwpt allocation data is
395	* valid.
396	* @IOMMU_HWPT_ALLOC_PASID: Requests a domain that can be used with PASID. The
397	* domain can be attached to any PASID on the device.
398	* Any domain attached to the non-PASID part of the
399	* device must also be flagged, otherwise attaching a
400	* PASID will blocked.
401	* For the user that wants to attach PASID, ioas is
402	* not recommended for both the non-PASID part
403	* and PASID part of the device.
404	* If IOMMU does not support PASID it will return
405	* error (-EOPNOTSUPP).
406	*/
407	enum iommufd_hwpt_alloc_flags {
408	IOMMU_HWPT_ALLOC_NEST_PARENT = 1 << 0,
409	IOMMU_HWPT_ALLOC_DIRTY_TRACKING = 1 << 1,
410	IOMMU_HWPT_FAULT_ID_VALID = 1 << 2,
411	IOMMU_HWPT_ALLOC_PASID = 1 << 3,
412	};
413
414	/**
415	* enum iommu_hwpt_vtd_s1_flags - Intel VT-d stage-1 page table
416	* entry attributes
417	* @IOMMU_VTD_S1_SRE: Supervisor request
418	* @IOMMU_VTD_S1_EAFE: Extended access enable
419	* @IOMMU_VTD_S1_WPE: Write protect enable
420	*/
421	enum iommu_hwpt_vtd_s1_flags {
422	IOMMU_VTD_S1_SRE = 1 << 0,
423	IOMMU_VTD_S1_EAFE = 1 << 1,
424	IOMMU_VTD_S1_WPE = 1 << 2,
425	};
426
427	/**
428	* struct iommu_hwpt_vtd_s1 - Intel VT-d stage-1 page table
429	* info (IOMMU_HWPT_DATA_VTD_S1)
430	* @flags: Combination of enum iommu_hwpt_vtd_s1_flags
431	* @pgtbl_addr: The base address of the stage-1 page table.
432	* @addr_width: The address width of the stage-1 page table
433	* @__reserved: Must be 0
434	*/
435	struct iommu_hwpt_vtd_s1 {
436	__aligned_u64 flags;
437	__aligned_u64 pgtbl_addr;
438	__u32 addr_width;
439	__u32 __reserved;
440	};
441
442	/**
443	* struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 nested STE
444	* (IOMMU_HWPT_DATA_ARM_SMMUV3)
445	*
446	* @ste: The first two double words of the user space Stream Table Entry for
447	* the translation. Must be little-endian.
448	* Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec)
449	* - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax
450	* - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD
451	*
452	* -EIO will be returned if @ste is not legal or contains any non-allowed field.
453	* Cfg can be used to select a S1, Bypass or Abort configuration. A Bypass
454	* nested domain will translate the same as the nesting parent. The S1 will
455	* install a Context Descriptor Table pointing at userspace memory translated
456	* by the nesting parent.
457	*
458	* It's suggested to allocate a vDEVICE object carrying vSID and then re-attach
459	* the nested domain, as soon as the vSID is available in the VMM level:
460	*
461	* - when Cfg=translate, a vDEVICE must be allocated prior to attaching to the
462	* allocated nested domain, as CD/ATS invalidations and vevents need a vSID.
463	* - when Cfg=bypass/abort, a vDEVICE is not enforced during the nested domain
464	* attachment, to support a GBPA case where VM sets CR0.SMMUEN=0. However, if
465	* VM sets CR0.SMMUEN=1 while missing a vDEVICE object, kernel would fail to
466	* report events to the VM. E.g. F_TRANSLATION when guest STE.Cfg=abort.
467	*/
468	struct iommu_hwpt_arm_smmuv3 {
469	__aligned_le64 ste[2];
470	};
471
472	/**
473	* struct iommu_hwpt_amd_guest - AMD IOMMU guest I/O page table data
474	* (IOMMU_HWPT_DATA_AMD_GUEST)
475	* @dte: Guest Device Table Entry (DTE)
476	*/
477	struct iommu_hwpt_amd_guest {
478	__aligned_u64 dte[4];
479	};
480
481	/**
482	* enum iommu_hwpt_data_type - IOMMU HWPT Data Type
483	* @IOMMU_HWPT_DATA_NONE: no data
484	* @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table
485	* @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table
486	* @IOMMU_HWPT_DATA_AMD_GUEST: AMD IOMMU guest page table
487	*/
488	enum iommu_hwpt_data_type {
489	IOMMU_HWPT_DATA_NONE = 0,
490	IOMMU_HWPT_DATA_VTD_S1 = 1,
491	IOMMU_HWPT_DATA_ARM_SMMUV3 = 2,
492	IOMMU_HWPT_DATA_AMD_GUEST = 3,
493	};
494
495	/**
496	* struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC)
497	* @size: sizeof(struct iommu_hwpt_alloc)
498	* @flags: Combination of enum iommufd_hwpt_alloc_flags
499	* @dev_id: The device to allocate this HWPT for
500	* @pt_id: The IOAS or HWPT or vIOMMU to connect this HWPT to
501	* @out_hwpt_id: The ID of the new HWPT
502	* @__reserved: Must be 0
503	* @data_type: One of enum iommu_hwpt_data_type
504	* @data_len: Length of the type specific data
505	* @data_uptr: User pointer to the type specific data
506	* @fault_id: The ID of IOMMUFD_FAULT object. Valid only if flags field of
507	* IOMMU_HWPT_FAULT_ID_VALID is set.
508	* @__reserved2: Padding to 64-bit alignment. Must be 0.
509	*
510	* Explicitly allocate a hardware page table object. This is the same object
511	* type that is returned by iommufd_device_attach() and represents the
512	* underlying iommu driver's iommu_domain kernel object.
513	*
514	* A kernel-managed HWPT will be created with the mappings from the given
515	* IOAS via the @pt_id. The @data_type for this allocation must be set to
516	* IOMMU_HWPT_DATA_NONE. The HWPT can be allocated as a parent HWPT for a
517	* nesting configuration by passing IOMMU_HWPT_ALLOC_NEST_PARENT via @flags.
518	*
519	* A user-managed nested HWPT will be created from a given vIOMMU (wrapping a
520	* parent HWPT) or a parent HWPT via @pt_id, in which the parent HWPT must be
521	* allocated previously via the same ioctl from a given IOAS (@pt_id). In this
522	* case, the @data_type must be set to a pre-defined type corresponding to an
523	* I/O page table type supported by the underlying IOMMU hardware. The device
524	* via @dev_id and the vIOMMU via @pt_id must be associated to the same IOMMU
525	* instance.
526	*
527	* If the @data_type is set to IOMMU_HWPT_DATA_NONE, @data_len and
528	* @data_uptr should be zero. Otherwise, both @data_len and @data_uptr
529	* must be given.
530	*/
531	struct iommu_hwpt_alloc {
532	__u32 size;
533	__u32 flags;
534	__u32 dev_id;
535	__u32 pt_id;
536	__u32 out_hwpt_id;
537	__u32 __reserved;
538	__u32 data_type;
539	__u32 data_len;
540	__aligned_u64 data_uptr;
541	__u32 fault_id;
542	__u32 __reserved2;
543	};
544	#define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC)
545
546	/**
547	* enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info
548	* @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings
549	* on a nested_parent domain.
550	* https://www.intel.com/content/www/us/en/content-details/772415/content-details.html
551	*/
552	enum iommu_hw_info_vtd_flags {
553	IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0,
554	};
555
556	/**
557	* struct iommu_hw_info_vtd - Intel VT-d hardware information
558	*
559	* @flags: Combination of enum iommu_hw_info_vtd_flags
560	* @__reserved: Must be 0
561	*
562	* @cap_reg: Value of Intel VT-d capability register defined in VT-d spec
563	* section 11.4.2 Capability Register.
564	* @ecap_reg: Value of Intel VT-d capability register defined in VT-d spec
565	* section 11.4.3 Extended Capability Register.
566	*
567	* User needs to understand the Intel VT-d specification to decode the
568	* register value.
569	*/
570	struct iommu_hw_info_vtd {
571	__u32 flags;
572	__u32 __reserved;
573	__aligned_u64 cap_reg;
574	__aligned_u64 ecap_reg;
575	};
576
577	/**
578	* struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information
579	* (IOMMU_HW_INFO_TYPE_ARM_SMMUV3)
580	*
581	* @flags: Must be set to 0
582	* @__reserved: Must be 0
583	* @idr: Implemented features for ARM SMMU Non-secure programming interface
584	* @iidr: Information about the implementation and implementer of ARM SMMU,
585	* and architecture version supported
586	* @aidr: ARM SMMU architecture version
587	*
588	* For the details of @idr, @iidr and @aidr, please refer to the chapters
589	* from 6.3.1 to 6.3.6 in the SMMUv3 Spec.
590	*
591	* This reports the raw HW capability, and not all bits are meaningful to be
592	* read by userspace. Only the following fields should be used:
593	*
594	* idr[0]: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN , CD2L, ASID16, TTF
595	* idr[1]: SIDSIZE, SSIDSIZE
596	* idr[3]: BBML, RIL
597	* idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K
598	*
599	* - S1P should be assumed to be true if a NESTED HWPT can be created
600	* - VFIO/iommufd only support platforms with COHACC, it should be assumed to be
601	* true.
602	* - ATS is a per-device property. If the VMM describes any devices as ATS
603	* capable in ACPI/DT it should set the corresponding idr.
604	*
605	* This list may expand in future (eg E0PD, AIE, PBHA, D128, DS etc). It is
606	* important that VMMs do not read bits outside the list to allow for
607	* compatibility with future kernels. Several features in the SMMUv3
608	* architecture are not currently supported by the kernel for nesting: HTTU,
609	* BTM, MPAM and others.
610	*/
611	struct iommu_hw_info_arm_smmuv3 {
612	__u32 flags;
613	__u32 __reserved;
614	__u32 idr[6];
615	__u32 iidr;
616	__u32 aidr;
617	};
618
619	/**
620	* struct iommu_hw_info_tegra241_cmdqv - NVIDIA Tegra241 CMDQV Hardware
621	* Information (IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV)
622	*
623	* @flags: Must be 0
624	* @version: Version number for the CMDQ-V HW for PARAM bits[03:00]
625	* @log2vcmdqs: Log2 of the total number of VCMDQs for PARAM bits[07:04]
626	* @log2vsids: Log2 of the total number of SID replacements for PARAM bits[15:12]
627	* @__reserved: Must be 0
628	*
629	* VMM can use these fields directly in its emulated global PARAM register. Note
630	* that only one Virtual Interface (VINTF) should be exposed to a VM, i.e. PARAM
631	* bits[11:08] should be set to 0 for log2 of the total number of VINTFs.
632	*/
633	struct iommu_hw_info_tegra241_cmdqv {
634	__u32 flags;
635	__u8 version;
636	__u8 log2vcmdqs;
637	__u8 log2vsids;
638	__u8 __reserved;
639	};
640
641	/**
642	* struct iommu_hw_info_amd - AMD IOMMU device info
643	*
644	* @efr : Value of AMD IOMMU Extended Feature Register (EFR)
645	* @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2)
646	*
647	* Please See description of these registers in the following sections of
648	* the AMD I/O Virtualization Technology (IOMMU) Specification.
649	* (https://docs.amd.com/v/u/en-US/48882_3.10_PUB)
650	*
651	* - MMIO Offset 0030h IOMMU Extended Feature Register
652	* - MMIO Offset 01A0h IOMMU Extended Feature 2 Register
653	*
654	* Note: The EFR and EFR2 are raw values reported by hardware.
655	* VMM is responsible to determine the appropriate flags to be exposed to
656	* the VM since cetertain features are not currently supported by the kernel
657	* for HW-vIOMMU.
658	*
659	* Current VMM-allowed list of feature flags are:
660	* - EFR[GTSup, GASup, GioSup, PPRSup, EPHSup, GATS, GLX, PASmax]
661	*/
662	struct iommu_hw_info_amd {
663	__aligned_u64 efr;
664	__aligned_u64 efr2;
665	};
666
667	/**
668	* enum iommu_hw_info_type - IOMMU Hardware Info Types
669	* @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware
670	* info
671	* @IOMMU_HW_INFO_TYPE_DEFAULT: Input to request for a default type
672	* @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type
673	* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type
674	* @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM
675	* SMMUv3) info type
676	* @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type
677	*/
678	enum iommu_hw_info_type {
679	IOMMU_HW_INFO_TYPE_NONE = 0,
680	IOMMU_HW_INFO_TYPE_DEFAULT = 0,
681	IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,
682	IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,
683	IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,
684	IOMMU_HW_INFO_TYPE_AMD = 4,
685	};
686
687	/**
688	* enum iommufd_hw_capabilities
689	* @IOMMU_HW_CAP_DIRTY_TRACKING: IOMMU hardware support for dirty tracking
690	* If available, it means the following APIs
691	* are supported:
692	*
693	* IOMMU_HWPT_GET_DIRTY_BITMAP
694	* IOMMU_HWPT_SET_DIRTY_TRACKING
695	*
696	* @IOMMU_HW_CAP_PCI_PASID_EXEC: Execute Permission Supported, user ignores it
697	* when the struct
698	* iommu_hw_info::out_max_pasid_log2 is zero.
699	* @IOMMU_HW_CAP_PCI_PASID_PRIV: Privileged Mode Supported, user ignores it
700	* when the struct
701	* iommu_hw_info::out_max_pasid_log2 is zero.
702	* @IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED: ATS is not supported or cannot be used
703	* on this device (absence implies ATS
704	* may be enabled)
705	*/
706	enum iommufd_hw_capabilities {
707	IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0,
708	IOMMU_HW_CAP_PCI_PASID_EXEC = 1 << 1,
709	IOMMU_HW_CAP_PCI_PASID_PRIV = 1 << 2,
710	IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED = 1 << 3,
711	};
712
713	/**
714	* enum iommufd_hw_info_flags - Flags for iommu_hw_info
715	* @IOMMU_HW_INFO_FLAG_INPUT_TYPE: If set, @in_data_type carries an input type
716	* for user space to request for a specific info
717	*/
718	enum iommufd_hw_info_flags {
719	IOMMU_HW_INFO_FLAG_INPUT_TYPE = 1 << 0,
720	};
721
722	/**
723	* struct iommu_hw_info - ioctl(IOMMU_GET_HW_INFO)
724	* @size: sizeof(struct iommu_hw_info)
725	* @flags: Must be 0
726	* @dev_id: The device bound to the iommufd
727	* @data_len: Input the length of a user buffer in bytes. Output the length of
728	* data that kernel supports
729	* @data_uptr: User pointer to a user-space buffer used by the kernel to fill
730	* the iommu type specific hardware information data
731	* @in_data_type: This shares the same field with @out_data_type, making it be
732	* a bidirectional field. When IOMMU_HW_INFO_FLAG_INPUT_TYPE is
733	* set, an input type carried via this @in_data_type field will
734	* be valid, requesting for the info data to the given type. If
735	* IOMMU_HW_INFO_FLAG_INPUT_TYPE is unset, any input value will
736	* be seen as IOMMU_HW_INFO_TYPE_DEFAULT
737	* @out_data_type: Output the iommu hardware info type as defined in the enum
738	* iommu_hw_info_type.
739	* @out_capabilities: Output the generic iommu capability info type as defined
740	* in the enum iommu_hw_capabilities.
741	* @out_max_pasid_log2: Output the width of PASIDs. 0 means no PASID support.
742	* PCI devices turn to out_capabilities to check if the
743	* specific capabilities is supported or not.
744	* @__reserved: Must be 0
745	*
746	* Query an iommu type specific hardware information data from an iommu behind
747	* a given device that has been bound to iommufd. This hardware info data will
748	* be used to sync capabilities between the virtual iommu and the physical
749	* iommu, e.g. a nested translation setup needs to check the hardware info, so
750	* a guest stage-1 page table can be compatible with the physical iommu.
751	*
752	* To capture an iommu type specific hardware information data, @data_uptr and
753	* its length @data_len must be provided. Trailing bytes will be zeroed if the
754	* user buffer is larger than the data that kernel has. Otherwise, kernel only
755	* fills the buffer using the given length in @data_len. If the ioctl succeeds,
756	* @data_len will be updated to the length that kernel actually supports,
757	* @out_data_type will be filled to decode the data filled in the buffer
758	* pointed by @data_uptr. Input @data_len == zero is allowed.
759	*/
760	struct iommu_hw_info {
761	__u32 size;
762	__u32 flags;
763	__u32 dev_id;
764	__u32 data_len;
765	__aligned_u64 data_uptr;
766	union {
767	__u32 in_data_type;
768	__u32 out_data_type;
769	};
770	__u8 out_max_pasid_log2;
771	__u8 __reserved[3];
772	__aligned_u64 out_capabilities;
773	};
774	#define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO)
775
776	/*
777	* enum iommufd_hwpt_set_dirty_tracking_flags - Flags for steering dirty
778	* tracking
779	* @IOMMU_HWPT_DIRTY_TRACKING_ENABLE: Enable dirty tracking
780	*/
781	enum iommufd_hwpt_set_dirty_tracking_flags {
782	IOMMU_HWPT_DIRTY_TRACKING_ENABLE = 1,
783	};
784
785	/**
786	* struct iommu_hwpt_set_dirty_tracking - ioctl(IOMMU_HWPT_SET_DIRTY_TRACKING)
787	* @size: sizeof(struct iommu_hwpt_set_dirty_tracking)
788	* @flags: Combination of enum iommufd_hwpt_set_dirty_tracking_flags
789	* @hwpt_id: HW pagetable ID that represents the IOMMU domain
790	* @__reserved: Must be 0
791	*
792	* Toggle dirty tracking on an HW pagetable.
793	*/
794	struct iommu_hwpt_set_dirty_tracking {
795	__u32 size;
796	__u32 flags;
797	__u32 hwpt_id;
798	__u32 __reserved;
799	};
800	#define IOMMU_HWPT_SET_DIRTY_TRACKING _IO(IOMMUFD_TYPE, \
801	IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING)
802
803	/**
804	* enum iommufd_hwpt_get_dirty_bitmap_flags - Flags for getting dirty bits
805	* @IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR: Just read the PTEs without clearing
806	* any dirty bits metadata. This flag
807	* can be passed in the expectation
808	* where the next operation is an unmap
809	* of the same IOVA range.
810	*
811	*/
812	enum iommufd_hwpt_get_dirty_bitmap_flags {
813	IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR = 1,
814	};
815
816	/**
817	* struct iommu_hwpt_get_dirty_bitmap - ioctl(IOMMU_HWPT_GET_DIRTY_BITMAP)
818	* @size: sizeof(struct iommu_hwpt_get_dirty_bitmap)
819	* @hwpt_id: HW pagetable ID that represents the IOMMU domain
820	* @flags: Combination of enum iommufd_hwpt_get_dirty_bitmap_flags
821	* @__reserved: Must be 0
822	* @iova: base IOVA of the bitmap first bit
823	* @length: IOVA range size
824	* @page_size: page size granularity of each bit in the bitmap
825	* @data: bitmap where to set the dirty bits. The bitmap bits each
826	* represent a page_size which you deviate from an arbitrary iova.
827	*
828	* Checking a given IOVA is dirty:
829	*
830	* data[(iova / page_size) / 64] & (1ULL << ((iova / page_size) % 64))
831	*
832	* Walk the IOMMU pagetables for a given IOVA range to return a bitmap
833	* with the dirty IOVAs. In doing so it will also by default clear any
834	* dirty bit metadata set in the IOPTE.
835	*/
836	struct iommu_hwpt_get_dirty_bitmap {
837	__u32 size;
838	__u32 hwpt_id;
839	__u32 flags;
840	__u32 __reserved;
841	__aligned_u64 iova;
842	__aligned_u64 length;
843	__aligned_u64 page_size;
844	__aligned_u64 data;
845	};
846	#define IOMMU_HWPT_GET_DIRTY_BITMAP _IO(IOMMUFD_TYPE, \
847	IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP)
848
849	/**
850	* enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
851	* Data Type
852	* @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
853	* @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3
854	*/
855	enum iommu_hwpt_invalidate_data_type {
856	IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0,
857	IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1,
858	};
859
860	/**
861	* enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
862	* stage-1 cache invalidation
863	* @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
864	* to all-levels page structure cache or just
865	* the leaf PTE cache.
866	*/
867	enum iommu_hwpt_vtd_s1_invalidate_flags {
868	IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
869	};
870
871	/**
872	* struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
873	* (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
874	* @addr: The start address of the range to be invalidated. It needs to
875	* be 4KB aligned.
876	* @npages: Number of contiguous 4K pages to be invalidated.
877	* @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
878	* @__reserved: Must be 0
879	*
880	* The Intel VT-d specific invalidation data for user-managed stage-1 cache
881	* invalidation in nested translation. Userspace uses this structure to
882	* tell the impacted cache scope after modifying the stage-1 page table.
883	*
884	* Invalidating all the caches related to the page table by setting @addr
885	* to be 0 and @npages to be U64_MAX.
886	*
887	* The device TLB will be invalidated automatically if ATS is enabled.
888	*/
889	struct iommu_hwpt_vtd_s1_invalidate {
890	__aligned_u64 addr;
891	__aligned_u64 npages;
892	__u32 flags;
893	__u32 __reserved;
894	};
895
896	/**
897	* struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation
898	* (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3)
899	* @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
900	* Must be little-endian.
901	*
902	* Supported command list only when passing in a vIOMMU via @hwpt_id:
903	* CMDQ_OP_TLBI_NSNH_ALL
904	* CMDQ_OP_TLBI_NH_VA
905	* CMDQ_OP_TLBI_NH_VAA
906	* CMDQ_OP_TLBI_NH_ALL
907	* CMDQ_OP_TLBI_NH_ASID
908	* CMDQ_OP_ATC_INV
909	* CMDQ_OP_CFGI_CD
910	* CMDQ_OP_CFGI_CD_ALL
911	*
912	* -EIO will be returned if the command is not supported.
913	*/
914	struct iommu_viommu_arm_smmuv3_invalidate {
915	__aligned_le64 cmd[2];
916	};
917
918	/**
919	* struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
920	* @size: sizeof(struct iommu_hwpt_invalidate)
921	* @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation
922	* @data_uptr: User pointer to an array of driver-specific cache invalidation
923	* data.
924	* @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data
925	* type of all the entries in the invalidation request array. It
926	* should be a type supported by the hwpt pointed by @hwpt_id.
927	* @entry_len: Length (in bytes) of a request entry in the request array
928	* @entry_num: Input the number of cache invalidation requests in the array.
929	* Output the number of requests successfully handled by kernel.
930	* @__reserved: Must be 0.
931	*
932	* Invalidate iommu cache for user-managed page table or vIOMMU. Modifications
933	* on a user-managed page table should be followed by this operation, if a HWPT
934	* is passed in via @hwpt_id. Other caches, such as device cache or descriptor
935	* cache can be flushed if a vIOMMU is passed in via the @hwpt_id field.
936	*
937	* Each ioctl can support one or more cache invalidation requests in the array
938	* that has a total size of @entry_len * @entry_num.
939	*
940	* An empty invalidation request array by setting @entry_num==0 is allowed, and
941	* @entry_len and @data_uptr would be ignored in this case. This can be used to
942	* check if the given @data_type is supported or not by kernel.
943	*/
944	struct iommu_hwpt_invalidate {
945	__u32 size;
946	__u32 hwpt_id;
947	__aligned_u64 data_uptr;
948	__u32 data_type;
949	__u32 entry_len;
950	__u32 entry_num;
951	__u32 __reserved;
952	};
953	#define IOMMU_HWPT_INVALIDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_INVALIDATE)
954
955	/**
956	* enum iommu_hwpt_pgfault_flags - flags for struct iommu_hwpt_pgfault
957	* @IOMMU_PGFAULT_FLAGS_PASID_VALID: The pasid field of the fault data is
958	* valid.
959	* @IOMMU_PGFAULT_FLAGS_LAST_PAGE: It's the last fault of a fault group.
960	*/
961	enum iommu_hwpt_pgfault_flags {
962	IOMMU_PGFAULT_FLAGS_PASID_VALID = (1 << 0),
963	IOMMU_PGFAULT_FLAGS_LAST_PAGE = (1 << 1),
964	};
965
966	/**
967	* enum iommu_hwpt_pgfault_perm - perm bits for struct iommu_hwpt_pgfault
968	* @IOMMU_PGFAULT_PERM_READ: request for read permission
969	* @IOMMU_PGFAULT_PERM_WRITE: request for write permission
970	* @IOMMU_PGFAULT_PERM_EXEC: (PCIE 10.4.1) request with a PASID that has the
971	* Execute Requested bit set in PASID TLP Prefix.
972	* @IOMMU_PGFAULT_PERM_PRIV: (PCIE 10.4.1) request with a PASID that has the
973	* Privileged Mode Requested bit set in PASID TLP
974	* Prefix.
975	*/
976	enum iommu_hwpt_pgfault_perm {
977	IOMMU_PGFAULT_PERM_READ = (1 << 0),
978	IOMMU_PGFAULT_PERM_WRITE = (1 << 1),
979	IOMMU_PGFAULT_PERM_EXEC = (1 << 2),
980	IOMMU_PGFAULT_PERM_PRIV = (1 << 3),
981	};
982
983	/**
984	* struct iommu_hwpt_pgfault - iommu page fault data
985	* @flags: Combination of enum iommu_hwpt_pgfault_flags
986	* @dev_id: id of the originated device
987	* @pasid: Process Address Space ID
988	* @grpid: Page Request Group Index
989	* @perm: Combination of enum iommu_hwpt_pgfault_perm
990	* @__reserved: Must be 0.
991	* @addr: Fault address
992	* @length: a hint of how much data the requestor is expecting to fetch. For
993	* example, if the PRI initiator knows it is going to do a 10MB
994	* transfer, it could fill in 10MB and the OS could pre-fault in
995	* 10MB of IOVA. It's default to 0 if there's no such hint.
996	* @cookie: kernel-managed cookie identifying a group of fault messages. The
997	* cookie number encoded in the last page fault of the group should
998	* be echoed back in the response message.
999	*/
1000	struct iommu_hwpt_pgfault {
1001	__u32 flags;
1002	__u32 dev_id;
1003	__u32 pasid;
1004	__u32 grpid;
1005	__u32 perm;
1006	__u32 __reserved;
1007	__aligned_u64 addr;
1008	__u32 length;
1009	__u32 cookie;
1010	};
1011
1012	/**
1013	* enum iommufd_page_response_code - Return status of fault handlers
1014	* @IOMMUFD_PAGE_RESP_SUCCESS: Fault has been handled and the page tables
1015	* populated, retry the access. This is the
1016	* "Success" defined in PCI 10.4.2.1.
1017	* @IOMMUFD_PAGE_RESP_INVALID: Could not handle this fault, don't retry the
1018	* access. This is the "Invalid Request" in PCI
1019	* 10.4.2.1.
1020	*/
1021	enum iommufd_page_response_code {
1022	IOMMUFD_PAGE_RESP_SUCCESS = 0,
1023	IOMMUFD_PAGE_RESP_INVALID = 1,
1024	};
1025
1026	/**
1027	* struct iommu_hwpt_page_response - IOMMU page fault response
1028	* @cookie: The kernel-managed cookie reported in the fault message.
1029	* @code: One of response code in enum iommufd_page_response_code.
1030	*/
1031	struct iommu_hwpt_page_response {
1032	__u32 cookie;
1033	__u32 code;
1034	};
1035
1036	/**
1037	* struct iommu_fault_alloc - ioctl(IOMMU_FAULT_QUEUE_ALLOC)
1038	* @size: sizeof(struct iommu_fault_alloc)
1039	* @flags: Must be 0
1040	* @out_fault_id: The ID of the new FAULT
1041	* @out_fault_fd: The fd of the new FAULT
1042	*
1043	* Explicitly allocate a fault handling object.
1044	*/
1045	struct iommu_fault_alloc {
1046	__u32 size;
1047	__u32 flags;
1048	__u32 out_fault_id;
1049	__u32 out_fault_fd;
1050	};
1051	#define IOMMU_FAULT_QUEUE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_FAULT_QUEUE_ALLOC)
1052
1053	/**
1054	* enum iommu_viommu_type - Virtual IOMMU Type
1055	* @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use
1056	* @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type
1057	* @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM
1058	* SMMUv3) enabled ARM SMMUv3 type
1059	*/
1060	enum iommu_viommu_type {
1061	IOMMU_VIOMMU_TYPE_DEFAULT = 0,
1062	IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,
1063	/*
1064	* TEGRA241_CMDQV requirements (otherwise, VCMDQs will not work)
1065	* - Kernel will allocate a VINTF (HYP_OWN=0) to back this VIOMMU. So,
1066	* VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register
1067	*/
1068	IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2,
1069	};
1070
1071	/**
1072	* struct iommu_viommu_tegra241_cmdqv - NVIDIA Tegra241 CMDQV Virtual Interface
1073	* (IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV)
1074	* @out_vintf_mmap_offset: mmap offset argument for VINTF's page0
1075	* @out_vintf_mmap_length: mmap length argument for VINTF's page0
1076	*
1077	* Both @out_vintf_mmap_offset and @out_vintf_mmap_length are reported by kernel
1078	* for user space to mmap the VINTF page0 from the host physical address space
1079	* to the guest physical address space so that a guest kernel can directly R/W
1080	* access to the VINTF page0 in order to control its virtual command queues.
1081	*/
1082	struct iommu_viommu_tegra241_cmdqv {
1083	__aligned_u64 out_vintf_mmap_offset;
1084	__aligned_u64 out_vintf_mmap_length;
1085	};
1086
1087	/**
1088	* struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC)
1089	* @size: sizeof(struct iommu_viommu_alloc)
1090	* @flags: Must be 0
1091	* @type: Type of the virtual IOMMU. Must be defined in enum iommu_viommu_type
1092	* @dev_id: The device's physical IOMMU will be used to back the virtual IOMMU
1093	* @hwpt_id: ID of a nesting parent HWPT to associate to
1094	* @out_viommu_id: Output virtual IOMMU ID for the allocated object
1095	* @data_len: Length of the type specific data
1096	* @__reserved: Must be 0
1097	* @data_uptr: User pointer to a driver-specific virtual IOMMU data
1098	*
1099	* Allocate a virtual IOMMU object, representing the underlying physical IOMMU's
1100	* virtualization support that is a security-isolated slice of the real IOMMU HW
1101	* that is unique to a specific VM. Operations global to the IOMMU are connected
1102	* to the vIOMMU, such as:
1103	* - Security namespace for guest owned ID, e.g. guest-controlled cache tags
1104	* - Non-device-affiliated event reporting, e.g. invalidation queue errors
1105	* - Access to a sharable nesting parent pagetable across physical IOMMUs
1106	* - Virtualization of various platforms IDs, e.g. RIDs and others
1107	* - Delivery of paravirtualized invalidation
1108	* - Direct assigned invalidation queues
1109	* - Direct assigned interrupts
1110	*/
1111	struct iommu_viommu_alloc {
1112	__u32 size;
1113	__u32 flags;
1114	__u32 type;
1115	__u32 dev_id;
1116	__u32 hwpt_id;
1117	__u32 out_viommu_id;
1118	__u32 data_len;
1119	__u32 __reserved;
1120	__aligned_u64 data_uptr;
1121	};
1122	#define IOMMU_VIOMMU_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VIOMMU_ALLOC)
1123
1124	/**
1125	* struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC)
1126	* @size: sizeof(struct iommu_vdevice_alloc)
1127	* @viommu_id: vIOMMU ID to associate with the virtual device
1128	* @dev_id: The physical device to allocate a virtual instance on the vIOMMU
1129	* @out_vdevice_id: Object handle for the vDevice. Pass to IOMMU_DESTORY
1130	* @virt_id: Virtual device ID per vIOMMU, e.g. vSID of ARM SMMUv3, vDeviceID
1131	* of AMD IOMMU, and vRID of Intel VT-d
1132	*
1133	* Allocate a virtual device instance (for a physical device) against a vIOMMU.
1134	* This instance holds the device's information (related to its vIOMMU) in a VM.
1135	* User should use IOMMU_DESTROY to destroy the virtual device before
1136	* destroying the physical device (by closing vfio_cdev fd). Otherwise the
1137	* virtual device would be forcibly destroyed on physical device destruction,
1138	* its vdevice_id would be permanently leaked (unremovable & unreusable) until
1139	* iommu fd closed.
1140	*/
1141	struct iommu_vdevice_alloc {
1142	__u32 size;
1143	__u32 viommu_id;
1144	__u32 dev_id;
1145	__u32 out_vdevice_id;
1146	__aligned_u64 virt_id;
1147	};
1148	#define IOMMU_VDEVICE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VDEVICE_ALLOC)
1149
1150	/**
1151	* struct iommu_ioas_change_process - ioctl(VFIO_IOAS_CHANGE_PROCESS)
1152	* @size: sizeof(struct iommu_ioas_change_process)
1153	* @__reserved: Must be 0
1154	*
1155	* This transfers pinned memory counts for every memory map in every IOAS
1156	* in the context to the current process. This only supports maps created
1157	* with IOMMU_IOAS_MAP_FILE, and returns EINVAL if other maps are present.
1158	* If the ioctl returns a failure status, then nothing is changed.
1159	*
1160	* This API is useful for transferring operation of a device from one process
1161	* to another, such as during userland live update.
1162	*/
1163	struct iommu_ioas_change_process {
1164	__u32 size;
1165	__u32 __reserved;
1166	};
1167
1168	#define IOMMU_IOAS_CHANGE_PROCESS \
1169	_IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_CHANGE_PROCESS)
1170
1171	/**
1172	* enum iommu_veventq_flag - flag for struct iommufd_vevent_header
1173	* @IOMMU_VEVENTQ_FLAG_LOST_EVENTS: vEVENTQ has lost vEVENTs
1174	*/
1175	enum iommu_veventq_flag {
1176	IOMMU_VEVENTQ_FLAG_LOST_EVENTS = (1U << 0),
1177	};
1178
1179	/**
1180	* struct iommufd_vevent_header - Virtual Event Header for a vEVENTQ Status
1181	* @flags: Combination of enum iommu_veventq_flag
1182	* @sequence: The sequence index of a vEVENT in the vEVENTQ, with a range of
1183	* [0, INT_MAX] where the following index of INT_MAX is 0
1184	*
1185	* Each iommufd_vevent_header reports a sequence index of the following vEVENT:
1186	*
1187	* +----------------------+-------+----------------------+-------+---+-------+
1188	* | header0 {sequence=0} | data0 | header1 {sequence=1} | data1 |...| dataN |
1189	* +----------------------+-------+----------------------+-------+---+-------+
1190	*
1191	* And this sequence index is expected to be monotonic to the sequence index of
1192	* the previous vEVENT. If two adjacent sequence indexes has a delta larger than
1193	* 1, it means that delta - 1 number of vEVENTs has lost, e.g. two lost vEVENTs:
1194	*
1195	* +-----+----------------------+-------+----------------------+-------+-----+
1196	* | ... | header3 {sequence=3} | data3 | header6 {sequence=6} | data6 | ... |
1197	* +-----+----------------------+-------+----------------------+-------+-----+
1198	*
1199	* If a vEVENT lost at the tail of the vEVENTQ and there is no following vEVENT
1200	* providing the next sequence index, an IOMMU_VEVENTQ_FLAG_LOST_EVENTS header
1201	* would be added to the tail, and no data would follow this header:
1202	*
1203	* +--+----------------------+-------+-----------------------------------------+
1204	* |..| header3 {sequence=3} | data3 | header4 {flags=LOST_EVENTS, sequence=4} |
1205	* +--+----------------------+-------+-----------------------------------------+
1206	*/
1207	struct iommufd_vevent_header {
1208	__u32 flags;
1209	__u32 sequence;
1210	};
1211
1212	/**
1213	* enum iommu_veventq_type - Virtual Event Queue Type
1214	* @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use
1215	* @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue
1216	* @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ
1217	*/
1218	enum iommu_veventq_type {
1219	IOMMU_VEVENTQ_TYPE_DEFAULT = 0,
1220	IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1,
1221	IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2,
1222	};
1223
1224	/**
1225	* struct iommu_vevent_arm_smmuv3 - ARM SMMUv3 Virtual Event
1226	* (IOMMU_VEVENTQ_TYPE_ARM_SMMUV3)
1227	* @evt: 256-bit ARM SMMUv3 Event record, little-endian.
1228	* Reported event records: (Refer to "7.3 Event records" in SMMUv3 HW Spec)
1229	* - 0x04 C_BAD_STE
1230	* - 0x06 F_STREAM_DISABLED
1231	* - 0x08 C_BAD_SUBSTREAMID
1232	* - 0x0a C_BAD_CD
1233	* - 0x10 F_TRANSLATION
1234	* - 0x11 F_ADDR_SIZE
1235	* - 0x12 F_ACCESS
1236	* - 0x13 F_PERMISSION
1237	*
1238	* StreamID field reports a virtual device ID. To receive a virtual event for a
1239	* device, a vDEVICE must be allocated via IOMMU_VDEVICE_ALLOC.
1240	*/
1241	struct iommu_vevent_arm_smmuv3 {
1242	__aligned_le64 evt[4];
1243	};
1244
1245	/**
1246	* struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ
1247	* (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV)
1248	* @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian.
1249	* (Refer to register LVCMDQ_ERR_MAPs per VINTF )
1250	*
1251	* The 128-bit register value from HW exclusively reflect the error bits for a
1252	* Virtual Interface represented by a vIOMMU object. Read and report directly.
1253	*/
1254	struct iommu_vevent_tegra241_cmdqv {
1255	__aligned_le64 lvcmdq_err_map[2];
1256	};
1257
1258	/**
1259	* struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC)
1260	* @size: sizeof(struct iommu_veventq_alloc)
1261	* @flags: Must be 0
1262	* @viommu_id: virtual IOMMU ID to associate the vEVENTQ with
1263	* @type: Type of the vEVENTQ. Must be defined in enum iommu_veventq_type
1264	* @veventq_depth: Maximum number of events in the vEVENTQ
1265	* @out_veventq_id: The ID of the new vEVENTQ
1266	* @out_veventq_fd: The fd of the new vEVENTQ. User space must close the
1267	* successfully returned fd after using it
1268	* @__reserved: Must be 0
1269	*
1270	* Explicitly allocate a virtual event queue interface for a vIOMMU. A vIOMMU
1271	* can have multiple FDs for different types, but is confined to one per @type.
1272	* User space should open the @out_veventq_fd to read vEVENTs out of a vEVENTQ,
1273	* if there are vEVENTs available. A vEVENTQ will lose events due to overflow,
1274	* if the number of the vEVENTs hits @veventq_depth.
1275	*
1276	* Each vEVENT in a vEVENTQ encloses a struct iommufd_vevent_header followed by
1277	* a type-specific data structure, in a normal case:
1278	*
1279	* +-+---------+-------+---------+-------+-----+---------+-------+-+
1280	* | | header0 | data0 | header1 | data1 | ... | headerN | dataN | |
1281	* +-+---------+-------+---------+-------+-----+---------+-------+-+
1282	*
1283	* unless a tailing IOMMU_VEVENTQ_FLAG_LOST_EVENTS header is logged (refer to
1284	* struct iommufd_vevent_header).
1285	*/
1286	struct iommu_veventq_alloc {
1287	__u32 size;
1288	__u32 flags;
1289	__u32 viommu_id;
1290	__u32 type;
1291	__u32 veventq_depth;
1292	__u32 out_veventq_id;
1293	__u32 out_veventq_fd;
1294	__u32 __reserved;
1295	};
1296	#define IOMMU_VEVENTQ_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VEVENTQ_ALLOC)
1297
1298	/**
1299	* enum iommu_hw_queue_type - HW Queue Type
1300	* @IOMMU_HW_QUEUE_TYPE_DEFAULT: Reserved for future use
1301	* @IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM
1302	* SMMUv3) Virtual Command Queue (VCMDQ)
1303	*/
1304	enum iommu_hw_queue_type {
1305	IOMMU_HW_QUEUE_TYPE_DEFAULT = 0,
1306	/*
1307	* TEGRA241_CMDQV requirements (otherwise, allocation will fail)
1308	* - alloc starts from the lowest @index=0 in ascending order
1309	* - destroy starts from the last allocated @index in descending order
1310	* - @base_addr must be aligned to @length in bytes and mapped in IOAS
1311	* - @length must be a power of 2, with a minimum 32 bytes and a maximum
1312	* 2 ^ idr[1].CMDQS * 16 bytes (use GET_HW_INFO call to read idr[1]
1313	* from struct iommu_hw_info_arm_smmuv3)
1314	* - suggest to back the queue memory with contiguous physical pages or
1315	* a single huge page with alignment of the queue size, and limit the
1316	* emulated vSMMU's IDR1.CMDQS to log2(huge page size / 16 bytes)
1317	*/
1318	IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV = 1,
1319	};
1320
1321	/**
1322	* struct iommu_hw_queue_alloc - ioctl(IOMMU_HW_QUEUE_ALLOC)
1323	* @size: sizeof(struct iommu_hw_queue_alloc)
1324	* @flags: Must be 0
1325	* @viommu_id: Virtual IOMMU ID to associate the HW queue with
1326	* @type: One of enum iommu_hw_queue_type
1327	* @index: The logical index to the HW queue per virtual IOMMU for a multi-queue
1328	* model
1329	* @out_hw_queue_id: The ID of the new HW queue
1330	* @nesting_parent_iova: Base address of the queue memory in the guest physical
1331	* address space
1332	* @length: Length of the queue memory
1333	*
1334	* Allocate a HW queue object for a vIOMMU-specific HW-accelerated queue, which
1335	* allows HW to access a guest queue memory described using @nesting_parent_iova
1336	* and @length.
1337	*
1338	* A vIOMMU can allocate multiple queues, but it must use a different @index per
1339	* type to separate each allocation, e.g::
1340	*
1341	* Type1 HW queue0, Type1 HW queue1, Type2 HW queue0, ...
1342	*/
1343	struct iommu_hw_queue_alloc {
1344	__u32 size;
1345	__u32 flags;
1346	__u32 viommu_id;
1347	__u32 type;
1348	__u32 index;
1349	__u32 out_hw_queue_id;
1350	__aligned_u64 nesting_parent_iova;
1351	__aligned_u64 length;
1352	};
1353	#define IOMMU_HW_QUEUE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HW_QUEUE_ALLOC)
1354	#endif