1/* $OpenBSD: cpufunc.h,v 1.34 2023/05/30 08:30:00 jsg Exp $ */
2/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
3
4/*
5 * Copyright (c) 1997 Mark Brinicombe.
6 * Copyright (c) 1997 Causality Limited
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Causality Limited.
20 * 4. The name of Causality Limited may not be used to endorse or promote
21 * products derived from this software without specific prior written
22 * permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * RiscBSD kernel project
37 *
38 * cpufunc.h
39 *
40 * Prototypes for cpu, mmu and tlb related functions.
41 */
42
43#ifndef _ARM_CPUFUNC_H_
44#define _ARM_CPUFUNC_H_
45
46#ifdef _KERNEL
47
48#include <sys/types.h>
49#include <arm/cpuconf.h>
50
51struct cpu_functions {
52
53 /* CPU functions */
54
55 u_int (*cf_id) (void);
56 void (*cf_cpwait) (void);
57
58 /* MMU functions */
59
60 u_int (*cf_control) (u_int clear, u_int set);
61 u_int (*cf_auxcontrol) (u_int clear, u_int set);
62 void (*cf_domains) (u_int domains);
63 void (*cf_setttb) (u_int ttb);
64 u_int (*cf_dfsr) (void);
65 u_int (*cf_dfar) (void);
66 u_int (*cf_ifsr) (void);
67 u_int (*cf_ifar) (void);
68
69 /* TLB functions */
70
71 void (*cf_tlb_flushID) (void);
72 void (*cf_tlb_flushID_SE) (u_int va);
73 void (*cf_tlb_flushI) (void);
74 void (*cf_tlb_flushI_SE) (u_int va);
75 void (*cf_tlb_flushD) (void);
76 void (*cf_tlb_flushD_SE) (u_int va);
77
78 /*
79 * Cache operations:
80 *
81 * We define the following primitives:
82 *
83 * icache_sync_all Synchronize I-cache
84 * icache_sync_range Synchronize I-cache range
85 *
86 * dcache_wbinv_all Write-back and Invalidate D-cache
87 * dcache_wbinv_range Write-back and Invalidate D-cache range
88 * dcache_inv_range Invalidate D-cache range
89 * dcache_wb_range Write-back D-cache range
90 *
91 * idcache_wbinv_all Write-back and Invalidate D-cache,
92 * Invalidate I-cache
93 * idcache_wbinv_range Write-back and Invalidate D-cache,
94 * Invalidate I-cache range
95 *
96 * Note that the ARM term for "write-back" is "clean". We use
97 * the term "write-back" since it's a more common way to describe
98 * the operation.
99 *
100 * There are some rules that must be followed:
101 *
102 * I-cache Synch (all or range):
103 * The goal is to synchronize the instruction stream,
104 * so you may need to write-back dirty D-cache blocks
105 * first. If a range is requested, and you can't
106 * synchronize just a range, you have to hit the whole
107 * thing.
108 *
109 * D-cache Write-Back and Invalidate range:
110 * If you can't WB-Inv a range, you must WB-Inv the
111 * entire D-cache.
112 *
113 * D-cache Invalidate:
114 * If you can't Inv the D-cache, you must Write-Back
115 * and Invalidate. Code that uses this operation
116 * MUST NOT assume that the D-cache will not be written
117 * back to memory.
118 *
119 * D-cache Write-Back:
120 * If you can't Write-back without doing an Inv,
121 * that's fine. Then treat this as a WB-Inv.
122 * Skipping the invalidate is merely an optimization.
123 *
124 * All operations:
125 * Valid virtual addresses must be passed to each
126 * cache operation.
127 */
128 void (*cf_icache_sync_all) (void);
129 void (*cf_icache_sync_range) (vaddr_t, vsize_t);
130
131 void (*cf_dcache_wbinv_all) (void);
132 void (*cf_dcache_wbinv_range) (vaddr_t, vsize_t);
133 void (*cf_dcache_inv_range) (vaddr_t, vsize_t);
134 void (*cf_dcache_wb_range) (vaddr_t, vsize_t);
135
136 void (*cf_idcache_wbinv_all) (void);
137 void (*cf_idcache_wbinv_range) (vaddr_t, vsize_t);
138
139 void (*cf_sdcache_wbinv_all) (void);
140 void (*cf_sdcache_wbinv_range) (vaddr_t, paddr_t, vsize_t);
141 void (*cf_sdcache_inv_range) (vaddr_t, paddr_t, vsize_t);
142 void (*cf_sdcache_wb_range) (vaddr_t, paddr_t, vsize_t);
143 void (*cf_sdcache_drain_writebuf) (void);
144
145 /* Other functions */
146
147 void (*cf_flush_prefetchbuf) (void);
148 void (*cf_drain_writebuf) (void);
149
150 void (*cf_sleep) (int mode);
151
152 /* Soft functions */
153 void (*cf_context_switch) (u_int);
154 void (*cf_setup) (void);
155};
156
157extern struct cpu_functions cpufuncs;
158extern u_int cputype;
159
160#define cpu_id() cpufuncs.cf_id()
161#define cpu_cpwait() cpufuncs.cf_cpwait()
162
163#define cpu_control(c, s) cpufuncs.cf_control(c, s)
164#define cpu_auxcontrol(c, s) cpufuncs.cf_auxcontrol(c, s)
165#define cpu_domains(d) cpufuncs.cf_domains(d)
166#define cpu_setttb(t) cpufuncs.cf_setttb(t)
167#define cpu_dfsr() cpufuncs.cf_dfsr()
168#define cpu_dfar() cpufuncs.cf_dfar()
169#define cpu_ifsr() cpufuncs.cf_ifsr()
170#define cpu_ifar() cpufuncs.cf_ifar()
171
172#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
173#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
174#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
175#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
176#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
177#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
178
179#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
180#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
181
182#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
183#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
184#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
185#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
186
187#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
188#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
189
190#define cpu_sdcache_enabled() (cpufuncs.cf_sdcache_wbinv_all != cpufunc_nullop)
191#define cpu_sdcache_wbinv_all() cpufuncs.cf_sdcache_wbinv_all()
192#define cpu_sdcache_wbinv_range(va, pa, s) cpufuncs.cf_sdcache_wbinv_range((va), (pa), (s))
193#define cpu_sdcache_inv_range(va, pa, s) cpufuncs.cf_sdcache_inv_range((va), (pa), (s))
194#define cpu_sdcache_wb_range(va, pa, s) cpufuncs.cf_sdcache_wb_range((va), (pa), (s))
195#define cpu_sdcache_drain_writebuf() cpufuncs.cf_sdcache_drain_writebuf()
196
197#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
198#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
199
200#define cpu_sleep(m) cpufuncs.cf_sleep(m)
201
202#define cpu_context_switch(a) cpufuncs.cf_context_switch(a)
203#define cpu_setup(a) cpufuncs.cf_setup(a)
204
205int set_cpufuncs (void);
206#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
207#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
208
209void cpufunc_nullop (void);
210int early_abort_fixup (void *);
211int late_abort_fixup (void *);
212u_int cpufunc_id (void);
213u_int cpufunc_control (u_int clear, u_int set);
214u_int cpufunc_auxcontrol (u_int clear, u_int set);
215void cpufunc_domains (u_int domains);
216u_int cpufunc_dfsr (void);
217u_int cpufunc_dfar (void);
218u_int cpufunc_ifsr (void);
219u_int cpufunc_ifar (void);
220
221void armv7_setttb (u_int);
222
223void armv7_tlb_flushID_SE (u_int);
224void armv7_tlb_flushI_SE (u_int);
225
226void armv7_context_switch (u_int);
227
228void armv7_setup (void);
229void armv7_tlb_flushID (void);
230void armv7_tlb_flushI (void);
231void armv7_tlb_flushD (void);
232void armv7_tlb_flushD_SE (u_int va);
233
234void armv7_flush_bp(void);
235void cortex_a15_flush_bp(void);
236
237void armv7_drain_writebuf (void);
238void armv7_cpu_sleep (int mode);
239
240u_int armv7_periphbase (void);
241
242void armv7_icache_sync_all (void);
243void armv7_icache_sync_range (vaddr_t, vsize_t);
244
245void armv7_dcache_wbinv_all (void);
246void armv7_dcache_wbinv_range (vaddr_t, vsize_t);
247void armv7_dcache_inv_range (vaddr_t, vsize_t);
248void armv7_dcache_wb_range (vaddr_t, vsize_t);
249
250void armv7_idcache_wbinv_all (void);
251void armv7_idcache_wbinv_range (vaddr_t, vsize_t);
252
253extern unsigned armv7_dcache_sets_max;
254extern unsigned armv7_dcache_sets_inc;
255extern unsigned armv7_dcache_index_max;
256extern unsigned armv7_dcache_index_inc;
257
258#define tlb_flush cpu_tlb_flushID
259#define setttb cpu_setttb
260#define drain_writebuf cpu_drain_writebuf
261
262/*
263 * Macros for manipulating CPU interrupts
264 */
265/* Functions to manipulate the CPSR. */
266static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor);
267static __inline u_int32_t __get_cpsr(void);
268
269static __inline u_int32_t
270__set_cpsr_c(u_int bic, u_int eor)
271{
272 u_int32_t tmp, ret;
273
274 __asm volatile(
275 "mrs %0, cpsr\n\t" /* Get the CPSR */
276 "bic %1, %0, %2\n\t" /* Clear bits */
277 "eor %1, %1, %3\n\t" /* XOR bits */
278 "msr cpsr_c, %1" /* Set CPSR control field */
279 : "=&r" (ret), "=&r" (tmp)
280 : "r" (bic), "r" (eor));
281
282 return ret;
283}
284
285static __inline u_int32_t
286__get_cpsr(void)
287{
288 u_int32_t ret;
289
290 __asm volatile("mrs %0, cpsr" : "=&r" (ret));
291
292 return ret;
293}
294
295#define disable_interrupts(mask) \
296 (__set_cpsr_c((mask) & (PSR_I | PSR_F), \
297 (mask) & (PSR_I | PSR_F)))
298
299#define enable_interrupts(mask) \
300 (__set_cpsr_c((mask) & (PSR_I | PSR_F), 0))
301
302#define restore_interrupts(old_cpsr) \
303 (__set_cpsr_c((PSR_I | PSR_F), (old_cpsr) & (PSR_I | PSR_F)))
304
305/*
306 * Functions to manipulate cpu r13
307 * (in arm/arm/setstack.S)
308 */
309
310void set_stackptr (u_int mode, u_int address);
311u_int get_stackptr (u_int mode);
312
313/*
314 * CPU functions from locore.S
315 */
316
317void cpu_reset (void) __attribute__((__noreturn__));
318
319/*
320 * Cache info variables.
321 */
322
323/* PRIMARY CACHE VARIABLES */
324extern int arm_picache_size;
325extern int arm_picache_line_size;
326extern int arm_picache_ways;
327
328extern int arm_pdcache_size; /* and unified */
329extern int arm_pdcache_line_size;
330extern int arm_pdcache_ways;
331
332extern int arm_pcache_type;
333extern int arm_pcache_unified;
334
335extern int arm_dcache_align;
336extern int arm_dcache_align_mask;
337
338#endif /* _KERNEL */
339#endif /* _ARM_CPUFUNC_H_ */