1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2003 Hidetoshi Shimokawa
5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the acknowledgement as bellow:
18 *
19 * This product includes software developed by K. Kobayashi and H. Shimokawa
20 *
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 */
37
38#ifndef _FIREWIRE_H
39#define _FIREWIRE_H 1
40
41#define DEV_DEF 0
42#define DEV_DV 2
43
44struct fw_isochreq {
45 unsigned char ch:6;
46 unsigned char tag:2;
47};
48
49struct fw_isobufreq {
50 struct fw_bufspec {
51 unsigned int nchunk;
52 unsigned int npacket;
53 unsigned int psize;
54 } tx, rx;
55};
56
57struct fw_addr {
58 uint32_t hi;
59 uint32_t lo;
60};
61
62struct fw_asybindreq {
63 struct fw_addr start;
64 unsigned long len;
65};
66
67struct fw_reg_req_t {
68 uint32_t addr;
69 uint32_t data;
70};
71
72#define MAXREC(x) (2 << (x))
73#define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */
74#define FWMAXQUEUE 128
75
76#define FWLOCALBUS 0xffc0
77
78#define FWTCODE_WREQQ 0
79#define FWTCODE_WREQB 1
80#define FWTCODE_WRES 2
81#define FWTCODE_RREQQ 4
82#define FWTCODE_RREQB 5
83#define FWTCODE_RRESQ 6
84#define FWTCODE_RRESB 7
85#define FWTCODE_CYCS 8
86#define FWTCODE_LREQ 9
87#define FWTCODE_STREAM 0xa
88#define FWTCODE_LRES 0xb
89#define FWTCODE_PHY 0xe
90
91#define FWRETRY_1 0
92#define FWRETRY_X 1
93#define FWRETRY_A 2
94#define FWRETRY_B 3
95
96#define FWRCODE_COMPLETE 0
97#define FWRCODE_ER_CONFL 4
98#define FWRCODE_ER_DATA 5
99#define FWRCODE_ER_TYPE 6
100#define FWRCODE_ER_ADDR 7
101
102/*
103 * Defined 1394a-2000
104 * Table 5B-1
105 */
106#define FWSPD_S100 0
107#define FWSPD_S200 1
108#define FWSPD_S400 2
109#define FWSPD_S800 3
110#define FWSPD_S1600 4
111#define FWSPD_S3200 5
112
113#define FWP_TL_VALID (1 << 7)
114
115struct fw_isohdr {
116 uint32_t hdr[1];
117};
118
119struct fw_asyhdr {
120 uint32_t hdr[4];
121};
122
123#if BYTE_ORDER == BIG_ENDIAN
124#define BIT4x2(x,y) uint8_t x:4, y:4
125#define BIT16x2(x,y) uint32_t x:16, y:16
126#else
127#define BIT4x2(x,y) uint8_t y:4, x:4
128#define BIT16x2(x,y) uint32_t y:16, x:16
129#endif
130
131
132#if BYTE_ORDER == BIG_ENDIAN
133#define COMMON_HDR(a,b,c,d) uint32_t a:16,b:8,c:4,d:4
134#define COMMON_RES(a,b,c,d) uint32_t a:16,b:4,c:4,d:8
135#else
136#define COMMON_HDR(a,b,c,d) uint32_t d:4,c:4,b:8,a:16
137#define COMMON_RES(a,b,c,d) uint32_t d:8,c:4,b:4,a:16
138#endif
139
140struct fw_pkt {
141 union {
142 uint32_t ld[0];
143 struct {
144 COMMON_HDR(, , tcode, );
145 } common;
146 struct {
147 COMMON_HDR(len, chtag, tcode, sy);
148 uint32_t payload[0];
149 } stream;
150 struct {
151 COMMON_HDR(dst, tlrt, tcode, pri);
152 BIT16x2(src, );
153 } hdr;
154 struct {
155 COMMON_HDR(dst, tlrt, tcode, pri);
156 BIT16x2(src, dest_hi);
157 uint32_t dest_lo;
158 } rreqq;
159 struct {
160 COMMON_HDR(dst, tlrt, tcode, pri);
161 COMMON_RES(src, rtcode, , );
162 uint32_t :32;
163 } wres;
164 struct {
165 COMMON_HDR(dst, tlrt, tcode, pri);
166 BIT16x2(src, dest_hi);
167 uint32_t dest_lo;
168 BIT16x2(len, extcode);
169 } rreqb;
170 struct {
171 COMMON_HDR(dst, tlrt, tcode, pri);
172 BIT16x2(src, dest_hi);
173 uint32_t dest_lo;
174 uint32_t data;
175 } wreqq;
176 struct {
177 COMMON_HDR(dst, tlrt, tcode, pri);
178 BIT16x2(src, dest_hi);
179 uint32_t dest_lo;
180 uint32_t data;
181 } cyc;
182 struct {
183 COMMON_HDR(dst, tlrt, tcode, pri);
184 COMMON_RES(src, rtcode, , );
185 uint32_t :32;
186 uint32_t data;
187 } rresq;
188 struct {
189 COMMON_HDR(dst, tlrt, tcode, pri);
190 BIT16x2(src, dest_hi);
191 uint32_t dest_lo;
192 BIT16x2(len, extcode);
193 uint32_t payload[0];
194 } wreqb;
195 struct {
196 COMMON_HDR(dst, tlrt, tcode, pri);
197 BIT16x2(src, dest_hi);
198 uint32_t dest_lo;
199 BIT16x2(len, extcode);
200 uint32_t payload[0];
201 } lreq;
202 struct {
203 COMMON_HDR(dst, tlrt, tcode, pri);
204 COMMON_RES(src, rtcode, , );
205 uint32_t :32;
206 BIT16x2(len, extcode);
207 uint32_t payload[0];
208 } rresb;
209 struct {
210 COMMON_HDR(dst, tlrt, tcode, pri);
211 COMMON_RES(src, rtcode, , );
212 uint32_t :32;
213 BIT16x2(len, extcode);
214 uint32_t payload[0];
215 } lres;
216 } mode;
217};
218
219/*
220 * Response code (rtcode)
221 */
222/* The node has successfully completed the command. */
223#define RESP_CMP 0
224/* A resource conflict was detected. The request may be retried. */
225#define RESP_CONFLICT_ERROR 4
226/* Hardware error, data is unavailable. */
227#define RESP_DATA_ERROR 5
228/* A field in the request packet header was set to an unsupported or incorrect
229 * value, or an invalid transaction was attempted (e.g., a write to a read-only
230 * address). */
231#define RESP_TYPE_ERROR 6
232/* The destination offset field in the request was set to an address not
233 * accessible in the destination node. */
234#define RESP_ADDRESS_ERROR 7
235
236/*
237 * Extended transaction code (extcode)
238 */
239#define EXTCODE_MASK_SWAP 1
240#define EXTCODE_CMP_SWAP 2
241#define EXTCODE_FETCH_ADD 3
242#define EXTCODE_LITTLE_ADD 4
243#define EXTCODE_BOUNDED_ADD 5
244#define EXTCODE_WRAP_ADD 6
245
246struct fw_eui64 {
247 uint32_t hi, lo;
248};
249#define FW_EUI64_BYTE(eui, x) \
250 ((((x) < 4)? \
251 ((eui)->hi >> (8 * (3 - (x)))): \
252 ((eui)->lo >> (8 * (7 - (x)))) \
253 ) & 0xff)
254#define FW_EUI64_EQUAL(x, y) \
255 ((x).hi == (y).hi && (x).lo == (y).lo)
256
257struct fw_asyreq {
258 struct fw_asyreq_t {
259 unsigned char sped;
260 unsigned int type;
261#define FWASREQNODE 0
262#define FWASREQEUI 1
263#define FWASRESTL 2
264#define FWASREQSTREAM 3
265 unsigned short len;
266 union {
267 struct fw_eui64 eui;
268 } dst;
269 } req;
270 struct fw_pkt pkt;
271 uint32_t data[512];
272};
273
274struct fw_devinfo {
275 struct fw_eui64 eui;
276 uint16_t dst;
277 uint16_t status;
278};
279
280#define FW_MAX_DEVLST 70
281struct fw_devlstreq {
282 uint16_t n;
283 uint16_t info_len;
284 struct fw_devinfo dev[FW_MAX_DEVLST];
285};
286
287/*
288 * Defined in IEEE 1394a-2000
289 * 4.3.4.1
290 */
291#define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
292#define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
293#define FW_SELF_ID_PORT_NOT_CONNECTED 1
294#define FW_SELF_ID_PORT_NOT_EXISTS 0
295
296#define FW_SELF_ID_PAGE0 0
297#define FW_SELF_ID_PAGE1 1
298
299#if BYTE_ORDER == BIG_ENDIAN
300union fw_self_id {
301 struct {
302 uint32_t id:2,
303 phy_id:6,
304 sequel:1,
305 link_active:1,
306 gap_count:6,
307 phy_speed:2,
308 reserved:2,
309 contender:1,
310 power_class:3,
311 port0:2,
312 port1:2,
313 port2:2,
314 initiated_reset:1,
315 more_packets:1;
316 } p0;
317 struct {
318 uint32_t
319 id:2,
320 phy_id:6,
321 sequel:1,
322 sequence_num:3,
323 reserved2:2,
324 port3:2,
325 port4:2,
326 port5:2,
327 port6:2,
328 port7:2,
329 port8:2,
330 port9:2,
331 port10:2,
332 reserved1:1,
333 more_packets:1;
334 } p1;
335 struct {
336 uint32_t
337 id:2,
338 phy_id:6,
339 sequel:1,
340 sequence_num:3,
341 :2,
342 port11:2,
343 port12:2,
344 port13:2,
345 port14:2,
346 port15:2,
347 :8;
348 } p2;
349};
350#else
351union fw_self_id {
352 struct {
353 uint32_t more_packets:1,
354 initiated_reset:1,
355 port2:2,
356 port1:2,
357 port0:2,
358 power_class:3,
359 contender:1,
360 reserved:2,
361 phy_speed:2,
362 gap_count:6,
363 link_active:1,
364 sequel:1,
365 phy_id:6,
366 id:2;
367 } p0;
368 struct {
369 uint32_t more_packets:1,
370 reserved1:1,
371 port10:2,
372 port9:2,
373 port8:2,
374 port7:2,
375 port6:2,
376 port5:2,
377 port4:2,
378 port3:2,
379 reserved2:2,
380 sequence_num:3,
381 sequel:1,
382 phy_id:6,
383 id:2;
384 } p1;
385 struct {
386 uint32_t
387 reserved3:8,
388 port15:2,
389 port14:2,
390 port13:2,
391 port12:2,
392 port11:2,
393 reserved4:2,
394 sequence_num:3,
395 sequel:1,
396 phy_id:6,
397 id:2;
398 } p2;
399};
400#endif
401
402
403struct fw_topology_map {
404 uint32_t crc:16,
405 crc_len:16;
406 uint32_t generation;
407 uint32_t self_id_count:16,
408 node_count:16;
409 union fw_self_id self_id[4 * 64];
410};
411
412struct fw_speed_map {
413 uint32_t crc:16,
414 crc_len:16;
415 uint32_t generation;
416 uint8_t speed[64][64];
417};
418
419struct fw_crom_buf {
420 struct fw_eui64 eui;
421 uint32_t len;
422 void *ptr;
423};
424
425/*
426 * FireWire specific system requests.
427 */
428#define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq)
429#define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq)
430#define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq)
431#define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq)
432#define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq)
433#define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq)
434
435#define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq)
436#define FW_IBUSRST _IOR('S', 1, unsigned int)
437#define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq)
438#define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq)
439#define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq)
440#define FW_GTPMAP _IOR('S', 5, struct fw_topology_map)
441#define FW_GCROM _IOWR('S', 7, struct fw_crom_buf)
442
443#define FW_SDEUI64 _IOW('S', 20, struct fw_eui64)
444#define FW_GDEUI64 _IOR('S', 21, struct fw_eui64)
445
446#define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t)
447#define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t)
448#define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t)
449#define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t)
450
451#define DUMPDMA _IOWR('S', 82, uint32_t)
452
453#ifdef _KERNEL
454
455#define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
456
457#define MAKEMINOR(f, u, s) \
458 ((f) | (((u) & 0xff) << 8) | (s & 0xff))
459#define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8)
460#define DEV2SUB(x) (dev2unit(x) & 0xff)
461
462#define FWMEM_FLAG 0x10000
463#define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG)
464#endif
465#endif