1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2003 Hidetoshi Shimokawa
5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the acknowledgement as bellow:
18 *
19 * This product includes software developed by K. Kobayashi and H. Shimokawa
20 *
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 *
37 */
38#define PCI_CBMEM PCIR_BAR(0)
39
40#define FW_VENDORID_NATSEMI 0x100B
41#define FW_VENDORID_NEC 0x1033
42#define FW_VENDORID_SIS 0x1039
43#define FW_VENDORID_TI 0x104c
44#define FW_VENDORID_SONY 0x104d
45#define FW_VENDORID_VIA 0x1106
46#define FW_VENDORID_RICOH 0x1180
47#define FW_VENDORID_APPLE 0x106b
48#define FW_VENDORID_LUCENT 0x11c1
49#define FW_VENDORID_INTEL 0x8086
50#define FW_VENDORID_ADAPTEC 0x9004
51
52#define FW_DEVICE_CS4210 (0x000f << 16)
53#define FW_DEVICE_UPD861 (0x0063 << 16)
54#define FW_DEVICE_UPD871 (0x00ce << 16)
55#define FW_DEVICE_UPD72870 (0x00cd << 16)
56#define FW_DEVICE_UPD72873 (0x00e7 << 16)
57#define FW_DEVICE_UPD72874 (0x00f2 << 16)
58#define FW_DEVICE_TITSB22 (0x8009 << 16)
59#define FW_DEVICE_TITSB23 (0x8019 << 16)
60#define FW_DEVICE_TITSB26 (0x8020 << 16)
61#define FW_DEVICE_TITSB43 (0x8021 << 16)
62#define FW_DEVICE_TITSB43A (0x8023 << 16)
63#define FW_DEVICE_TITSB43AB23 (0x8024 << 16)
64#define FW_DEVICE_TITSB82AA2 (0x8025 << 16)
65#define FW_DEVICE_TITSB43AB21 (0x8026 << 16)
66#define FW_DEVICE_TIPCI4410A (0x8017 << 16)
67#define FW_DEVICE_TIPCI4450 (0x8011 << 16)
68#define FW_DEVICE_TIPCI4451 (0x8027 << 16)
69#define FW_DEVICE_CXD1947 (0x8009 << 16)
70#define FW_DEVICE_CXD3222 (0x8039 << 16)
71#define FW_DEVICE_VT6306 (0x3044 << 16)
72#define FW_DEVICE_R5C551 (0x0551 << 16)
73#define FW_DEVICE_R5C552 (0x0552 << 16)
74#define FW_DEVICE_PANGEA (0x0030 << 16)
75#define FW_DEVICE_UNINORTH2 (0x0031 << 16)
76#define FW_DEVICE_AIC5800 (0x5800 << 16)
77#define FW_DEVICE_FW322 (0x5811 << 16)
78#define FW_DEVICE_7007 (0x7007 << 16)
79#define FW_DEVICE_82372FB (0x7605 << 16)
80
81#define PCI_INTERFACE_OHCI 0x10
82
83#define FW_OHCI_BASE_REG 0x10
84
85#define OHCI_DMA_ITCH 0x20
86#define OHCI_DMA_IRCH 0x20
87
88#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
89
90
91typedef uint32_t fwohcireg_t;
92
93/* for PCI */
94#if BYTE_ORDER == BIG_ENDIAN
95#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y))
96#define FWOHCI_DMA_READ(x) le32toh(x)
97#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y))
98#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y)))
99#else
100#define FWOHCI_DMA_WRITE(x, y) ((x) = (y))
101#define FWOHCI_DMA_READ(x) (x)
102#define FWOHCI_DMA_SET(x, y) ((x) |= (y))
103#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y))
104#endif
105
106struct fwohcidb {
107 union {
108 struct {
109 uint32_t cmd;
110 uint32_t addr;
111 uint32_t depend;
112 uint32_t res;
113 } desc;
114 uint32_t immed[4];
115 } db;
116#define OHCI_STATUS_SHIFT 16
117#define OHCI_COUNT_MASK 0xffff
118#define OHCI_OUTPUT_MORE (0 << 28)
119#define OHCI_OUTPUT_LAST (1 << 28)
120#define OHCI_INPUT_MORE (2 << 28)
121#define OHCI_INPUT_LAST (3 << 28)
122#define OHCI_STORE_QUAD (4 << 28)
123#define OHCI_LOAD_QUAD (5 << 28)
124#define OHCI_NOP (6 << 28)
125#define OHCI_STOP (7 << 28)
126#define OHCI_STORE (8 << 28)
127#define OHCI_CMD_MASK (0xf << 28)
128
129#define OHCI_UPDATE (1 << 27)
130
131#define OHCI_KEY_ST0 (0 << 24)
132#define OHCI_KEY_ST1 (1 << 24)
133#define OHCI_KEY_ST2 (2 << 24)
134#define OHCI_KEY_ST3 (3 << 24)
135#define OHCI_KEY_REGS (5 << 24)
136#define OHCI_KEY_SYS (6 << 24)
137#define OHCI_KEY_DEVICE (7 << 24)
138#define OHCI_KEY_MASK (7 << 24)
139
140#define OHCI_INTERRUPT_NEVER (0 << 20)
141#define OHCI_INTERRUPT_TRUE (1 << 20)
142#define OHCI_INTERRUPT_FALSE (2 << 20)
143#define OHCI_INTERRUPT_ALWAYS (3 << 20)
144
145#define OHCI_BRANCH_NEVER (0 << 18)
146#define OHCI_BRANCH_TRUE (1 << 18)
147#define OHCI_BRANCH_FALSE (2 << 18)
148#define OHCI_BRANCH_ALWAYS (3 << 18)
149#define OHCI_BRANCH_MASK (3 << 18)
150
151#define OHCI_WAIT_NEVER (0 << 16)
152#define OHCI_WAIT_TRUE (1 << 16)
153#define OHCI_WAIT_FALSE (2 << 16)
154#define OHCI_WAIT_ALWAYS (3 << 16)
155};
156
157#define OHCI_SPD_S100 0x4
158#define OHCI_SPD_S200 0x1
159#define OHCI_SPD_S400 0x2
160
161
162#define FWOHCIEV_NOSTAT 0
163#define FWOHCIEV_LONGP 2
164#define FWOHCIEV_MISSACK 3
165#define FWOHCIEV_UNDRRUN 4
166#define FWOHCIEV_OVRRUN 5
167#define FWOHCIEV_DESCERR 6
168#define FWOHCIEV_DTRDERR 7
169#define FWOHCIEV_DTWRERR 8
170#define FWOHCIEV_BUSRST 9
171#define FWOHCIEV_TIMEOUT 0xa
172#define FWOHCIEV_TCODERR 0xb
173#define FWOHCIEV_UNKNOWN 0xe
174#define FWOHCIEV_FLUSHED 0xf
175#define FWOHCIEV_ACKCOMPL 0x11
176#define FWOHCIEV_ACKPEND 0x12
177#define FWOHCIEV_ACKBSX 0x14
178#define FWOHCIEV_ACKBSA 0x15
179#define FWOHCIEV_ACKBSB 0x16
180#define FWOHCIEV_ACKTARD 0x1b
181#define FWOHCIEV_ACKDERR 0x1d
182#define FWOHCIEV_ACKTERR 0x1e
183
184#define FWOHCIEV_MASK 0x1f
185
186struct ohci_dma {
187 fwohcireg_t cntl;
188
189#define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
190
191#define OHCI_CNTL_BUFFIL (0x1 << 31)
192#define OHCI_CNTL_ISOHDR (0x1 << 30)
193#define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
194#define OHCI_CNTL_MULTICH (0x1 << 28)
195
196#define OHCI_CNTL_DMA_RUN (0x1 << 15)
197#define OHCI_CNTL_DMA_WAKE (0x1 << 12)
198#define OHCI_CNTL_DMA_DEAD (0x1 << 11)
199#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10)
200#define OHCI_CNTL_DMA_BT (0x1 << 8)
201#define OHCI_CNTL_DMA_BAD (0x1 << 7)
202#define OHCI_CNTL_DMA_STAT (0xff)
203
204 fwohcireg_t cntl_clr;
205 fwohcireg_t dummy0;
206 fwohcireg_t cmd;
207 fwohcireg_t match;
208 fwohcireg_t dummy1;
209 fwohcireg_t dummy2;
210 fwohcireg_t dummy3;
211};
212
213struct ohci_itdma {
214 fwohcireg_t cntl;
215 fwohcireg_t cntl_clr;
216 fwohcireg_t dummy0;
217 fwohcireg_t cmd;
218};
219
220struct ohci_registers {
221 fwohcireg_t ver; /* Version No. 0x0 */
222 fwohcireg_t guid; /* GUID_ROM No. 0x4 */
223 fwohcireg_t retry; /* AT retries 0x8 */
224#define FWOHCI_RETRY 0x8
225 fwohcireg_t csr_data; /* CSR data 0xc */
226 fwohcireg_t csr_cmp; /* CSR compare 0x10 */
227 fwohcireg_t csr_cntl; /* CSR compare 0x14 */
228 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */
229 fwohcireg_t bus_id; /* BUS_ID 0x1c */
230 fwohcireg_t bus_opt; /* BUS option 0x20 */
231#define FWOHCIGUID_H 0x24
232#define FWOHCIGUID_L 0x28
233 fwohcireg_t guid_hi; /* GUID hi 0x24 */
234 fwohcireg_t guid_lo; /* GUID lo 0x28 */
235 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
236 fwohcireg_t config_rom; /* config ROM map 0x34 */
237 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
238 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
239 fwohcireg_t vendor; /* vendor ID 0x40 */
240 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
241 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
242 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
243#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */
244#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
245#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
246#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
247#define OHCI_HCC_LPS (1 << 19) /* LPS */
248#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */
249#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */
250#define OHCI_HCC_RESET (1 << 16) /* softReset */
251 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */
252 fwohcireg_t dummy3[1]; /* dummy 0x60 */
253 fwohcireg_t sid_buf; /* self id buffer 0x64 */
254 fwohcireg_t sid_cnt; /* self id count 0x68 */
255 fwohcireg_t dummy4[1]; /* dummy 0x6c */
256 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */
257 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */
258 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */
259 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */
260#define FWOHCI_INTSTAT 0x80
261#define FWOHCI_INTSTATCLR 0x84
262#define FWOHCI_INTMASK 0x88
263#define FWOHCI_INTMASKCLR 0x8c
264 fwohcireg_t int_stat; /* 0x80 */
265 fwohcireg_t int_clear; /* 0x84 */
266 fwohcireg_t int_mask; /* 0x88 */
267 fwohcireg_t int_mask_clear; /* 0x8c */
268 fwohcireg_t it_int_stat; /* 0x90 */
269 fwohcireg_t it_int_clear; /* 0x94 */
270 fwohcireg_t it_int_mask; /* 0x98 */
271 fwohcireg_t it_mask_clear; /* 0x9c */
272 fwohcireg_t ir_int_stat; /* 0xa0 */
273 fwohcireg_t ir_int_clear; /* 0xa4 */
274 fwohcireg_t ir_int_mask; /* 0xa8 */
275 fwohcireg_t ir_mask_clear; /* 0xac */
276 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */
277 fwohcireg_t fairness; /* fairness control 0xdc */
278 fwohcireg_t link_cntl; /* Chip control 0xe0*/
279 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
280#define FWOHCI_NODEID 0xe8
281 fwohcireg_t node; /* Node ID 0xe8 */
282#define OHCI_NODE_VALID (1U << 31)
283#define OHCI_NODE_ROOT (1 << 30)
284
285#define OHCI_ASYSRCBUS 1
286
287 fwohcireg_t phy_access; /* PHY cntl 0xec */
288#define PHYDEV_RDDONE (1<<31)
289#define PHYDEV_RDCMD (1<<15)
290#define PHYDEV_WRCMD (1<<14)
291#define PHYDEV_REGADDR 8
292#define PHYDEV_WRDATA 0
293#define PHYDEV_RDADDR 24
294#define PHYDEV_RDDATA 16
295
296 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */
297 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */
298 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */
299 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */
300 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */
301 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */
302 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
303 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
304 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
305 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
306
307 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
308
309 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
310
311 /* 0x180, 0x184, 0x188, 0x18c */
312 /* 0x190, 0x194, 0x198, 0x19c */
313 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */
314 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */
315 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */
316 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */
317 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */
318 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */
319 struct ohci_dma dma_ch[0x4];
320
321 /* 0x200, 0x204, 0x208, 0x20c */
322 /* 0x210, 0x204, 0x208, 0x20c */
323 struct ohci_itdma dma_itch[0x20];
324
325 /* 0x400, 0x404, 0x408, 0x40c */
326 /* 0x410, 0x404, 0x408, 0x40c */
327 struct ohci_dma dma_irch[0x20];
328};
329
330#ifndef _STANDALONE
331struct fwohcidb_tr {
332 STAILQ_ENTRY(fwohcidb_tr) link;
333 struct fw_xfer *xfer;
334 struct fwohcidb *db;
335 bus_dmamap_t dma_map;
336 caddr_t buf;
337 bus_addr_t bus_addr;
338 int dbcnt;
339};
340#endif
341
342/*
343 * OHCI info structure.
344 */
345struct fwohci_txpkthdr {
346 union {
347 uint32_t ld[4];
348 struct {
349#if BYTE_ORDER == BIG_ENDIAN
350 uint32_t spd:16, /* XXX include reserved field */
351 :8,
352 tcode:4,
353 :4;
354#else
355 uint32_t :4,
356 tcode:4,
357 :8,
358 spd:16; /* XXX include reserved fields */
359#endif
360 }common;
361 struct {
362#if BYTE_ORDER == BIG_ENDIAN
363 uint32_t :8,
364 srcbus:1,
365 :4,
366 spd:3,
367 tlrt:8,
368 tcode:4,
369 :4;
370#else
371 uint32_t :4,
372 tcode:4,
373 tlrt:8,
374 spd:3,
375 :4,
376 srcbus:1,
377 :8;
378#endif
379 BIT16x2(dst, );
380 } asycomm;
381 struct {
382#if BYTE_ORDER == BIG_ENDIAN
383 uint32_t :13,
384 spd:3,
385 chtag:8,
386 tcode:4,
387 sy:4;
388#else
389 uint32_t sy:4,
390 tcode:4,
391 chtag:8,
392 spd:3,
393 :13;
394#endif
395 BIT16x2(len, );
396 } stream;
397 } mode;
398};
399
400struct fwohci_trailer {
401#if BYTE_ORDER == BIG_ENDIAN
402 uint32_t stat:16,
403 time:16;
404#else
405 uint32_t time:16,
406 stat:16;
407#endif
408};
409
410#define OHCI_CNTL_CYCSRC (0x1 << 22)
411#define OHCI_CNTL_CYCMTR (0x1 << 21)
412#define OHCI_CNTL_CYCTIMER (0x1 << 20)
413#define OHCI_CNTL_PHYPKT (0x1 << 10)
414#define OHCI_CNTL_SID (0x1 << 9)
415
416/*
417 * defined in OHCI 1.1
418 * chapter 6.1
419 */
420#define OHCI_INT_DMA_ATRQ (0x1 << 0)
421#define OHCI_INT_DMA_ATRS (0x1 << 1)
422#define OHCI_INT_DMA_ARRQ (0x1 << 2)
423#define OHCI_INT_DMA_ARRS (0x1 << 3)
424#define OHCI_INT_DMA_PRRQ (0x1 << 4)
425#define OHCI_INT_DMA_PRRS (0x1 << 5)
426#define OHCI_INT_DMA_IT (0x1 << 6)
427#define OHCI_INT_DMA_IR (0x1 << 7)
428#define OHCI_INT_PW_ERR (0x1 << 8)
429#define OHCI_INT_LR_ERR (0x1 << 9)
430#define OHCI_INT_PHY_SID (0x1 << 16)
431#define OHCI_INT_PHY_BUS_R (0x1 << 17)
432#define OHCI_INT_REG_FAIL (0x1 << 18)
433#define OHCI_INT_PHY_INT (0x1 << 19)
434#define OHCI_INT_CYC_START (0x1 << 20)
435#define OHCI_INT_CYC_64SECOND (0x1 << 21)
436#define OHCI_INT_CYC_LOST (0x1 << 22)
437#define OHCI_INT_CYC_ERR (0x1 << 23)
438#define OHCI_INT_ERR (0x1 << 24)
439#define OHCI_INT_CYC_LONG (0x1 << 25)
440#define OHCI_INT_PHY_REG (0x1 << 26)
441#define OHCI_INT_EN (0x1 << 31)
442
443#define IP_CHANNELS 0x0234
444#define FWOHCI_MAXREC 2048
445
446#define OHCI_ISORA 0x02
447#define OHCI_ISORB 0x04
448
449#define FWOHCITCODE_PHY 0xe