1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2003 Hidetoshi Shimokawa
5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the acknowledgement as bellow:
18 *
19 * This product includes software developed by K. Kobayashi and H. Shimokawa
20 *
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 *
37 */
38
39#define STATE_CLEAR 0x0000
40#define STATE_SET 0x0004
41#define NODE_IDS 0x0008
42#define RESET_START 0x000c
43#define SPLIT_TIMEOUT_HI 0x0018
44#define SPLIT_TIMEOUT_LO 0x001c
45#define CYCLE_TIME 0x0200
46#define BUS_TIME 0x0204
47#define BUSY_TIMEOUT 0x0210
48#define PRIORITY_BUDGET 0x0218
49#define BUS_MGR_ID 0x021c
50#define BANDWIDTH_AV 0x0220
51#define CHANNELS_AV_HI 0x0224
52#define CHANNELS_AV_LO 0x0228
53#define IP_CHANNELS 0x0234
54
55#define CONF_ROM 0x0400
56
57#define TOPO_MAP 0x1000
58#define SPED_MAP 0x2000
59
60#define CSRTYPE_SHIFT 6
61#define CSRTYPE_MASK (3 << CSRTYPE_SHIFT)
62#define CSRTYPE_I (0 << CSRTYPE_SHIFT) /* Immediate */
63#define CSRTYPE_C (1 << CSRTYPE_SHIFT) /* CSR offset */
64#define CSRTYPE_L (2 << CSRTYPE_SHIFT) /* Leaf */
65#define CSRTYPE_D (3 << CSRTYPE_SHIFT) /* Directory */
66
67/*
68 * CSR keys
69 * 00 - 2F: defined by CSR architecture standards.
70 * 30 - 37: defined by BUS starndards
71 * 38 - 3F: defined by Vendor/Specifier
72 */
73#define CSRKEY_MASK 0x3f
74#define CSRKEY_DESC 0x01 /* Descriptor */
75#define CSRKEY_BDINFO 0x02 /* Bus_Dependent_Info */
76#define CSRKEY_VENDOR 0x03 /* Vendor */
77#define CSRKEY_HW 0x04 /* Hardware_Version */
78#define CSRKEY_MODULE 0x07 /* Module */
79#define CSRKEY_NCAP 0x0c /* Node_Capabilities */
80#define CSRKEY_EUI64 0x0d /* EUI_64 */
81#define CSRKEY_UNIT 0x11 /* Unit */
82#define CSRKEY_SPEC 0x12 /* Specifier_ID */
83#define CSRKEY_VER 0x13 /* Version */
84#define CSRKEY_DINFO 0x14 /* Dependent_Info */
85#define CSRKEY_ULOC 0x15 /* Unit_Location */
86#define CSRKEY_MODEL 0x17 /* Model */
87#define CSRKEY_INST 0x18 /* Instance */
88#define CSRKEY_KEYW 0x19 /* Keyword */
89#define CSRKEY_FEAT 0x1a /* Feature */
90#define CSRKEY_EROM 0x1b /* Extended_ROM */
91#define CSRKEY_EKSID 0x1c /* Extended_Key_Specifier_ID */
92#define CSRKEY_EKEY 0x1d /* Extended_Key */
93#define CSRKEY_EDATA 0x1e /* Extended_Data */
94#define CSRKEY_MDESC 0x1f /* Modifiable_Descriptor */
95#define CSRKEY_DID 0x20 /* Directory_ID */
96#define CSRKEY_REV 0x21 /* Revision */
97
98#define CSRKEY_FIRM_VER 0x3c /* Firmware version */
99#define CSRKEY_UNIT_CH 0x3a /* Unit characteristics */
100#define CSRKEY_COM_SPEC 0x38 /* Command set revision */
101#define CSRKEY_COM_SET 0x39 /* Command set */
102
103#define CROM_UDIR (CSRTYPE_D | CSRKEY_UNIT) /* 0x81 Unit directory */
104#define CROM_TEXTLEAF (CSRTYPE_L | CSRKEY_DESC) /* 0x81 Text leaf */
105#define CROM_LUN (CSRTYPE_I | CSRKEY_DINFO) /* 0x14 Logical unit num. */
106#define CROM_MGM (CSRTYPE_C | CSRKEY_DINFO) /* 0x54 Management agent */
107
108#define CSRVAL_VENDOR_PRIVATE 0xacde48
109#define CSRVAL_1394TA 0x00a02d
110#define CSRVAL_ANSIT10 0x00609e
111#define CSRVAL_IETF 0x00005e
112
113#define CSR_PROTAVC 0x010001
114#define CSR_PROTCAL 0x010002
115#define CSR_PROTEHS 0x010004
116#define CSR_PROTHAVI 0x010008
117#define CSR_PROTCAM104 0x000100
118#define CSR_PROTCAM120 0x000101
119#define CSR_PROTCAM130 0x000102
120#define CSR_PROTDPP 0x0a6be2
121#define CSR_PROTIICP 0x4b661f
122
123#define CSRVAL_T10SBP2 0x010483
124#define CSRVAL_SCSI 0x0104d8
125
126struct csrreg {
127#if BYTE_ORDER == BIG_ENDIAN
128 uint32_t key:8,
129 val:24;
130#else
131 uint32_t val:24,
132 key:8;
133#endif
134};
135struct csrhdr {
136#if BYTE_ORDER == BIG_ENDIAN
137 uint32_t info_len:8,
138 crc_len:8,
139 crc:16;
140#else
141 uint32_t crc:16,
142 crc_len:8,
143 info_len:8;
144#endif
145};
146struct csrdirectory {
147 BIT16x2(crc_len, crc);
148 struct csrreg entry[0];
149};
150struct csrtext {
151 BIT16x2(crc_len, crc);
152#if BYTE_ORDER == BIG_ENDIAN
153 uint32_t spec_type:8,
154 spec_id:24;
155#else
156 uint32_t spec_id:24,
157 spec_type:8;
158#endif
159 uint32_t lang_id;
160 uint32_t text[0];
161};
162
163struct bus_info {
164#define CSR_BUS_NAME_IEEE1394 0x31333934
165 uint32_t bus_name;
166#if BYTE_ORDER == BIG_ENDIAN
167 uint32_t irmc:1, /* iso. resource manager capable */
168 cmc:1, /* cycle master capable */
169 isc:1, /* iso. operation support */
170 bmc:1, /* bus manager capable */
171 pmc:1, /* power manager capable */
172 :3,
173 cyc_clk_acc:8, /* 0 <= ppm <= 100 */
174 max_rec:4, /* (2 << max_rec) bytes */
175 :2,
176 max_rom:2,
177 generation:4,
178 :1,
179 link_spd:3;
180#else
181 uint32_t link_spd:3,
182 :1,
183 generation:4,
184 max_rom:2,
185 :2,
186 max_rec:4, /* (2 << max_rec) bytes */
187 cyc_clk_acc:8, /* 0 <= ppm <= 100 */
188 :3,
189 pmc:1, /* power manager capable */
190 bmc:1, /* bus manager capable */
191 isc:1, /* iso. operation support */
192 cmc:1, /* cycle master capable */
193 irmc:1; /* iso. resource manager capable */
194#endif
195 struct fw_eui64 eui64;
196};
197/* max_rom */
198#define MAXROM_4 0
199#define MAXROM_64 1
200#define MAXROM_1024 2
201
202#define CROM_MAX_DEPTH 10
203struct crom_ptr {
204 struct csrdirectory *dir;
205 int index;
206};
207
208struct crom_context {
209 int depth;
210 struct crom_ptr stack[CROM_MAX_DEPTH];
211};
212
213void crom_init_context(struct crom_context *, uint32_t *);
214struct csrreg *crom_get(struct crom_context *);
215void crom_next(struct crom_context *);
216void crom_parse_text(struct crom_context *, char *, int);
217uint16_t crom_crc(uint32_t *r, int);
218struct csrreg *crom_search_key(struct crom_context *, uint8_t);
219int crom_has_specver(uint32_t *, uint32_t, uint32_t);
220
221#if !defined(_KERNEL) && !defined(_BOOT)
222char *crom_desc(struct crom_context *, char *, int);
223#endif
224
225/* For CROM build */
226#if defined(_KERNEL) || defined(_BOOT) || defined(TEST)
227#define CROM_MAX_CHUNK_LEN 20
228struct crom_src {
229 struct csrhdr hdr;
230 struct bus_info businfo;
231 STAILQ_HEAD(, crom_chunk) chunk_list;
232};
233
234struct crom_chunk {
235 STAILQ_ENTRY(crom_chunk) link;
236 struct crom_chunk *ref_chunk;
237 int ref_index;
238 int offset;
239 struct {
240 BIT16x2(crc_len, crc);
241 uint32_t buf[CROM_MAX_CHUNK_LEN];
242 } data;
243};
244
245extern int crom_add_quad(struct crom_chunk *, uint32_t);
246extern int crom_add_entry(struct crom_chunk *, int, int);
247extern int crom_add_chunk(struct crom_src *src, struct crom_chunk *,
248 struct crom_chunk *, int);
249extern int crom_add_simple_text(struct crom_src *src, struct crom_chunk *,
250 struct crom_chunk *, char *);
251extern int crom_load(struct crom_src *, uint32_t *, int);
252#endif