1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Ampere Computing LLC
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#ifndef _DEV_HWPMC_PMU_DMC620_REG_H_
29#define _DEV_HWPMC_PMU_DMC620_REG_H_
30
31#define DMC620_UNIT_PER_SOCKET 8
32#define DMC620_MAX_SOCKET 2
33#define DMC620_UNIT_MAX (DMC620_UNIT_PER_SOCKET * DMC620_MAX_SOCKET)
34
35#define DMC620_SNAPSHOT_REQ 0x000 /* WO */
36#define DMC620_SNAPSHOT_ACK 0x004 /* RO */
37#define DMC620_OVERFLOW_STATUS_CLKDIV2 0x008 /* RW */
38#define DMC620_OVERFLOW_STATUS_CLK 0x00C /* RW */
39
40#define DMC620_COUNTER_MASK_LO 0x000 /* RW */
41#define DMC620_COUNTER_MASK_HI 0x004 /* RW */
42#define DMC620_COUNTER_MATCH_LO 0x008 /* RW */
43#define DMC620_COUNTER_MATCH_HI 0x00C /* RW */
44#define DMC620_COUNTER_CONTROL 0x010 /* RW */
45#define DMC620_COUNTER_CONTROL_ENABLE (1 << 0)
46#define DMC620_COUNTER_CONTROL_INVERT (1 << 1)
47#define DMC620_COUNTER_CONTROL_EVENT_SHIFT 2
48#define DMC620_COUNTER_CONTROL_EVENT_MASK (0x1f << 2)
49#define DMC620_COUNTER_CONTROL_INCR_SHIFT 7
50#define DMC620_COUNTER_CONTROL_INCR_MASK (0x3 << 7)
51#define DMC620_COUNTER_SNAPSHOT_VALUE_LO 0x018 /* RO */
52#define DMC620_COUNTER_VALUE_LO 0x020 /* RW */
53
54#define DMC620_CLKDIV2_COUNTERS_BASE 0x010
55#define DMC620_CLKDIV2_COUNTERS_OFF 0x28
56#define DMC620_CLKDIV2_COUNTERS_N 8
57#define DMC620_CLKDIV2_REG(u, r) (DMC620_CLKDIV2_COUNTERS_BASE + \
58 (DMC620_CLKDIV2_COUNTERS_OFF * (u)) + (r))
59
60#define DMC620_CLK_COUNTERS_BASE 0x150
61#define DMC620_CLK_COUNTERS_OFF 0x28
62#define DMC620_CLK_COUNTERS_N 2
63#define DMC620_CLK_REG(u, r) (DMC620_CLK_COUNTERS_BASE + \
64 (DMC620_CLK_COUNTERS_OFF * (u)) + (r))
65
66/* CLK counters continue registers set. */
67#define DMC620_REG(u, r) (DMC620_CLKDIV2_COUNTERS_BASE + \
68 (DMC620_CLKDIV2_COUNTERS_OFF * (u)) + (r))
69
70#define DMC620_PMU_DEFAULT_UNITS_N 8
71
72#define DMC620_COUNTERS_N (DMC620_CLKDIV2_COUNTERS_N + \
73 DMC620_CLK_COUNTERS_N)
74
75/* IO from HWPMC module to driver. */
76uint32_t pmu_dmc620_rd4(void *arg, u_int cntr, off_t reg);
77void pmu_dmc620_wr4(void *arg, u_int cntr, off_t reg, uint32_t val);
78
79/* Driver's interrupt notification to HWPMC module. */
80int dmc620_intr(struct trapframe *tf, int c, int unit, int ri);
81
82/* Registration of counters pool. */
83void dmc620_pmc_register(int unit, void *argi, int domain);
84void dmc620_pmc_unregister(int unit);
85
86#endif /*_DEV_HWPMC_PMU_DMC620_REG_H_ */